1 //===-- SparcInternals.h ----------------------------------------*- C++ -*-===//
3 // This file defines stuff that is to be private to the Sparc backend, but is
4 // shared among different portions of the backend.
6 //===----------------------------------------------------------------------===//
8 #ifndef SPARC_INTERNALS_H
9 #define SPARC_INTERNALS_H
11 #include "llvm/CodeGen/MachineInstrBuilder.h"
12 #include "llvm/Target/TargetMachine.h"
13 #include "llvm/Target/TargetSchedInfo.h"
14 #include "llvm/Target/TargetFrameInfo.h"
15 #include "llvm/Target/TargetCacheInfo.h"
16 #include "llvm/Target/TargetRegInfo.h"
17 #include "llvm/Target/TargetOptInfo.h"
18 #include "llvm/Type.h"
19 #include "SparcRegClassInfo.h"
20 #include <sys/types.h>
27 enum SparcInstrSchedClass {
28 SPARC_NONE, /* Instructions with no scheduling restrictions */
29 SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
30 SPARC_IEU0, /* Integer class IEU0 */
31 SPARC_IEU1, /* Integer class IEU1 */
32 SPARC_FPM, /* FP Multiply or Divide instructions */
33 SPARC_FPA, /* All other FP instructions */
34 SPARC_CTI, /* Control-transfer instructions */
35 SPARC_LD, /* Load instructions */
36 SPARC_ST, /* Store instructions */
37 SPARC_SINGLE, /* Instructions that must issue by themselves */
39 SPARC_INV, /* This should stay at the end for the next value */
40 SPARC_NUM_SCHED_CLASSES = SPARC_INV
44 //---------------------------------------------------------------------------
45 // enum SparcMachineOpCode.
46 // const TargetInstrDescriptor SparcMachineInstrDesc[]
49 // Description of UltraSparc machine instructions.
51 //---------------------------------------------------------------------------
54 enum SparcMachineOpCode {
55 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
56 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
58 #include "SparcInstr.def"
60 // End-of-array marker
62 NUM_REAL_OPCODES = PHI, // number of valid opcodes
63 NUM_TOTAL_OPCODES = INVALID_OPCODE
68 // Array of machine instruction descriptions...
69 extern const TargetInstrDescriptor SparcMachineInstrDesc[];
72 //---------------------------------------------------------------------------
73 // class UltraSparcInstrInfo
76 // Information about individual instructions.
77 // Most information is stored in the SparcMachineInstrDesc array above.
78 // Other information is computed on demand, and most such functions
79 // default to member functions in base class TargetInstrInfo.
80 //---------------------------------------------------------------------------
82 struct UltraSparcInstrInfo : public TargetInstrInfo {
83 UltraSparcInstrInfo();
86 // All immediate constants are in position 1 except the
87 // store instructions and SETxx.
89 virtual int getImmedConstantPos(MachineOpCode opCode) const {
91 if (this->maxImmedConstant(opCode, ignore) != 0) {
93 assert(! this->isStore((MachineOpCode) V9::STB - 1));
95 assert(! this->isStore((MachineOpCode) V9::STXFSR + 1));
97 if (opCode == V9::SETSW || opCode == V9::SETUW ||
98 opCode == V9::SETX || opCode == V9::SETHI)
100 if (opCode >= V9::STB && opCode <= V9::STXFSR)
108 /// createNOPinstr - returns the target's implementation of NOP, which is
109 /// usually a pseudo-instruction, implemented by a degenerate version of
110 /// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi g0, 0
112 MachineInstr* createNOPinstr() const {
113 return BuildMI(V9::SETHI, 2).addReg(SparcIntRegClass::g0).addZImm(0);
116 /// isNOPinstr - not having a special NOP opcode, we need to know if a given
117 /// instruction is interpreted as an `official' NOP instr, i.e., there may be
118 /// more than one way to `do nothing' but only one canonical way to slack off.
120 bool isNOPinstr(const MachineInstr &MI) const {
121 // Make sure the instruction is EXACTLY `sethi g0, 0'
122 if (MI.getOpcode() == V9::SETHI && MI.getNumOperands() == 2) {
123 const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
124 if (op0.isMachineRegister() &&
125 op0.getMachineRegNum() == SparcIntRegClass::g0 &&
126 op1.isImmediate() && op1.getImmedValue() == 0)
134 virtual bool hasResultInterlock(MachineOpCode opCode) const
136 // All UltraSPARC instructions have interlocks (note that delay slots
137 // are not considered here).
138 // However, instructions that use the result of an FCMP produce a
139 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
140 // Force the compiler to insert a software interlock (i.e., gap of
141 // 2 other groups, including NOPs if necessary).
142 return (opCode == V9::FCMPS || opCode == V9::FCMPD || opCode == V9::FCMPQ);
145 //-------------------------------------------------------------------------
146 // Queries about representation of LLVM quantities (e.g., constants)
147 //-------------------------------------------------------------------------
149 virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
150 const Instruction* I) const;
152 //-------------------------------------------------------------------------
153 // Code generation support for creating individual machine instructions
154 //-------------------------------------------------------------------------
156 // Get certain common op codes for the current target. This and all the
157 // Create* methods below should be moved to a machine code generation class
159 virtual MachineOpCode getNOPOpCode() const { return V9::NOP; }
161 // Create an instruction sequence to put the constant `val' into
162 // the virtual register `dest'. `val' may be a Constant or a
163 // GlobalValue, viz., the constant address of a global variable or function.
164 // The generated instructions are returned in `mvec'.
165 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
166 // Any stack space required is allocated via mcff.
168 virtual void CreateCodeToLoadConst(const TargetMachine& target,
172 std::vector<MachineInstr*>& mvec,
173 MachineCodeForInstruction& mcfi) const;
175 // Create an instruction sequence to copy an integer value `val'
176 // to a floating point value `dest' by copying to memory and back.
177 // val must be an integral type. dest must be a Float or Double.
178 // The generated instructions are returned in `mvec'.
179 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
180 // Any stack space required is allocated via mcff.
182 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
186 std::vector<MachineInstr*>& mvec,
187 MachineCodeForInstruction& mcfi) const;
189 // Similarly, create an instruction sequence to copy an FP value
190 // `val' to an integer value `dest' by copying to memory and back.
191 // The generated instructions are returned in `mvec'.
192 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
193 // Any stack space required is allocated via mcff.
195 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
199 std::vector<MachineInstr*>& mvec,
200 MachineCodeForInstruction& mcfi) const;
202 // Create instruction(s) to copy src to dest, for arbitrary types
203 // The generated instructions are returned in `mvec'.
204 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
205 // Any stack space required is allocated via mcff.
207 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
211 std::vector<MachineInstr*>& mvec,
212 MachineCodeForInstruction& mcfi) const;
214 // Create instruction sequence to produce a sign-extended register value
215 // from an arbitrary sized value (sized in bits, not bytes).
216 // The generated instructions are appended to `mvec'.
217 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
218 // Any stack space required is allocated via mcff.
220 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
224 unsigned int numLowBits,
225 std::vector<MachineInstr*>& mvec,
226 MachineCodeForInstruction& mcfi) const;
228 // Create instruction sequence to produce a zero-extended register value
229 // from an arbitrary sized value (sized in bits, not bytes).
230 // The generated instructions are appended to `mvec'.
231 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
232 // Any stack space required is allocated via mcff.
234 virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
238 unsigned int numLowBits,
239 std::vector<MachineInstr*>& mvec,
240 MachineCodeForInstruction& mcfi) const;
244 //----------------------------------------------------------------------------
245 // class UltraSparcRegInfo
247 // This class implements the virtual class TargetRegInfo for Sparc.
249 //----------------------------------------------------------------------------
251 class UltraSparcRegInfo : public TargetRegInfo {
252 // The actual register classes in the Sparc
255 IntRegClassID, // Integer
256 FloatRegClassID, // Float (both single/double)
257 IntCCRegClassID, // Int Condition Code
258 FloatCCRegClassID // Float Condition code
262 // Type of registers available in Sparc. There can be several reg types
263 // in the same class. For instace, the float reg class has Single/Double
274 // **** WARNING: If the above enum order is changed, also modify
275 // getRegisterClassOfValue method below since it assumes this particular
276 // order for efficiency.
279 // Number of registers used for passing int args (usually 6: %o0 - %o5)
281 unsigned const NumOfIntArgRegs;
283 // Number of registers used for passing float args (usually 32: %f0 - %f31)
285 unsigned const NumOfFloatArgRegs;
287 // An out of bound register number that can be used to initialize register
288 // numbers. Useful for error detection.
290 int const InvalidRegNum;
293 // ======================== Private Methods =============================
295 // The following methods are used to color special live ranges (e.g.
296 // function args and return values etc.) with specific hardware registers
297 // as required. See SparcRegInfo.cpp for the implementation.
299 void suggestReg4RetAddr(MachineInstr *RetMI,
300 LiveRangeInfo &LRI) const;
302 void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI) const;
304 void InitializeOutgoingArg(MachineInstr* CallMI, AddedInstrns *CallAI,
305 PhyRegAlloc &PRA, LiveRange* LR,
306 unsigned regType, unsigned RegClassID,
307 int UniArgReg, unsigned int argNo,
308 std::vector<MachineInstr *>& AddedInstrnsBefore)
311 int getRegType(const Type* type) const;
312 int getRegType(const LiveRange *LR) const;
313 int getRegType(int unifiedRegNum) const;
315 // Used to generate a copy instruction based on the register class of
318 MachineInstr *cpValue2RegMI(Value *Val, unsigned DestReg,
322 // The following 2 methods are used to order the instructions addeed by
323 // the register allocator in association with function calling. See
324 // SparcRegInfo.cpp for more details
326 void moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
327 MachineInstr *UnordInst,
328 PhyRegAlloc &PRA) const;
330 void OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
331 std::vector<MachineInstr *> &OrdVec,
332 PhyRegAlloc &PRA) const;
335 // Compute which register can be used for an argument, if any
337 int regNumForIntArg(bool inCallee, bool isVarArgsCall,
338 unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
339 unsigned& regClassId) const;
341 int regNumForFPArg(unsigned RegType, bool inCallee, bool isVarArgsCall,
342 unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
343 unsigned& regClassId) const;
346 UltraSparcRegInfo(const UltraSparc &tgt);
348 // To find the register class used for a specified Type
350 unsigned getRegClassIDOfType(const Type *type,
351 bool isCCReg = false) const;
353 // To find the register class to which a specified register belongs
355 unsigned getRegClassIDOfReg(int unifiedRegNum) const;
356 unsigned getRegClassIDOfRegType(int regType) const;
358 // getZeroRegNum - returns the register that contains always zero this is the
359 // unified register number
361 virtual int getZeroRegNum() const;
363 // getCallAddressReg - returns the reg used for pushing the address when a
364 // function is called. This can be used for other purposes between calls
366 unsigned getCallAddressReg() const;
368 // Returns the register containing the return address.
369 // It should be made sure that this register contains the return
370 // value when a return instruction is reached.
372 unsigned getReturnAddressReg() const;
374 // Number of registers used for passing int args (usually 6: %o0 - %o5)
375 // and float args (usually 32: %f0 - %f31)
377 unsigned const GetNumOfIntArgRegs() const { return NumOfIntArgRegs; }
378 unsigned const GetNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
380 // The following methods are used to color special live ranges (e.g.
381 // function args and return values etc.) with specific hardware registers
382 // as required. See SparcRegInfo.cpp for the implementation for Sparc.
384 void suggestRegs4MethodArgs(const Function *Meth,
385 LiveRangeInfo& LRI) const;
387 void suggestRegs4CallArgs(MachineInstr *CallMI,
388 LiveRangeInfo& LRI) const;
390 void suggestReg4RetValue(MachineInstr *RetMI,
391 LiveRangeInfo& LRI) const;
393 void colorMethodArgs(const Function *Meth, LiveRangeInfo &LRI,
394 AddedInstrns *FirstAI) const;
396 void colorCallArgs(MachineInstr *CallMI, LiveRangeInfo &LRI,
397 AddedInstrns *CallAI, PhyRegAlloc &PRA,
398 const BasicBlock *BB) const;
400 void colorRetValue(MachineInstr *RetI, LiveRangeInfo& LRI,
401 AddedInstrns *RetAI) const;
404 // method used for printing a register for debugging purposes
406 static void printReg(const LiveRange *LR);
408 // Each register class has a seperate space for register IDs. To convert
409 // a regId in a register class to a common Id, or vice versa,
410 // we use the folloing methods.
412 // This method provides a unique number for each register
413 inline int getUnifiedRegNum(unsigned regClassID, int reg) const {
415 if (regClassID == IntRegClassID) {
416 assert(reg < 32 && "Invalid reg. number");
419 else if (regClassID == FloatRegClassID) {
420 assert(reg < 64 && "Invalid reg. number");
421 return reg + 32; // we have 32 int regs
423 else if (regClassID == FloatCCRegClassID) {
424 assert(reg < 4 && "Invalid reg. number");
425 return reg + 32 + 64; // 32 int, 64 float
427 else if (regClassID == IntCCRegClassID ) {
428 assert(reg == 0 && "Invalid reg. number");
429 return reg + 4+ 32 + 64; // only one int CC reg
431 else if (reg==InvalidRegNum) {
432 return InvalidRegNum;
435 assert(0 && "Invalid register class");
439 // This method converts the unified number to the number in its class,
440 // and returns the class ID in regClassID.
441 inline int getClassRegNum(int ureg, unsigned& regClassID) const {
442 if (ureg < 32) { regClassID = IntRegClassID; return ureg; }
443 else if (ureg < 32+64) { regClassID = FloatRegClassID; return ureg-32; }
444 else if (ureg < 4 +96) { regClassID = FloatCCRegClassID; return ureg-96; }
445 else if (ureg < 1 +100) { regClassID = IntCCRegClassID; return ureg-100;}
446 else if (ureg == InvalidRegNum) { return InvalidRegNum; }
447 else { assert(0 && "Invalid unified register number"); }
451 // Returns the assembly-language name of the specified machine register.
453 virtual const char * const getUnifiedRegName(int reg) const;
456 // returns the # of bytes of stack space allocated for each register
457 // type. For Sparc, currently we allocate 8 bytes on stack for all
458 // register types. We can optimize this later if necessary to save stack
459 // space (However, should make sure that stack alignment is correct)
461 inline int getSpilledRegSize(int RegType) const {
466 // To obtain the return value and the indirect call address (if any)
467 // contained in a CALL machine instruction
469 const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
470 const Value * getCallInstIndirectAddrVal(const MachineInstr *CallMI) const;
472 // The following methods are used to generate "copy" machine instructions
473 // for an architecture.
475 // The function regTypeNeedsScratchReg() can be used to check whether a
476 // scratch register is needed to copy a register of type `regType' to
477 // or from memory. If so, such a scratch register can be provided by
478 // the caller (e.g., if it knows which regsiters are free); otherwise
479 // an arbitrary one will be chosen and spilled by the copy instructions.
481 bool regTypeNeedsScratchReg(int RegType,
482 int& scratchRegClassId) const;
484 void cpReg2RegMI(std::vector<MachineInstr*>& mvec,
485 unsigned SrcReg, unsigned DestReg,
488 void cpReg2MemMI(std::vector<MachineInstr*>& mvec,
489 unsigned SrcReg, unsigned DestPtrReg,
490 int Offset, int RegType, int scratchReg = -1) const;
492 void cpMem2RegMI(std::vector<MachineInstr*>& mvec,
493 unsigned SrcPtrReg, int Offset, unsigned DestReg,
494 int RegType, int scratchReg = -1) const;
496 void cpValue2Value(Value *Src, Value *Dest,
497 std::vector<MachineInstr*>& mvec) const;
499 // To see whether a register is a volatile (i.e., whehter it must be
500 // preserved acorss calls)
502 inline bool isRegVolatile(int RegClassID, int Reg) const {
503 return MachineRegClassArr[RegClassID]->isRegVolatile(Reg);
507 virtual unsigned getFramePointer() const;
508 virtual unsigned getStackPointer() const;
510 virtual int getInvalidRegNum() const {
511 return InvalidRegNum;
514 // This method inserts the caller saving code for call instructions
516 void insertCallerSavingCode(std::vector<MachineInstr*>& instrnsBefore,
517 std::vector<MachineInstr*>& instrnsAfter,
519 const BasicBlock *BB, PhyRegAlloc &PRA ) const;
525 //---------------------------------------------------------------------------
526 // class UltraSparcSchedInfo
529 // Interface to instruction scheduling information for UltraSPARC.
530 // The parameter values above are based on UltraSPARC IIi.
531 //---------------------------------------------------------------------------
534 class UltraSparcSchedInfo: public TargetSchedInfo {
536 UltraSparcSchedInfo(const TargetMachine &tgt);
538 virtual void initializeResources();
542 //---------------------------------------------------------------------------
543 // class UltraSparcFrameInfo
546 // Interface to stack frame layout info for the UltraSPARC.
547 // Starting offsets for each area of the stack frame are aligned at
548 // a multiple of getStackFrameSizeAlignment().
549 //---------------------------------------------------------------------------
551 class UltraSparcFrameInfo: public TargetFrameInfo {
552 const TargetMachine ⌖
554 UltraSparcFrameInfo(const TargetMachine &TM)
555 : TargetFrameInfo(StackGrowsDown, StackFrameSizeAlignment, 0), target(TM) {}
558 // These methods provide constant parameters of the frame layout.
560 int getStackFrameSizeAlignment() const { return StackFrameSizeAlignment;}
561 int getMinStackFrameSize() const { return MinStackFrameSize; }
562 int getNumFixedOutgoingArgs() const { return NumFixedOutgoingArgs; }
563 int getSizeOfEachArgOnStack() const { return SizeOfEachArgOnStack; }
564 bool argsOnStackHaveFixedSize() const { return true; }
566 // This method adjusts a stack offset to meet alignment rules of target.
567 // The fixed OFFSET (0x7ff) must be subtracted and the result aligned.
568 virtual int adjustAlignment (int unalignedOffset,
570 unsigned int align) const {
571 return unalignedOffset + (growUp? +1:-1)*((unalignedOffset-OFFSET) % align);
574 // These methods compute offsets using the frame contents for a
575 // particular function. The frame contents are obtained from the
576 // MachineCodeInfoForMethod object for the given function.
578 int getFirstIncomingArgOffset (MachineFunction& mcInfo,
581 growUp = true; // arguments area grows upwards
582 return FirstIncomingArgOffsetFromFP;
584 int getFirstOutgoingArgOffset (MachineFunction& mcInfo,
587 growUp = true; // arguments area grows upwards
588 return FirstOutgoingArgOffsetFromSP;
590 int getFirstOptionalOutgoingArgOffset(MachineFunction& mcInfo,
593 growUp = true; // arguments area grows upwards
594 return FirstOptionalOutgoingArgOffsetFromSP;
597 int getFirstAutomaticVarOffset (MachineFunction& mcInfo,
599 int getRegSpillAreaOffset (MachineFunction& mcInfo,
601 int getTmpAreaOffset (MachineFunction& mcInfo,
603 int getDynamicAreaOffset (MachineFunction& mcInfo,
607 // These methods specify the base register used for each stack area
608 // (generally FP or SP)
610 virtual int getIncomingArgBaseRegNum() const {
611 return (int) target.getRegInfo().getFramePointer();
613 virtual int getOutgoingArgBaseRegNum() const {
614 return (int) target.getRegInfo().getStackPointer();
616 virtual int getOptionalOutgoingArgBaseRegNum() const {
617 return (int) target.getRegInfo().getStackPointer();
619 virtual int getAutomaticVarBaseRegNum() const {
620 return (int) target.getRegInfo().getFramePointer();
622 virtual int getRegSpillAreaBaseRegNum() const {
623 return (int) target.getRegInfo().getFramePointer();
625 virtual int getDynamicAreaBaseRegNum() const {
626 return (int) target.getRegInfo().getStackPointer();
629 virtual int getIncomingArgOffset(MachineFunction& mcInfo,
630 unsigned argNum) const {
631 assert(argsOnStackHaveFixedSize());
633 unsigned relativeOffset = argNum * getSizeOfEachArgOnStack();
634 bool growUp; // do args grow up or down
635 int firstArg = getFirstIncomingArgOffset(mcInfo, growUp);
636 return growUp ? firstArg + relativeOffset : firstArg - relativeOffset;
639 virtual int getOutgoingArgOffset(MachineFunction& mcInfo,
640 unsigned argNum) const {
641 assert(argsOnStackHaveFixedSize());
642 //assert(((int) argNum - this->getNumFixedOutgoingArgs())
643 // <= (int) mcInfo.getInfo()->getMaxOptionalNumArgs());
645 unsigned relativeOffset = argNum * getSizeOfEachArgOnStack();
646 bool growUp; // do args grow up or down
647 int firstArg = getFirstOutgoingArgOffset(mcInfo, growUp);
648 return growUp ? firstArg + relativeOffset : firstArg - relativeOffset;
652 /*----------------------------------------------------------------------
653 This diagram shows the stack frame layout used by llc on Sparc V9.
654 Note that only the location of automatic variables, spill area,
655 temporary storage, and dynamically allocated stack area are chosen
656 by us. The rest conform to the Sparc V9 ABI.
657 All stack addresses are offset by OFFSET = 0x7ff (2047).
659 Alignment assumptions and other invariants:
660 (1) %sp+OFFSET and %fp+OFFSET are always aligned on 16-byte boundary
661 (2) Variables in automatic, spill, temporary, or dynamic regions
662 are aligned according to their size as in all memory accesses.
663 (3) Everything below the dynamically allocated stack area is only used
664 during a call to another function, so it is never needed when
665 the current function is active. This is why space can be allocated
666 dynamically by incrementing %sp any time within the function.
671 %fp+OFFSET+176 Optional extra incoming arguments# 1..N
672 %fp+OFFSET+168 Incoming argument #6
674 %fp+OFFSET+128 Incoming argument #1
676 ---%fp+OFFSET-0--------Bottom of caller's stack frame--------------------
677 %fp+OFFSET-8 Automatic variables <-- ****TOP OF STACK FRAME****
682 %sp+OFFSET+176+8N Bottom of dynamically allocated stack area
683 %sp+OFFSET+168+8N Optional extra outgoing argument# N
685 %sp+OFFSET+176 Optional extra outgoing argument# 1
686 %sp+OFFSET+168 Outgoing argument #6
688 %sp+OFFSET+128 Outgoing argument #1
689 %sp+OFFSET+120 Save area for %i7
691 %sp+OFFSET+0 Save area for %l0 <-- ****BOTTOM OF STACK FRAME****
693 *----------------------------------------------------------------------*/
695 // All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
696 static const int OFFSET = (int) 0x7ff;
697 static const int StackFrameSizeAlignment = 16;
698 static const int MinStackFrameSize = 176;
699 static const int NumFixedOutgoingArgs = 6;
700 static const int SizeOfEachArgOnStack = 8;
701 static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
702 static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
703 static const int StaticAreaOffsetFromFP = 0 + OFFSET;
704 static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
705 static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
709 //---------------------------------------------------------------------------
710 // class UltraSparcCacheInfo
713 // Interface to cache parameters for the UltraSPARC.
714 // Just use defaults for now.
715 //---------------------------------------------------------------------------
717 struct UltraSparcCacheInfo: public TargetCacheInfo {
718 UltraSparcCacheInfo(const TargetMachine &T) : TargetCacheInfo(T) {}
722 //---------------------------------------------------------------------------
723 // class UltraSparcOptInfo
726 // Interface to machine-level optimization routines for the UltraSPARC.
727 //---------------------------------------------------------------------------
729 struct UltraSparcOptInfo: public TargetOptInfo {
730 UltraSparcOptInfo(const TargetMachine &T) : TargetOptInfo(T) {}
732 virtual bool IsUselessCopy (const MachineInstr* MI) const;
735 //---------------------------------------------------------------------------
736 // class UltraSparcMachine
739 // Primary interface to machine description for the UltraSPARC.
740 // Primarily just initializes machine-dependent parameters in
741 // class TargetMachine, and creates machine-dependent subclasses
742 // for classes such as InstrInfo, SchedInfo and RegInfo.
743 //---------------------------------------------------------------------------
745 class UltraSparc : public TargetMachine {
746 UltraSparcInstrInfo instrInfo;
747 UltraSparcSchedInfo schedInfo;
748 UltraSparcRegInfo regInfo;
749 UltraSparcFrameInfo frameInfo;
750 UltraSparcCacheInfo cacheInfo;
751 UltraSparcOptInfo optInfo;
755 virtual const TargetInstrInfo &getInstrInfo() const { return instrInfo; }
756 virtual const TargetSchedInfo &getSchedInfo() const { return schedInfo; }
757 virtual const TargetRegInfo &getRegInfo() const { return regInfo; }
758 virtual const TargetFrameInfo &getFrameInfo() const { return frameInfo; }
759 virtual const TargetCacheInfo &getCacheInfo() const { return cacheInfo; }
760 virtual const TargetOptInfo &getOptInfo() const { return optInfo; }
762 virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
764 // getPrologEpilogInsertionPass - Inserts prolog/epilog code.
765 Pass* getPrologEpilogInsertionPass();
767 // getFunctionAsmPrinterPass - Writes out machine code for a single function
768 Pass* getFunctionAsmPrinterPass(std::ostream &Out);
770 // getModuleAsmPrinterPass - Writes generated machine code to assembly file.
771 Pass* getModuleAsmPrinterPass(std::ostream &Out);
773 // getEmitBytecodeToAsmPass - Emits final LLVM bytecode to assembly file.
774 Pass* getEmitBytecodeToAsmPass(std::ostream &Out);
777 int64_t GetConstantValueAsSignedInt(const Value *V, bool &isValidConstant);