1 //===-- SparcInternals.h ----------------------------------------*- C++ -*-===//
3 // This file defines stuff that is to be private to the Sparc backend, but is
4 // shared among different portions of the backend.
6 //===----------------------------------------------------------------------===//
8 #ifndef SPARC_INTERNALS_H
9 #define SPARC_INTERNALS_H
11 #include "llvm/Target/TargetMachine.h"
12 #include "llvm/Target/MachineSchedInfo.h"
13 #include "llvm/Target/MachineFrameInfo.h"
14 #include "llvm/Target/MachineCacheInfo.h"
15 #include "llvm/Target/MachineRegInfo.h"
16 #include "llvm/Target/MachineOptInfo.h"
17 #include "llvm/Type.h"
18 #include <sys/types.h>
25 // OpCodeMask definitions for the Sparc V9
27 const OpCodeMask Immed = 0x00002000; // immed or reg operand?
28 const OpCodeMask Annul = 0x20000000; // annul delay instr?
29 const OpCodeMask PredictTaken = 0x00080000; // predict branch taken?
32 enum SparcInstrSchedClass {
33 SPARC_NONE, /* Instructions with no scheduling restrictions */
34 SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
35 SPARC_IEU0, /* Integer class IEU0 */
36 SPARC_IEU1, /* Integer class IEU1 */
37 SPARC_FPM, /* FP Multiply or Divide instructions */
38 SPARC_FPA, /* All other FP instructions */
39 SPARC_CTI, /* Control-transfer instructions */
40 SPARC_LD, /* Load instructions */
41 SPARC_ST, /* Store instructions */
42 SPARC_SINGLE, /* Instructions that must issue by themselves */
44 SPARC_INV, /* This should stay at the end for the next value */
45 SPARC_NUM_SCHED_CLASSES = SPARC_INV
49 //---------------------------------------------------------------------------
50 // enum SparcMachineOpCode.
51 // const MachineInstrDescriptor SparcMachineInstrDesc[]
54 // Description of UltraSparc machine instructions.
56 //---------------------------------------------------------------------------
58 enum SparcMachineOpCode {
59 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
60 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
62 #include "SparcInstr.def"
64 // End-of-array marker
66 NUM_REAL_OPCODES = PHI, // number of valid opcodes
67 NUM_TOTAL_OPCODES = INVALID_OPCODE
71 // Array of machine instruction descriptions...
72 extern const MachineInstrDescriptor SparcMachineInstrDesc[];
75 //---------------------------------------------------------------------------
76 // class UltraSparcInstrInfo
79 // Information about individual instructions.
80 // Most information is stored in the SparcMachineInstrDesc array above.
81 // Other information is computed on demand, and most such functions
82 // default to member functions in base class MachineInstrInfo.
83 //---------------------------------------------------------------------------
85 struct UltraSparcInstrInfo : public MachineInstrInfo {
86 UltraSparcInstrInfo(const TargetMachine& tgt);
89 // All immediate constants are in position 1 except the
90 // store instructions and SETxx.
92 virtual int getImmedConstantPos(MachineOpCode opCode) const {
94 if (this->maxImmedConstant(opCode, ignore) != 0)
96 assert(! this->isStore((MachineOpCode) STB - 1)); // 1st store opcode
97 assert(! this->isStore((MachineOpCode) STXFSR+1));// last store opcode
98 if (opCode==SETSW || opCode==SETUW || opCode==SETX || opCode==SETHI)
100 if (opCode >= STB && opCode <= STXFSR)
108 virtual bool hasResultInterlock (MachineOpCode opCode) const
110 // All UltraSPARC instructions have interlocks (note that delay slots
111 // are not considered here).
112 // However, instructions that use the result of an FCMP produce a
113 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
114 // Force the compiler to insert a software interlock (i.e., gap of
115 // 2 other groups, including NOPs if necessary).
116 return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
119 //-------------------------------------------------------------------------
120 // Queries about representation of LLVM quantities (e.g., constants)
121 //-------------------------------------------------------------------------
123 virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
124 const Instruction* I) const;
126 //-------------------------------------------------------------------------
127 // Code generation support for creating individual machine instructions
128 //-------------------------------------------------------------------------
130 // Get certain common op codes for the current target. This and all the
131 // Create* methods below should be moved to a machine code generation class
133 virtual MachineOpCode getNOPOpCode() const { return NOP; }
135 // Create an instruction sequence to put the constant `val' into
136 // the virtual register `dest'. `val' may be a Constant or a
137 // GlobalValue, viz., the constant address of a global variable or function.
138 // The generated instructions are returned in `mvec'.
139 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
140 // Any stack space required is allocated via mcff.
142 virtual void CreateCodeToLoadConst(const TargetMachine& target,
146 std::vector<MachineInstr*>& mvec,
147 MachineCodeForInstruction& mcfi) const;
149 // Create an instruction sequence to copy an integer value `val'
150 // to a floating point value `dest' by copying to memory and back.
151 // val must be an integral type. dest must be a Float or Double.
152 // The generated instructions are returned in `mvec'.
153 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
154 // Any stack space required is allocated via mcff.
156 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
160 std::vector<MachineInstr*>& mvec,
161 MachineCodeForInstruction& mcfi) const;
163 // Similarly, create an instruction sequence to copy an FP value
164 // `val' to an integer value `dest' by copying to memory and back.
165 // The generated instructions are returned in `mvec'.
166 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
167 // Any stack space required is allocated via mcff.
169 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
173 std::vector<MachineInstr*>& mvec,
174 MachineCodeForInstruction& mcfi) const;
176 // Create instruction(s) to copy src to dest, for arbitrary types
177 // The generated instructions are returned in `mvec'.
178 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
179 // Any stack space required is allocated via mcff.
181 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
185 std::vector<MachineInstr*>& mvec,
186 MachineCodeForInstruction& mcfi) const;
188 // Create instruction sequence to produce a sign-extended register value
189 // from an arbitrary sized value (sized in bits, not bytes).
190 // The generated instructions are appended to `mvec'.
191 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
192 // Any stack space required is allocated via mcff.
194 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
198 unsigned int numLowBits,
199 std::vector<MachineInstr*>& mvec,
200 MachineCodeForInstruction& mcfi) const;
202 // Create instruction sequence to produce a zero-extended register value
203 // from an arbitrary sized value (sized in bits, not bytes).
204 // The generated instructions are appended to `mvec'.
205 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
206 // Any stack space required is allocated via mcff.
208 virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
212 unsigned int numLowBits,
213 std::vector<MachineInstr*>& mvec,
214 MachineCodeForInstruction& mcfi) const;
218 //----------------------------------------------------------------------------
219 // class UltraSparcRegInfo
221 // This class implements the virtual class MachineRegInfo for Sparc.
223 //----------------------------------------------------------------------------
225 class UltraSparcRegInfo : public MachineRegInfo {
226 // The actual register classes in the Sparc
229 IntRegClassID, // Integer
230 FloatRegClassID, // Float (both single/double)
231 IntCCRegClassID, // Int Condition Code
232 FloatCCRegClassID // Float Condition code
236 // Type of registers available in Sparc. There can be several reg types
237 // in the same class. For instace, the float reg class has Single/Double
248 // **** WARNING: If the above enum order is changed, also modify
249 // getRegisterClassOfValue method below since it assumes this particular
250 // order for efficiency.
253 // reverse pointer to get info about the ultra sparc machine
255 const UltraSparc *const UltraSparcInfo;
257 // Number of registers used for passing int args (usually 6: %o0 - %o5)
259 unsigned const NumOfIntArgRegs;
261 // Number of registers used for passing float args (usually 32: %f0 - %f31)
263 unsigned const NumOfFloatArgRegs;
265 // An out of bound register number that can be used to initialize register
266 // numbers. Useful for error detection.
268 int const InvalidRegNum;
271 // ======================== Private Methods =============================
273 // The following methods are used to color special live ranges (e.g.
274 // function args and return values etc.) with specific hardware registers
275 // as required. See SparcRegInfo.cpp for the implementation.
277 void suggestReg4RetAddr(MachineInstr *RetMI,
278 LiveRangeInfo &LRI) const;
280 void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI) const;
282 void InitializeOutgoingArg(MachineInstr* CallMI, AddedInstrns *CallAI,
283 PhyRegAlloc &PRA, LiveRange* LR,
284 unsigned regType, unsigned RegClassID,
285 int UniArgReg, unsigned int argNo,
286 std::vector<MachineInstr *>& AddedInstrnsBefore)
289 // The following 4 methods are used to find the RegType (see enum above)
290 // for a reg class and a given primitive type, a LiveRange, a Value,
291 // or a particular machine register.
292 // The fifth function gives the reg class of the given RegType.
294 int getRegType(unsigned regClassID, const Type* type) const;
295 int getRegType(const LiveRange *LR) const;
296 int getRegType(const Value *Val) const;
297 int getRegType(int unifiedRegNum) const;
299 // Used to generate a copy instruction based on the register class of
302 MachineInstr *cpValue2RegMI(Value *Val, unsigned DestReg,
306 // The following 2 methods are used to order the instructions addeed by
307 // the register allocator in association with function calling. See
308 // SparcRegInfo.cpp for more details
310 void moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
311 MachineInstr *UnordInst,
312 PhyRegAlloc &PRA) const;
314 void OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
315 std::vector<MachineInstr *> &OrdVec,
316 PhyRegAlloc &PRA) const;
319 // Compute which register can be used for an argument, if any
321 int regNumForIntArg(bool inCallee, bool isVarArgsCall,
322 unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
323 unsigned& regClassId) const;
325 int regNumForFPArg(unsigned RegType, bool inCallee, bool isVarArgsCall,
326 unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
327 unsigned& regClassId) const;
330 UltraSparcRegInfo(const UltraSparc &tgt);
332 // To get complete machine information structure using the machine register
335 inline const UltraSparc &getUltraSparcInfo() const {
336 return *UltraSparcInfo;
339 // To find the register class used for a specified Type
341 unsigned getRegClassIDOfType(const Type *type,
342 bool isCCReg = false) const;
344 // To find the register class of a Value
346 inline unsigned getRegClassIDOfValue(const Value *Val,
347 bool isCCReg = false) const {
348 return getRegClassIDOfType(Val->getType(), isCCReg);
351 // To find the register class to which a specified register belongs
353 unsigned getRegClassIDOfReg(int unifiedRegNum) const;
354 unsigned getRegClassIDOfRegType(int regType) const;
356 // getZeroRegNum - returns the register that contains always zero this is the
357 // unified register number
359 virtual int getZeroRegNum() const;
361 // getCallAddressReg - returns the reg used for pushing the address when a
362 // function is called. This can be used for other purposes between calls
364 unsigned getCallAddressReg() const;
366 // Returns the register containing the return address.
367 // It should be made sure that this register contains the return
368 // value when a return instruction is reached.
370 unsigned getReturnAddressReg() const;
372 // Number of registers used for passing int args (usually 6: %o0 - %o5)
373 // and float args (usually 32: %f0 - %f31)
375 unsigned const GetNumOfIntArgRegs() const { return NumOfIntArgRegs; }
376 unsigned const GetNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
378 // The following methods are used to color special live ranges (e.g.
379 // function args and return values etc.) with specific hardware registers
380 // as required. See SparcRegInfo.cpp for the implementation for Sparc.
382 void suggestRegs4MethodArgs(const Function *Meth,
383 LiveRangeInfo& LRI) const;
385 void suggestRegs4CallArgs(MachineInstr *CallMI,
386 LiveRangeInfo& LRI) const;
388 void suggestReg4RetValue(MachineInstr *RetMI,
389 LiveRangeInfo& LRI) const;
391 void colorMethodArgs(const Function *Meth, LiveRangeInfo &LRI,
392 AddedInstrns *FirstAI) const;
394 void colorCallArgs(MachineInstr *CallMI, LiveRangeInfo &LRI,
395 AddedInstrns *CallAI, PhyRegAlloc &PRA,
396 const BasicBlock *BB) const;
398 void colorRetValue(MachineInstr *RetI, LiveRangeInfo& LRI,
399 AddedInstrns *RetAI) const;
402 // method used for printing a register for debugging purposes
404 static void printReg(const LiveRange *LR);
406 // Each register class has a seperate space for register IDs. To convert
407 // a regId in a register class to a common Id, or vice versa,
408 // we use the folloing methods.
410 // This method provides a unique number for each register
411 inline int getUnifiedRegNum(unsigned regClassID, int reg) const {
413 if (regClassID == IntRegClassID) {
414 assert(reg < 32 && "Invalid reg. number");
417 else if (regClassID == FloatRegClassID) {
418 assert(reg < 64 && "Invalid reg. number");
419 return reg + 32; // we have 32 int regs
421 else if (regClassID == FloatCCRegClassID) {
422 assert(reg < 4 && "Invalid reg. number");
423 return reg + 32 + 64; // 32 int, 64 float
425 else if (regClassID == IntCCRegClassID ) {
426 assert(reg == 0 && "Invalid reg. number");
427 return reg + 4+ 32 + 64; // only one int CC reg
429 else if (reg==InvalidRegNum) {
430 return InvalidRegNum;
433 assert(0 && "Invalid register class");
437 // This method converts the unified number to the number in its class,
438 // and returns the class ID in regClassID.
439 inline int getClassRegNum(int ureg, unsigned& regClassID) const {
440 if (ureg < 32) { regClassID = IntRegClassID; return ureg; }
441 else if (ureg < 32+64) { regClassID = FloatRegClassID; return ureg-32; }
442 else if (ureg < 4 +96) { regClassID = FloatCCRegClassID; return ureg-96; }
443 else if (ureg < 1 +100) { regClassID = IntCCRegClassID; return ureg-100;}
444 else if (ureg == InvalidRegNum) { return InvalidRegNum; }
445 else { assert(0 && "Invalid unified register number"); }
449 // Returns the assembly-language name of the specified machine register.
451 virtual const char * const getUnifiedRegName(int reg) const;
454 // returns the # of bytes of stack space allocated for each register
455 // type. For Sparc, currently we allocate 8 bytes on stack for all
456 // register types. We can optimize this later if necessary to save stack
457 // space (However, should make sure that stack alignment is correct)
459 inline int getSpilledRegSize(int RegType) const {
464 // To obtain the return value and the indirect call address (if any)
465 // contained in a CALL machine instruction
467 const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
468 const Value * getCallInstIndirectAddrVal(const MachineInstr *CallMI) const;
470 // The following methods are used to generate "copy" machine instructions
471 // for an architecture.
473 // The function regTypeNeedsScratchReg() can be used to check whether a
474 // scratch register is needed to copy a register of type `regType' to
475 // or from memory. If so, such a scratch register can be provided by
476 // the caller (e.g., if it knows which regsiters are free); otherwise
477 // an arbitrary one will be chosen and spilled by the copy instructions.
479 bool regTypeNeedsScratchReg(int RegType,
480 int& scratchRegClassId) const;
482 void cpReg2RegMI(std::vector<MachineInstr*>& mvec,
483 unsigned SrcReg, unsigned DestReg,
486 void cpReg2MemMI(std::vector<MachineInstr*>& mvec,
487 unsigned SrcReg, unsigned DestPtrReg,
488 int Offset, int RegType, int scratchReg = -1) const;
490 void cpMem2RegMI(std::vector<MachineInstr*>& mvec,
491 unsigned SrcPtrReg, int Offset, unsigned DestReg,
492 int RegType, int scratchReg = -1) const;
494 void cpValue2Value(Value *Src, Value *Dest,
495 std::vector<MachineInstr*>& mvec) const;
497 // To see whether a register is a volatile (i.e., whehter it must be
498 // preserved acorss calls)
500 inline bool isRegVolatile(int RegClassID, int Reg) const {
501 return MachineRegClassArr[RegClassID]->isRegVolatile(Reg);
505 virtual unsigned getFramePointer() const;
506 virtual unsigned getStackPointer() const;
508 virtual int getInvalidRegNum() const {
509 return InvalidRegNum;
512 // This method inserts the caller saving code for call instructions
514 void insertCallerSavingCode(std::vector<MachineInstr*>& instrnsBefore,
515 std::vector<MachineInstr*>& instrnsAfter,
517 const BasicBlock *BB, PhyRegAlloc &PRA ) const;
523 //---------------------------------------------------------------------------
524 // class UltraSparcSchedInfo
527 // Interface to instruction scheduling information for UltraSPARC.
528 // The parameter values above are based on UltraSPARC IIi.
529 //---------------------------------------------------------------------------
532 class UltraSparcSchedInfo: public MachineSchedInfo {
534 UltraSparcSchedInfo(const TargetMachine &tgt);
536 virtual void initializeResources();
540 //---------------------------------------------------------------------------
541 // class UltraSparcFrameInfo
544 // Interface to stack frame layout info for the UltraSPARC.
545 // Starting offsets for each area of the stack frame are aligned at
546 // a multiple of getStackFrameSizeAlignment().
547 //---------------------------------------------------------------------------
549 class UltraSparcFrameInfo: public MachineFrameInfo {
551 UltraSparcFrameInfo(const TargetMachine &tgt) : MachineFrameInfo(tgt) {}
554 // These methods provide constant parameters of the frame layout.
556 int getStackFrameSizeAlignment() const { return StackFrameSizeAlignment;}
557 int getMinStackFrameSize() const { return MinStackFrameSize; }
558 int getNumFixedOutgoingArgs() const { return NumFixedOutgoingArgs; }
559 int getSizeOfEachArgOnStack() const { return SizeOfEachArgOnStack; }
560 bool argsOnStackHaveFixedSize() const { return true; }
562 // This method adjusts a stack offset to meet alignment rules of target.
563 // The fixed OFFSET (0x7ff) must be subtracted and the result aligned.
564 virtual int adjustAlignment (int unalignedOffset,
566 unsigned int align) const {
567 return unalignedOffset + (growUp? +1:-1)*((unalignedOffset-OFFSET) % align);
570 // These methods compute offsets using the frame contents for a
571 // particular function. The frame contents are obtained from the
572 // MachineCodeInfoForMethod object for the given function.
574 int getFirstIncomingArgOffset (MachineCodeForMethod& mcInfo,
577 growUp = true; // arguments area grows upwards
578 return FirstIncomingArgOffsetFromFP;
580 int getFirstOutgoingArgOffset (MachineCodeForMethod& mcInfo,
583 growUp = true; // arguments area grows upwards
584 return FirstOutgoingArgOffsetFromSP;
586 int getFirstOptionalOutgoingArgOffset(MachineCodeForMethod& mcInfo,
589 growUp = true; // arguments area grows upwards
590 return FirstOptionalOutgoingArgOffsetFromSP;
593 int getFirstAutomaticVarOffset (MachineCodeForMethod& mcInfo,
595 int getRegSpillAreaOffset (MachineCodeForMethod& mcInfo,
597 int getTmpAreaOffset (MachineCodeForMethod& mcInfo,
599 int getDynamicAreaOffset (MachineCodeForMethod& mcInfo,
603 // These methods specify the base register used for each stack area
604 // (generally FP or SP)
606 virtual int getIncomingArgBaseRegNum() const {
607 return (int) target.getRegInfo().getFramePointer();
609 virtual int getOutgoingArgBaseRegNum() const {
610 return (int) target.getRegInfo().getStackPointer();
612 virtual int getOptionalOutgoingArgBaseRegNum() const {
613 return (int) target.getRegInfo().getStackPointer();
615 virtual int getAutomaticVarBaseRegNum() const {
616 return (int) target.getRegInfo().getFramePointer();
618 virtual int getRegSpillAreaBaseRegNum() const {
619 return (int) target.getRegInfo().getFramePointer();
621 virtual int getDynamicAreaBaseRegNum() const {
622 return (int) target.getRegInfo().getStackPointer();
626 /*----------------------------------------------------------------------
627 This diagram shows the stack frame layout used by llc on Sparc V9.
628 Note that only the location of automatic variables, spill area,
629 temporary storage, and dynamically allocated stack area are chosen
630 by us. The rest conform to the Sparc V9 ABI.
631 All stack addresses are offset by OFFSET = 0x7ff (2047).
633 Alignment assumpteions and other invariants:
634 (1) %sp+OFFSET and %fp+OFFSET are always aligned on 16-byte boundary
635 (2) Variables in automatic, spill, temporary, or dynamic regions
636 are aligned according to their size as in all memory accesses.
637 (3) Everything below the dynamically allocated stack area is only used
638 during a call to another function, so it is never needed when
639 the current function is active. This is why space can be allocated
640 dynamically by incrementing %sp any time within the function.
645 %fp+OFFSET+176 Optional extra incoming arguments# 1..N
646 %fp+OFFSET+168 Incoming argument #6
648 %fp+OFFSET+128 Incoming argument #1
650 ---%fp+OFFSET-0--------Bottom of caller's stack frame--------------------
651 %fp+OFFSET-8 Automatic variables <-- ****TOP OF STACK FRAME****
656 %sp+OFFSET+176+8N Bottom of dynamically allocated stack area
657 %sp+OFFSET+168+8N Optional extra outgoing argument# N
659 %sp+OFFSET+176 Optional extra outgoing argument# 1
660 %sp+OFFSET+168 Outgoing argument #6
662 %sp+OFFSET+128 Outgoing argument #1
663 %sp+OFFSET+120 Save area for %i7
665 %sp+OFFSET+0 Save area for %l0 <-- ****BOTTOM OF STACK FRAME****
667 *----------------------------------------------------------------------*/
669 // All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
670 static const int OFFSET = (int) 0x7ff;
671 static const int StackFrameSizeAlignment = 16;
672 static const int MinStackFrameSize = 176;
673 static const int NumFixedOutgoingArgs = 6;
674 static const int SizeOfEachArgOnStack = 8;
675 static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
676 static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
677 static const int StaticAreaOffsetFromFP = 0 + OFFSET;
678 static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
679 static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
683 //---------------------------------------------------------------------------
684 // class UltraSparcCacheInfo
687 // Interface to cache parameters for the UltraSPARC.
688 // Just use defaults for now.
689 //---------------------------------------------------------------------------
691 class UltraSparcCacheInfo: public MachineCacheInfo {
693 UltraSparcCacheInfo(const TargetMachine &T) : MachineCacheInfo(T) {}
697 //---------------------------------------------------------------------------
698 // class UltraSparcOptInfo
701 // Interface to machine-level optimization routines for the UltraSPARC.
702 //---------------------------------------------------------------------------
704 class UltraSparcOptInfo: public MachineOptInfo {
706 UltraSparcOptInfo(const TargetMachine &T) : MachineOptInfo(T) {}
708 virtual bool IsUselessCopy (const MachineInstr* MI) const;
712 //---------------------------------------------------------------------------
713 // class UltraSparcMachine
716 // Primary interface to machine description for the UltraSPARC.
717 // Primarily just initializes machine-dependent parameters in
718 // class TargetMachine, and creates machine-dependent subclasses
719 // for classes such as InstrInfo, SchedInfo and RegInfo.
720 //---------------------------------------------------------------------------
722 class UltraSparc : public TargetMachine {
724 UltraSparcInstrInfo instrInfo;
725 UltraSparcSchedInfo schedInfo;
726 UltraSparcRegInfo regInfo;
727 UltraSparcFrameInfo frameInfo;
728 UltraSparcCacheInfo cacheInfo;
729 UltraSparcOptInfo optInfo;
733 virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
734 virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
735 virtual const MachineRegInfo &getRegInfo() const { return regInfo; }
736 virtual const MachineFrameInfo &getFrameInfo() const { return frameInfo; }
737 virtual const MachineCacheInfo &getCacheInfo() const { return cacheInfo; }
738 virtual const MachineOptInfo &getOptInfo() const { return optInfo; }
740 // getPrologEpilogCodeInserter - Inserts prolog/epilog code.
741 virtual Pass* getPrologEpilogInsertionPass();
743 // getFunctionAsmPrinterPass - Writes out machine code for a single function
744 virtual Pass* getFunctionAsmPrinterPass(std::ostream &Out);
746 // getModuleAsmPrinterPass - Writes generated machine code to assembly file.
747 virtual Pass* getModuleAsmPrinterPass(std::ostream &Out);
749 // getEmitBytecodeToAsmPass - Emits final LLVM bytecode to assembly file.
750 virtual Pass* getEmitBytecodeToAsmPass(std::ostream &Out);