1 //===-- SparcInternals.h ----------------------------------------*- C++ -*-===//
3 // This file defines stuff that is to be private to the Sparc backend, but is
4 // shared among different portions of the backend.
6 //===----------------------------------------------------------------------===//
8 #ifndef SPARC_INTERNALS_H
9 #define SPARC_INTERNALS_H
11 #include "llvm/CodeGen/MachineInstrBuilder.h"
12 #include "llvm/Target/TargetMachine.h"
13 #include "llvm/Target/TargetSchedInfo.h"
14 #include "llvm/Target/TargetFrameInfo.h"
15 #include "llvm/Target/TargetCacheInfo.h"
16 #include "llvm/Target/TargetRegInfo.h"
17 #include "llvm/Target/TargetOptInfo.h"
18 #include "llvm/Type.h"
19 #include "SparcRegClassInfo.h"
20 #include "Config/sys/types.h"
27 enum SparcInstrSchedClass {
28 SPARC_NONE, /* Instructions with no scheduling restrictions */
29 SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
30 SPARC_IEU0, /* Integer class IEU0 */
31 SPARC_IEU1, /* Integer class IEU1 */
32 SPARC_FPM, /* FP Multiply or Divide instructions */
33 SPARC_FPA, /* All other FP instructions */
34 SPARC_CTI, /* Control-transfer instructions */
35 SPARC_LD, /* Load instructions */
36 SPARC_ST, /* Store instructions */
37 SPARC_SINGLE, /* Instructions that must issue by themselves */
39 SPARC_INV, /* This should stay at the end for the next value */
40 SPARC_NUM_SCHED_CLASSES = SPARC_INV
44 //---------------------------------------------------------------------------
45 // enum SparcMachineOpCode.
46 // const TargetInstrDescriptor SparcMachineInstrDesc[]
49 // Description of UltraSparc machine instructions.
51 //---------------------------------------------------------------------------
54 enum SparcMachineOpCode {
55 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
56 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
58 #include "SparcInstr.def"
60 // End-of-array marker
62 NUM_REAL_OPCODES = PHI, // number of valid opcodes
63 NUM_TOTAL_OPCODES = INVALID_OPCODE
68 // Array of machine instruction descriptions...
69 extern const TargetInstrDescriptor SparcMachineInstrDesc[];
72 //---------------------------------------------------------------------------
73 // class UltraSparcInstrInfo
76 // Information about individual instructions.
77 // Most information is stored in the SparcMachineInstrDesc array above.
78 // Other information is computed on demand, and most such functions
79 // default to member functions in base class TargetInstrInfo.
80 //---------------------------------------------------------------------------
82 struct UltraSparcInstrInfo : public TargetInstrInfo {
83 UltraSparcInstrInfo();
86 // All immediate constants are in position 1 except the
87 // store instructions and SETxx.
89 virtual int getImmedConstantPos(MachineOpCode opCode) const {
91 if (this->maxImmedConstant(opCode, ignore) != 0) {
93 assert(! this->isStore((MachineOpCode) V9::STBr - 1));
95 assert(! this->isStore((MachineOpCode) V9::STXFSRi + 1));
97 if (opCode == V9::SETSW || opCode == V9::SETUW ||
98 opCode == V9::SETX || opCode == V9::SETHI)
100 if (opCode >= V9::STBr && opCode <= V9::STXFSRi)
108 /// createNOPinstr - returns the target's implementation of NOP, which is
109 /// usually a pseudo-instruction, implemented by a degenerate version of
110 /// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi 0, g0
112 MachineInstr* createNOPinstr() const {
113 return BuildMI(V9::SETHI, 2).addZImm(0).addReg(SparcIntRegClass::g0);
116 /// isNOPinstr - not having a special NOP opcode, we need to know if a given
117 /// instruction is interpreted as an `official' NOP instr, i.e., there may be
118 /// more than one way to `do nothing' but only one canonical way to slack off.
120 bool isNOPinstr(const MachineInstr &MI) const {
121 // Make sure the instruction is EXACTLY `sethi g0, 0'
122 if (MI.getOpcode() == V9::SETHI && MI.getNumOperands() == 2) {
123 const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
124 if (op0.isImmediate() && op0.getImmedValue() == 0 &&
125 op1.isMachineRegister() &&
126 op1.getMachineRegNum() == SparcIntRegClass::g0)
134 virtual bool hasResultInterlock(MachineOpCode opCode) const
136 // All UltraSPARC instructions have interlocks (note that delay slots
137 // are not considered here).
138 // However, instructions that use the result of an FCMP produce a
139 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
140 // Force the compiler to insert a software interlock (i.e., gap of
141 // 2 other groups, including NOPs if necessary).
142 return (opCode == V9::FCMPS || opCode == V9::FCMPD || opCode == V9::FCMPQ);
145 //-------------------------------------------------------------------------
146 // Queries about representation of LLVM quantities (e.g., constants)
147 //-------------------------------------------------------------------------
149 virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
150 const Instruction* I) const;
152 //-------------------------------------------------------------------------
153 // Code generation support for creating individual machine instructions
154 //-------------------------------------------------------------------------
156 // Get certain common op codes for the current target. This and all the
157 // Create* methods below should be moved to a machine code generation class
159 virtual MachineOpCode getNOPOpCode() const { return V9::NOP; }
161 // Create an instruction sequence to put the constant `val' into
162 // the virtual register `dest'. `val' may be a Constant or a
163 // GlobalValue, viz., the constant address of a global variable or function.
164 // The generated instructions are returned in `mvec'.
165 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
166 // Any stack space required is allocated via mcff.
168 virtual void CreateCodeToLoadConst(const TargetMachine& target,
172 std::vector<MachineInstr*>& mvec,
173 MachineCodeForInstruction& mcfi) const;
175 // Create an instruction sequence to copy an integer value `val'
176 // to a floating point value `dest' by copying to memory and back.
177 // val must be an integral type. dest must be a Float or Double.
178 // The generated instructions are returned in `mvec'.
179 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
180 // Any stack space required is allocated via mcff.
182 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
186 std::vector<MachineInstr*>& mvec,
187 MachineCodeForInstruction& mcfi) const;
189 // Similarly, create an instruction sequence to copy an FP value
190 // `val' to an integer value `dest' by copying to memory and back.
191 // The generated instructions are returned in `mvec'.
192 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
193 // Any stack space required is allocated via mcff.
195 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
199 std::vector<MachineInstr*>& mvec,
200 MachineCodeForInstruction& mcfi) const;
202 // Create instruction(s) to copy src to dest, for arbitrary types
203 // The generated instructions are returned in `mvec'.
204 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
205 // Any stack space required is allocated via mcff.
207 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
211 std::vector<MachineInstr*>& mvec,
212 MachineCodeForInstruction& mcfi) const;
214 // Create instruction sequence to produce a sign-extended register value
215 // from an arbitrary sized value (sized in bits, not bytes).
216 // The generated instructions are appended to `mvec'.
217 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
218 // Any stack space required is allocated via mcff.
220 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
224 unsigned int numLowBits,
225 std::vector<MachineInstr*>& mvec,
226 MachineCodeForInstruction& mcfi) const;
228 // Create instruction sequence to produce a zero-extended register value
229 // from an arbitrary sized value (sized in bits, not bytes).
230 // The generated instructions are appended to `mvec'.
231 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
232 // Any stack space required is allocated via mcff.
234 virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
238 unsigned int numLowBits,
239 std::vector<MachineInstr*>& mvec,
240 MachineCodeForInstruction& mcfi) const;
244 //----------------------------------------------------------------------------
245 // class UltraSparcRegInfo
247 // This class implements the virtual class TargetRegInfo for Sparc.
249 //----------------------------------------------------------------------------
251 class UltraSparcRegInfo : public TargetRegInfo {
253 // The actual register classes in the Sparc
255 // **** WARNING: If this enum order is changed, also modify
256 // getRegisterClassOfValue method below since it assumes this particular
257 // order for efficiency.
260 IntRegClassID, // Integer
261 FloatRegClassID, // Float (both single/double)
262 IntCCRegClassID, // Int Condition Code
263 FloatCCRegClassID, // Float Condition code
264 SpecialRegClassID // Special (unallocated) registers
269 // Number of registers used for passing int args (usually 6: %o0 - %o5)
271 unsigned const NumOfIntArgRegs;
273 // Number of registers used for passing float args (usually 32: %f0 - %f31)
275 unsigned const NumOfFloatArgRegs;
277 // ======================== Private Methods =============================
279 // The following methods are used to color special live ranges (e.g.
280 // function args and return values etc.) with specific hardware registers
281 // as required. See SparcRegInfo.cpp for the implementation.
283 void suggestReg4RetAddr(MachineInstr *RetMI,
284 LiveRangeInfo &LRI) const;
286 void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI) const;
288 void InitializeOutgoingArg(MachineInstr* CallMI, AddedInstrns *CallAI,
289 PhyRegAlloc &PRA, LiveRange* LR,
290 unsigned regType, unsigned RegClassID,
291 int UniArgReg, unsigned int argNo,
292 std::vector<MachineInstr *>& AddedInstrnsBefore)
295 // Helper used by the all the getRegType() functions.
296 int getRegTypeForClassAndType(unsigned regClassID, const Type* type) const;
298 // Used to generate a copy instruction based on the register class of
301 MachineInstr *cpValue2RegMI(Value *Val, unsigned DestReg,
305 // The following 2 methods are used to order the instructions addeed by
306 // the register allocator in association with function calling. See
307 // SparcRegInfo.cpp for more details
309 void moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
310 MachineInstr *UnordInst,
311 PhyRegAlloc &PRA) const;
313 void OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
314 std::vector<MachineInstr *> &OrdVec,
315 PhyRegAlloc &PRA) const;
318 // Type of registers available in Sparc. There can be several reg types
319 // in the same class. For instace, the float reg class has Single/Double
331 UltraSparcRegInfo(const UltraSparc &tgt);
333 // To find the register class used for a specified Type
335 unsigned getRegClassIDOfType(const Type *type,
336 bool isCCReg = false) const;
338 // To find the register class to which a specified register belongs
340 unsigned getRegClassIDOfRegType(int regType) const;
342 // getZeroRegNum - returns the register that contains always zero this is the
343 // unified register number
345 virtual int getZeroRegNum() const;
347 // getCallAddressReg - returns the reg used for pushing the address when a
348 // function is called. This can be used for other purposes between calls
350 unsigned getCallAddressReg() const;
352 // Returns the register containing the return address.
353 // It should be made sure that this register contains the return
354 // value when a return instruction is reached.
356 unsigned getReturnAddressReg() const;
358 // Number of registers used for passing int args (usually 6: %o0 - %o5)
359 // and float args (usually 32: %f0 - %f31)
361 unsigned const getNumOfIntArgRegs() const { return NumOfIntArgRegs; }
362 unsigned const getNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
364 // Compute which register can be used for an argument, if any
366 int regNumForIntArg(bool inCallee, bool isVarArgsCall,
367 unsigned argNo, unsigned& regClassId) const;
369 int regNumForFPArg(unsigned RegType, bool inCallee, bool isVarArgsCall,
370 unsigned argNo, unsigned& regClassId) const;
372 // The following methods are used to color special live ranges (e.g.
373 // function args and return values etc.) with specific hardware registers
374 // as required. See SparcRegInfo.cpp for the implementation for Sparc.
376 void suggestRegs4MethodArgs(const Function *Meth,
377 LiveRangeInfo& LRI) const;
379 void suggestRegs4CallArgs(MachineInstr *CallMI,
380 LiveRangeInfo& LRI) const;
382 void suggestReg4RetValue(MachineInstr *RetMI,
383 LiveRangeInfo& LRI) const;
385 void colorMethodArgs(const Function *Meth, LiveRangeInfo &LRI,
386 AddedInstrns *FirstAI) const;
388 void colorCallArgs(MachineInstr *CallMI, LiveRangeInfo &LRI,
389 AddedInstrns *CallAI, PhyRegAlloc &PRA,
390 const BasicBlock *BB) const;
392 void colorRetValue(MachineInstr *RetI, LiveRangeInfo& LRI,
393 AddedInstrns *RetAI) const;
396 // method used for printing a register for debugging purposes
398 void printReg(const LiveRange *LR) const;
400 // returns the # of bytes of stack space allocated for each register
401 // type. For Sparc, currently we allocate 8 bytes on stack for all
402 // register types. We can optimize this later if necessary to save stack
403 // space (However, should make sure that stack alignment is correct)
405 inline int getSpilledRegSize(int RegType) const {
410 // To obtain the return value and the indirect call address (if any)
411 // contained in a CALL machine instruction
413 const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
414 const Value * getCallInstIndirectAddrVal(const MachineInstr *CallMI) const;
416 // The following methods are used to generate "copy" machine instructions
417 // for an architecture.
419 // The function regTypeNeedsScratchReg() can be used to check whether a
420 // scratch register is needed to copy a register of type `regType' to
421 // or from memory. If so, such a scratch register can be provided by
422 // the caller (e.g., if it knows which regsiters are free); otherwise
423 // an arbitrary one will be chosen and spilled by the copy instructions.
425 bool regTypeNeedsScratchReg(int RegType,
426 int& scratchRegClassId) const;
428 void cpReg2RegMI(std::vector<MachineInstr*>& mvec,
429 unsigned SrcReg, unsigned DestReg,
432 void cpReg2MemMI(std::vector<MachineInstr*>& mvec,
433 unsigned SrcReg, unsigned DestPtrReg,
434 int Offset, int RegType, int scratchReg = -1) const;
436 void cpMem2RegMI(std::vector<MachineInstr*>& mvec,
437 unsigned SrcPtrReg, int Offset, unsigned DestReg,
438 int RegType, int scratchReg = -1) const;
440 void cpValue2Value(Value *Src, Value *Dest,
441 std::vector<MachineInstr*>& mvec) const;
443 // To see whether a register is a volatile (i.e., whehter it must be
444 // preserved acorss calls)
446 inline bool isRegVolatile(int RegClassID, int Reg) const {
447 return MachineRegClassArr[RegClassID]->isRegVolatile(Reg);
450 // Get the register type for a register identified different ways.
451 int getRegType(const Type* type) const;
452 int getRegType(const LiveRange *LR) const;
453 int getRegType(int unifiedRegNum) const;
455 virtual unsigned getFramePointer() const;
456 virtual unsigned getStackPointer() const;
458 // This method inserts the caller saving code for call instructions
460 void insertCallerSavingCode(std::vector<MachineInstr*>& instrnsBefore,
461 std::vector<MachineInstr*>& instrnsAfter,
463 const BasicBlock *BB, PhyRegAlloc &PRA ) const;
469 //---------------------------------------------------------------------------
470 // class UltraSparcSchedInfo
473 // Interface to instruction scheduling information for UltraSPARC.
474 // The parameter values above are based on UltraSPARC IIi.
475 //---------------------------------------------------------------------------
478 class UltraSparcSchedInfo: public TargetSchedInfo {
480 UltraSparcSchedInfo(const TargetMachine &tgt);
482 virtual void initializeResources();
486 //---------------------------------------------------------------------------
487 // class UltraSparcFrameInfo
490 // Interface to stack frame layout info for the UltraSPARC.
491 // Starting offsets for each area of the stack frame are aligned at
492 // a multiple of getStackFrameSizeAlignment().
493 //---------------------------------------------------------------------------
495 class UltraSparcFrameInfo: public TargetFrameInfo {
496 const TargetMachine ⌖
498 UltraSparcFrameInfo(const TargetMachine &TM)
499 : TargetFrameInfo(StackGrowsDown, StackFrameSizeAlignment, 0), target(TM) {}
502 // These methods provide constant parameters of the frame layout.
504 int getStackFrameSizeAlignment() const { return StackFrameSizeAlignment;}
505 int getMinStackFrameSize() const { return MinStackFrameSize; }
506 int getNumFixedOutgoingArgs() const { return NumFixedOutgoingArgs; }
507 int getSizeOfEachArgOnStack() const { return SizeOfEachArgOnStack; }
508 bool argsOnStackHaveFixedSize() const { return true; }
510 // This method adjusts a stack offset to meet alignment rules of target.
511 // The fixed OFFSET (0x7ff) must be subtracted and the result aligned.
512 virtual int adjustAlignment (int unalignedOffset,
514 unsigned int align) const {
515 return unalignedOffset + (growUp? +1:-1)*((unalignedOffset-OFFSET) % align);
518 // These methods compute offsets using the frame contents for a
519 // particular function. The frame contents are obtained from the
520 // MachineCodeInfoForMethod object for the given function.
522 int getFirstIncomingArgOffset (MachineFunction& mcInfo,
525 growUp = true; // arguments area grows upwards
526 return FirstIncomingArgOffsetFromFP;
528 int getFirstOutgoingArgOffset (MachineFunction& mcInfo,
531 growUp = true; // arguments area grows upwards
532 return FirstOutgoingArgOffsetFromSP;
534 int getFirstOptionalOutgoingArgOffset(MachineFunction& mcInfo,
537 growUp = true; // arguments area grows upwards
538 return FirstOptionalOutgoingArgOffsetFromSP;
541 int getFirstAutomaticVarOffset (MachineFunction& mcInfo,
543 int getRegSpillAreaOffset (MachineFunction& mcInfo,
545 int getTmpAreaOffset (MachineFunction& mcInfo,
547 int getDynamicAreaOffset (MachineFunction& mcInfo,
551 // These methods specify the base register used for each stack area
552 // (generally FP or SP)
554 virtual int getIncomingArgBaseRegNum() const {
555 return (int) target.getRegInfo().getFramePointer();
557 virtual int getOutgoingArgBaseRegNum() const {
558 return (int) target.getRegInfo().getStackPointer();
560 virtual int getOptionalOutgoingArgBaseRegNum() const {
561 return (int) target.getRegInfo().getStackPointer();
563 virtual int getAutomaticVarBaseRegNum() const {
564 return (int) target.getRegInfo().getFramePointer();
566 virtual int getRegSpillAreaBaseRegNum() const {
567 return (int) target.getRegInfo().getFramePointer();
569 virtual int getDynamicAreaBaseRegNum() const {
570 return (int) target.getRegInfo().getStackPointer();
573 virtual int getIncomingArgOffset(MachineFunction& mcInfo,
574 unsigned argNum) const {
575 assert(argsOnStackHaveFixedSize());
577 unsigned relativeOffset = argNum * getSizeOfEachArgOnStack();
578 bool growUp; // do args grow up or down
579 int firstArg = getFirstIncomingArgOffset(mcInfo, growUp);
580 return growUp ? firstArg + relativeOffset : firstArg - relativeOffset;
583 virtual int getOutgoingArgOffset(MachineFunction& mcInfo,
584 unsigned argNum) const {
585 assert(argsOnStackHaveFixedSize());
586 //assert(((int) argNum - this->getNumFixedOutgoingArgs())
587 // <= (int) mcInfo.getInfo()->getMaxOptionalNumArgs());
589 unsigned relativeOffset = argNum * getSizeOfEachArgOnStack();
590 bool growUp; // do args grow up or down
591 int firstArg = getFirstOutgoingArgOffset(mcInfo, growUp);
592 return growUp ? firstArg + relativeOffset : firstArg - relativeOffset;
596 /*----------------------------------------------------------------------
597 This diagram shows the stack frame layout used by llc on Sparc V9.
598 Note that only the location of automatic variables, spill area,
599 temporary storage, and dynamically allocated stack area are chosen
600 by us. The rest conform to the Sparc V9 ABI.
601 All stack addresses are offset by OFFSET = 0x7ff (2047).
603 Alignment assumptions and other invariants:
604 (1) %sp+OFFSET and %fp+OFFSET are always aligned on 16-byte boundary
605 (2) Variables in automatic, spill, temporary, or dynamic regions
606 are aligned according to their size as in all memory accesses.
607 (3) Everything below the dynamically allocated stack area is only used
608 during a call to another function, so it is never needed when
609 the current function is active. This is why space can be allocated
610 dynamically by incrementing %sp any time within the function.
615 %fp+OFFSET+176 Optional extra incoming arguments# 1..N
616 %fp+OFFSET+168 Incoming argument #6
618 %fp+OFFSET+128 Incoming argument #1
620 ---%fp+OFFSET-0--------Bottom of caller's stack frame--------------------
621 %fp+OFFSET-8 Automatic variables <-- ****TOP OF STACK FRAME****
626 %sp+OFFSET+176+8N Bottom of dynamically allocated stack area
627 %sp+OFFSET+168+8N Optional extra outgoing argument# N
629 %sp+OFFSET+176 Optional extra outgoing argument# 1
630 %sp+OFFSET+168 Outgoing argument #6
632 %sp+OFFSET+128 Outgoing argument #1
633 %sp+OFFSET+120 Save area for %i7
635 %sp+OFFSET+0 Save area for %l0 <-- ****BOTTOM OF STACK FRAME****
637 *----------------------------------------------------------------------*/
639 // All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
640 static const int OFFSET = (int) 0x7ff;
641 static const int StackFrameSizeAlignment = 16;
642 static const int MinStackFrameSize = 176;
643 static const int NumFixedOutgoingArgs = 6;
644 static const int SizeOfEachArgOnStack = 8;
645 static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
646 static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
647 static const int StaticAreaOffsetFromFP = 0 + OFFSET;
648 static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
649 static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
653 //---------------------------------------------------------------------------
654 // class UltraSparcCacheInfo
657 // Interface to cache parameters for the UltraSPARC.
658 // Just use defaults for now.
659 //---------------------------------------------------------------------------
661 struct UltraSparcCacheInfo: public TargetCacheInfo {
662 UltraSparcCacheInfo(const TargetMachine &T) : TargetCacheInfo(T) {}
666 //---------------------------------------------------------------------------
667 // class UltraSparcOptInfo
670 // Interface to machine-level optimization routines for the UltraSPARC.
671 //---------------------------------------------------------------------------
673 struct UltraSparcOptInfo: public TargetOptInfo {
674 UltraSparcOptInfo(const TargetMachine &T) : TargetOptInfo(T) {}
676 virtual bool IsUselessCopy (const MachineInstr* MI) const;
679 /// createAddRegNumToValuesPass - this pass adds unsigned register numbers to
680 /// instructions, since that's not done by the Sparc InstSelector, but that's
681 /// how the target-independent register allocator in the JIT likes to see
682 /// instructions. This pass enables the usage of the JIT register allocator(s).
683 Pass *createAddRegNumToValuesPass();
685 //---------------------------------------------------------------------------
686 // class UltraSparcMachine
689 // Primary interface to machine description for the UltraSPARC.
690 // Primarily just initializes machine-dependent parameters in
691 // class TargetMachine, and creates machine-dependent subclasses
692 // for classes such as InstrInfo, SchedInfo and RegInfo.
693 //---------------------------------------------------------------------------
695 class UltraSparc : public TargetMachine {
696 UltraSparcInstrInfo instrInfo;
697 UltraSparcSchedInfo schedInfo;
698 UltraSparcRegInfo regInfo;
699 UltraSparcFrameInfo frameInfo;
700 UltraSparcCacheInfo cacheInfo;
701 UltraSparcOptInfo optInfo;
705 virtual const TargetInstrInfo &getInstrInfo() const { return instrInfo; }
706 virtual const TargetSchedInfo &getSchedInfo() const { return schedInfo; }
707 virtual const TargetRegInfo &getRegInfo() const { return regInfo; }
708 virtual const TargetFrameInfo &getFrameInfo() const { return frameInfo; }
709 virtual const TargetCacheInfo &getCacheInfo() const { return cacheInfo; }
710 virtual const TargetOptInfo &getOptInfo() const { return optInfo; }
712 virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
713 virtual bool addPassesToJITCompile(PassManager &PM);
714 virtual bool addPassesToEmitMachineCode(PassManager &PM,
715 MachineCodeEmitter &MCE);
717 // getPrologEpilogInsertionPass - Inserts prolog/epilog code.
718 Pass* getPrologEpilogInsertionPass();
720 // getFunctionAsmPrinterPass - Writes out machine code for a single function
721 Pass* getFunctionAsmPrinterPass(std::ostream &Out);
723 // getModuleAsmPrinterPass - Writes generated machine code to assembly file.
724 Pass* getModuleAsmPrinterPass(std::ostream &Out);
726 // getEmitBytecodeToAsmPass - Emits final LLVM bytecode to assembly file.
727 Pass* getEmitBytecodeToAsmPass(std::ostream &Out);
730 int64_t GetConstantValueAsSignedInt(const Value *V, bool &isValidConstant);
732 Pass *getFunctionInfo(std::ostream &out);