1 //===-- SparcInternals.h ----------------------------------------*- C++ -*-===//
3 // This file defines stuff that is to be private to the Sparc backend, but is
4 // shared among different portions of the backend.
6 //===----------------------------------------------------------------------===//
8 #ifndef SPARC_INTERNALS_H
9 #define SPARC_INTERNALS_H
11 #include "llvm/CodeGen/MachineInstrBuilder.h"
12 #include "llvm/Target/TargetMachine.h"
13 #include "llvm/Target/TargetSchedInfo.h"
14 #include "llvm/Target/TargetFrameInfo.h"
15 #include "llvm/Target/TargetCacheInfo.h"
16 #include "llvm/Target/TargetRegInfo.h"
17 #include "llvm/Target/TargetOptInfo.h"
18 #include "llvm/Type.h"
19 #include "SparcRegClassInfo.h"
20 #include "Config/sys/types.h"
26 enum SparcInstrSchedClass {
27 SPARC_NONE, /* Instructions with no scheduling restrictions */
28 SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
29 SPARC_IEU0, /* Integer class IEU0 */
30 SPARC_IEU1, /* Integer class IEU1 */
31 SPARC_FPM, /* FP Multiply or Divide instructions */
32 SPARC_FPA, /* All other FP instructions */
33 SPARC_CTI, /* Control-transfer instructions */
34 SPARC_LD, /* Load instructions */
35 SPARC_ST, /* Store instructions */
36 SPARC_SINGLE, /* Instructions that must issue by themselves */
38 SPARC_INV, /* This should stay at the end for the next value */
39 SPARC_NUM_SCHED_CLASSES = SPARC_INV
43 //---------------------------------------------------------------------------
44 // enum SparcMachineOpCode.
45 // const TargetInstrDescriptor SparcMachineInstrDesc[]
48 // Description of UltraSparc machine instructions.
50 //---------------------------------------------------------------------------
53 enum SparcMachineOpCode {
54 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
55 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
57 #include "SparcInstr.def"
59 // End-of-array marker
61 NUM_REAL_OPCODES = PHI, // number of valid opcodes
62 NUM_TOTAL_OPCODES = INVALID_OPCODE
67 // Array of machine instruction descriptions...
68 extern const TargetInstrDescriptor SparcMachineInstrDesc[];
71 //---------------------------------------------------------------------------
72 // class UltraSparcInstrInfo
75 // Information about individual instructions.
76 // Most information is stored in the SparcMachineInstrDesc array above.
77 // Other information is computed on demand, and most such functions
78 // default to member functions in base class TargetInstrInfo.
79 //---------------------------------------------------------------------------
81 struct UltraSparcInstrInfo : public TargetInstrInfo {
82 UltraSparcInstrInfo();
85 // All immediate constants are in position 1 except the
86 // store instructions and SETxx.
88 virtual int getImmedConstantPos(MachineOpCode opCode) const {
90 if (this->maxImmedConstant(opCode, ignore) != 0) {
92 assert(! this->isStore((MachineOpCode) V9::STBr - 1));
94 assert(! this->isStore((MachineOpCode) V9::STXFSRi + 1));
96 if (opCode == V9::SETSW || opCode == V9::SETUW ||
97 opCode == V9::SETX || opCode == V9::SETHI)
99 if (opCode >= V9::STBr && opCode <= V9::STXFSRi)
107 /// createNOPinstr - returns the target's implementation of NOP, which is
108 /// usually a pseudo-instruction, implemented by a degenerate version of
109 /// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi 0, g0
111 MachineInstr* createNOPinstr() const {
112 return BuildMI(V9::SETHI, 2).addZImm(0).addReg(SparcIntRegClass::g0);
115 /// isNOPinstr - not having a special NOP opcode, we need to know if a given
116 /// instruction is interpreted as an `official' NOP instr, i.e., there may be
117 /// more than one way to `do nothing' but only one canonical way to slack off.
119 bool isNOPinstr(const MachineInstr &MI) const {
120 // Make sure the instruction is EXACTLY `sethi g0, 0'
121 if (MI.getOpcode() == V9::SETHI && MI.getNumOperands() == 2) {
122 const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
123 if (op0.isImmediate() && op0.getImmedValue() == 0 &&
124 op1.isMachineRegister() &&
125 op1.getMachineRegNum() == SparcIntRegClass::g0)
133 virtual bool hasResultInterlock(MachineOpCode opCode) const
135 // All UltraSPARC instructions have interlocks (note that delay slots
136 // are not considered here).
137 // However, instructions that use the result of an FCMP produce a
138 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
139 // Force the compiler to insert a software interlock (i.e., gap of
140 // 2 other groups, including NOPs if necessary).
141 return (opCode == V9::FCMPS || opCode == V9::FCMPD || opCode == V9::FCMPQ);
144 //-------------------------------------------------------------------------
145 // Queries about representation of LLVM quantities (e.g., constants)
146 //-------------------------------------------------------------------------
148 virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
149 const Instruction* I) const;
151 //-------------------------------------------------------------------------
152 // Code generation support for creating individual machine instructions
153 //-------------------------------------------------------------------------
155 // Get certain common op codes for the current target. This and all the
156 // Create* methods below should be moved to a machine code generation class
158 virtual MachineOpCode getNOPOpCode() const { return V9::NOP; }
160 // Get the value of an integral constant in the form that must
161 // be put into the machine register. The specified constant is interpreted
162 // as (i.e., converted if necessary to) the specified destination type. The
163 // result is always returned as an uint64_t, since the representation of
164 // int64_t and uint64_t are identical. The argument can be any known const.
166 // isValidConstant is set to true if a valid constant was found.
168 virtual uint64_t ConvertConstantToIntType(const TargetMachine &target,
170 const Type *destType,
171 bool &isValidConstant) const;
173 // Create an instruction sequence to put the constant `val' into
174 // the virtual register `dest'. `val' may be a Constant or a
175 // GlobalValue, viz., the constant address of a global variable or function.
176 // The generated instructions are returned in `mvec'.
177 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
178 // Any stack space required is allocated via mcff.
180 virtual void CreateCodeToLoadConst(const TargetMachine& target,
184 std::vector<MachineInstr*>& mvec,
185 MachineCodeForInstruction& mcfi) const;
187 // Create an instruction sequence to copy an integer value `val'
188 // to a floating point value `dest' by copying to memory and back.
189 // val must be an integral type. dest must be a Float or Double.
190 // The generated instructions are returned in `mvec'.
191 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
192 // Any stack space required is allocated via mcff.
194 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
198 std::vector<MachineInstr*>& mvec,
199 MachineCodeForInstruction& mcfi) const;
201 // Similarly, create an instruction sequence to copy an FP value
202 // `val' to an integer value `dest' by copying to memory and back.
203 // The generated instructions are returned in `mvec'.
204 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
205 // Any stack space required is allocated via mcff.
207 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
211 std::vector<MachineInstr*>& mvec,
212 MachineCodeForInstruction& mcfi) const;
214 // Create instruction(s) to copy src to dest, for arbitrary types
215 // The generated instructions are returned in `mvec'.
216 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
217 // Any stack space required is allocated via mcff.
219 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
223 std::vector<MachineInstr*>& mvec,
224 MachineCodeForInstruction& mcfi) const;
226 // Create instruction sequence to produce a sign-extended register value
227 // from an arbitrary sized value (sized in bits, not bytes).
228 // The generated instructions are appended to `mvec'.
229 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
230 // Any stack space required is allocated via mcff.
232 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
236 unsigned int numLowBits,
237 std::vector<MachineInstr*>& mvec,
238 MachineCodeForInstruction& mcfi) const;
240 // Create instruction sequence to produce a zero-extended register value
241 // from an arbitrary sized value (sized in bits, not bytes).
242 // The generated instructions are appended to `mvec'.
243 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
244 // Any stack space required is allocated via mcff.
246 virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
250 unsigned int numLowBits,
251 std::vector<MachineInstr*>& mvec,
252 MachineCodeForInstruction& mcfi) const;
256 //----------------------------------------------------------------------------
257 // class UltraSparcRegInfo
259 // This class implements the virtual class TargetRegInfo for Sparc.
261 //----------------------------------------------------------------------------
263 class UltraSparcRegInfo : public TargetRegInfo {
267 // Number of registers used for passing int args (usually 6: %o0 - %o5)
269 unsigned const NumOfIntArgRegs;
271 // Number of registers used for passing float args (usually 32: %f0 - %f31)
273 unsigned const NumOfFloatArgRegs;
275 // ======================== Private Methods =============================
277 // The following methods are used to color special live ranges (e.g.
278 // function args and return values etc.) with specific hardware registers
279 // as required. See SparcRegInfo.cpp for the implementation.
281 void suggestReg4RetAddr(MachineInstr *RetMI,
282 LiveRangeInfo &LRI) const;
284 void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI) const;
286 // Helper used by the all the getRegType() functions.
287 int getRegTypeForClassAndType(unsigned regClassID, const Type* type) const;
290 // Type of registers available in Sparc. There can be several reg types
291 // in the same class. For instace, the float reg class has Single/Double
303 // The actual register classes in the Sparc
305 // **** WARNING: If this enum order is changed, also modify
306 // getRegisterClassOfValue method below since it assumes this particular
307 // order for efficiency.
310 IntRegClassID, // Integer
311 FloatRegClassID, // Float (both single/double)
312 IntCCRegClassID, // Int Condition Code
313 FloatCCRegClassID, // Float Condition code
314 SpecialRegClassID // Special (unallocated) registers
317 UltraSparcRegInfo(const UltraSparc &tgt);
319 // To find the register class used for a specified Type
321 unsigned getRegClassIDOfType(const Type *type,
322 bool isCCReg = false) const;
324 // To find the register class to which a specified register belongs
326 unsigned getRegClassIDOfRegType(int regType) const;
328 // getZeroRegNum - returns the register that contains always zero this is the
329 // unified register number
331 virtual int getZeroRegNum() const;
333 // getCallAddressReg - returns the reg used for pushing the address when a
334 // function is called. This can be used for other purposes between calls
336 unsigned getCallAddressReg() const;
338 // Returns the register containing the return address.
339 // It should be made sure that this register contains the return
340 // value when a return instruction is reached.
342 unsigned getReturnAddressReg() const;
344 // Number of registers used for passing int args (usually 6: %o0 - %o5)
345 // and float args (usually 32: %f0 - %f31)
347 unsigned const getNumOfIntArgRegs() const { return NumOfIntArgRegs; }
348 unsigned const getNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
350 // Compute which register can be used for an argument, if any
352 int regNumForIntArg(bool inCallee, bool isVarArgsCall,
353 unsigned argNo, unsigned& regClassId) const;
355 int regNumForFPArg(unsigned RegType, bool inCallee, bool isVarArgsCall,
356 unsigned argNo, unsigned& regClassId) const;
358 // The following methods are used to color special live ranges (e.g.
359 // function args and return values etc.) with specific hardware registers
360 // as required. See SparcRegInfo.cpp for the implementation for Sparc.
362 void suggestRegs4MethodArgs(const Function *Meth,
363 LiveRangeInfo& LRI) const;
365 void suggestRegs4CallArgs(MachineInstr *CallMI,
366 LiveRangeInfo& LRI) const;
368 void suggestReg4RetValue(MachineInstr *RetMI,
369 LiveRangeInfo& LRI) const;
371 void colorMethodArgs(const Function *Meth, LiveRangeInfo& LRI,
372 std::vector<MachineInstr*>& InstrnsBefore,
373 std::vector<MachineInstr*>& InstrnsAfter) const;
375 // method used for printing a register for debugging purposes
377 void printReg(const LiveRange *LR) const;
379 // returns the # of bytes of stack space allocated for each register
380 // type. For Sparc, currently we allocate 8 bytes on stack for all
381 // register types. We can optimize this later if necessary to save stack
382 // space (However, should make sure that stack alignment is correct)
384 inline int getSpilledRegSize(int RegType) const {
389 // To obtain the return value and the indirect call address (if any)
390 // contained in a CALL machine instruction
392 const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
393 const Value * getCallInstIndirectAddrVal(const MachineInstr *CallMI) const;
395 // The following methods are used to generate "copy" machine instructions
396 // for an architecture.
398 // The function regTypeNeedsScratchReg() can be used to check whether a
399 // scratch register is needed to copy a register of type `regType' to
400 // or from memory. If so, such a scratch register can be provided by
401 // the caller (e.g., if it knows which regsiters are free); otherwise
402 // an arbitrary one will be chosen and spilled by the copy instructions.
404 bool regTypeNeedsScratchReg(int RegType,
405 int& scratchRegClassId) const;
407 void cpReg2RegMI(std::vector<MachineInstr*>& mvec,
408 unsigned SrcReg, unsigned DestReg,
411 void cpReg2MemMI(std::vector<MachineInstr*>& mvec,
412 unsigned SrcReg, unsigned DestPtrReg,
413 int Offset, int RegType, int scratchReg = -1) const;
415 void cpMem2RegMI(std::vector<MachineInstr*>& mvec,
416 unsigned SrcPtrReg, int Offset, unsigned DestReg,
417 int RegType, int scratchReg = -1) const;
419 void cpValue2Value(Value *Src, Value *Dest,
420 std::vector<MachineInstr*>& mvec) const;
422 // Get the register type for a register identified different ways.
423 // Note that getRegTypeForLR(LR) != getRegTypeForDataType(LR->getType())!
424 // The reg class of a LR depends both on the Value types in it and whether
425 // they are CC registers or not (for example).
426 int getRegTypeForDataType(const Type* type) const;
427 int getRegTypeForLR(const LiveRange *LR) const;
428 int getRegType(int unifiedRegNum) const;
430 virtual unsigned getFramePointer() const;
431 virtual unsigned getStackPointer() const;
437 //---------------------------------------------------------------------------
438 // class UltraSparcSchedInfo
441 // Interface to instruction scheduling information for UltraSPARC.
442 // The parameter values above are based on UltraSPARC IIi.
443 //---------------------------------------------------------------------------
446 class UltraSparcSchedInfo: public TargetSchedInfo {
448 UltraSparcSchedInfo(const TargetMachine &tgt);
450 virtual void initializeResources();
454 //---------------------------------------------------------------------------
455 // class UltraSparcFrameInfo
458 // Interface to stack frame layout info for the UltraSPARC.
459 // Starting offsets for each area of the stack frame are aligned at
460 // a multiple of getStackFrameSizeAlignment().
461 //---------------------------------------------------------------------------
463 class UltraSparcFrameInfo: public TargetFrameInfo {
464 const TargetMachine ⌖
466 UltraSparcFrameInfo(const TargetMachine &TM)
467 : TargetFrameInfo(StackGrowsDown, StackFrameSizeAlignment, 0), target(TM) {}
470 // These methods provide constant parameters of the frame layout.
472 int getStackFrameSizeAlignment() const { return StackFrameSizeAlignment;}
473 int getMinStackFrameSize() const { return MinStackFrameSize; }
474 int getNumFixedOutgoingArgs() const { return NumFixedOutgoingArgs; }
475 int getSizeOfEachArgOnStack() const { return SizeOfEachArgOnStack; }
476 bool argsOnStackHaveFixedSize() const { return true; }
478 // This method adjusts a stack offset to meet alignment rules of target.
479 // The fixed OFFSET (0x7ff) must be subtracted and the result aligned.
480 virtual int adjustAlignment (int unalignedOffset,
482 unsigned int align) const {
483 return unalignedOffset + (growUp? +1:-1)*((unalignedOffset-OFFSET) % align);
486 // These methods compute offsets using the frame contents for a
487 // particular function. The frame contents are obtained from the
488 // MachineCodeInfoForMethod object for the given function.
490 int getFirstIncomingArgOffset (MachineFunction& mcInfo,
493 growUp = true; // arguments area grows upwards
494 return FirstIncomingArgOffsetFromFP;
496 int getFirstOutgoingArgOffset (MachineFunction& mcInfo,
499 growUp = true; // arguments area grows upwards
500 return FirstOutgoingArgOffsetFromSP;
502 int getFirstOptionalOutgoingArgOffset(MachineFunction& mcInfo,
505 growUp = true; // arguments area grows upwards
506 return FirstOptionalOutgoingArgOffsetFromSP;
509 int getFirstAutomaticVarOffset (MachineFunction& mcInfo,
511 int getRegSpillAreaOffset (MachineFunction& mcInfo,
513 int getTmpAreaOffset (MachineFunction& mcInfo,
515 int getDynamicAreaOffset (MachineFunction& mcInfo,
519 // These methods specify the base register used for each stack area
520 // (generally FP or SP)
522 virtual int getIncomingArgBaseRegNum() const {
523 return (int) target.getRegInfo().getFramePointer();
525 virtual int getOutgoingArgBaseRegNum() const {
526 return (int) target.getRegInfo().getStackPointer();
528 virtual int getOptionalOutgoingArgBaseRegNum() const {
529 return (int) target.getRegInfo().getStackPointer();
531 virtual int getAutomaticVarBaseRegNum() const {
532 return (int) target.getRegInfo().getFramePointer();
534 virtual int getRegSpillAreaBaseRegNum() const {
535 return (int) target.getRegInfo().getFramePointer();
537 virtual int getDynamicAreaBaseRegNum() const {
538 return (int) target.getRegInfo().getStackPointer();
541 virtual int getIncomingArgOffset(MachineFunction& mcInfo,
542 unsigned argNum) const {
543 assert(argsOnStackHaveFixedSize());
545 unsigned relativeOffset = argNum * getSizeOfEachArgOnStack();
546 bool growUp; // do args grow up or down
547 int firstArg = getFirstIncomingArgOffset(mcInfo, growUp);
548 return growUp ? firstArg + relativeOffset : firstArg - relativeOffset;
551 virtual int getOutgoingArgOffset(MachineFunction& mcInfo,
552 unsigned argNum) const {
553 assert(argsOnStackHaveFixedSize());
554 //assert(((int) argNum - this->getNumFixedOutgoingArgs())
555 // <= (int) mcInfo.getInfo()->getMaxOptionalNumArgs());
557 unsigned relativeOffset = argNum * getSizeOfEachArgOnStack();
558 bool growUp; // do args grow up or down
559 int firstArg = getFirstOutgoingArgOffset(mcInfo, growUp);
560 return growUp ? firstArg + relativeOffset : firstArg - relativeOffset;
564 /*----------------------------------------------------------------------
565 This diagram shows the stack frame layout used by llc on Sparc V9.
566 Note that only the location of automatic variables, spill area,
567 temporary storage, and dynamically allocated stack area are chosen
568 by us. The rest conform to the Sparc V9 ABI.
569 All stack addresses are offset by OFFSET = 0x7ff (2047).
571 Alignment assumptions and other invariants:
572 (1) %sp+OFFSET and %fp+OFFSET are always aligned on 16-byte boundary
573 (2) Variables in automatic, spill, temporary, or dynamic regions
574 are aligned according to their size as in all memory accesses.
575 (3) Everything below the dynamically allocated stack area is only used
576 during a call to another function, so it is never needed when
577 the current function is active. This is why space can be allocated
578 dynamically by incrementing %sp any time within the function.
583 %fp+OFFSET+176 Optional extra incoming arguments# 1..N
584 %fp+OFFSET+168 Incoming argument #6
586 %fp+OFFSET+128 Incoming argument #1
588 ---%fp+OFFSET-0--------Bottom of caller's stack frame--------------------
589 %fp+OFFSET-8 Automatic variables <-- ****TOP OF STACK FRAME****
594 %sp+OFFSET+176+8N Bottom of dynamically allocated stack area
595 %sp+OFFSET+168+8N Optional extra outgoing argument# N
597 %sp+OFFSET+176 Optional extra outgoing argument# 1
598 %sp+OFFSET+168 Outgoing argument #6
600 %sp+OFFSET+128 Outgoing argument #1
601 %sp+OFFSET+120 Save area for %i7
603 %sp+OFFSET+0 Save area for %l0 <-- ****BOTTOM OF STACK FRAME****
605 *----------------------------------------------------------------------*/
607 // All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
608 static const int OFFSET = (int) 0x7ff;
609 static const int StackFrameSizeAlignment = 16;
610 static const int MinStackFrameSize = 176;
611 static const int NumFixedOutgoingArgs = 6;
612 static const int SizeOfEachArgOnStack = 8;
613 static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
614 static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
615 static const int StaticAreaOffsetFromFP = 0 + OFFSET;
616 static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
617 static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
621 //---------------------------------------------------------------------------
622 // class UltraSparcCacheInfo
625 // Interface to cache parameters for the UltraSPARC.
626 // Just use defaults for now.
627 //---------------------------------------------------------------------------
629 struct UltraSparcCacheInfo: public TargetCacheInfo {
630 UltraSparcCacheInfo(const TargetMachine &T) : TargetCacheInfo(T) {}
634 //---------------------------------------------------------------------------
635 // class UltraSparcOptInfo
638 // Interface to machine-level optimization routines for the UltraSPARC.
639 //---------------------------------------------------------------------------
641 struct UltraSparcOptInfo: public TargetOptInfo {
642 UltraSparcOptInfo(const TargetMachine &T) : TargetOptInfo(T) {}
644 virtual bool IsUselessCopy (const MachineInstr* MI) const;
647 /// createAddRegNumToValuesPass - this pass adds unsigned register numbers to
648 /// instructions, since that's not done by the Sparc InstSelector, but that's
649 /// how the target-independent register allocator in the JIT likes to see
650 /// instructions. This pass enables the usage of the JIT register allocator(s).
651 Pass *createAddRegNumToValuesPass();
653 /// createStackSlotsPass - External interface to stack-slots pass that enters 2
654 /// empty slots at the top of each function stack
655 Pass *createStackSlotsPass(const TargetMachine &TM);
657 // Interface to pre-selection pass that specializes LLVM code for a target
659 Pass *createPreSelectionPass(TargetMachine &Target);
661 // External interface to peephole optimization pass operating on machine code.
662 FunctionPass *createPeepholeOptsPass(TargetMachine &Target);
665 //---------------------------------------------------------------------------
669 // Primary interface to machine description for the UltraSPARC.
670 // Primarily just initializes machine-dependent parameters in
671 // class TargetMachine, and creates machine-dependent subclasses
672 // for classes such as InstrInfo, SchedInfo and RegInfo.
673 //---------------------------------------------------------------------------
675 class UltraSparc : public TargetMachine {
676 UltraSparcInstrInfo instrInfo;
677 UltraSparcSchedInfo schedInfo;
678 UltraSparcRegInfo regInfo;
679 UltraSparcFrameInfo frameInfo;
680 UltraSparcCacheInfo cacheInfo;
681 UltraSparcOptInfo optInfo;
685 virtual const TargetInstrInfo &getInstrInfo() const { return instrInfo; }
686 virtual const TargetSchedInfo &getSchedInfo() const { return schedInfo; }
687 virtual const TargetRegInfo &getRegInfo() const { return regInfo; }
688 virtual const TargetFrameInfo &getFrameInfo() const { return frameInfo; }
689 virtual const TargetCacheInfo &getCacheInfo() const { return cacheInfo; }
690 virtual const TargetOptInfo &getOptInfo() const { return optInfo; }
692 virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
693 virtual bool addPassesToJITCompile(FunctionPassManager &PM);
694 virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
695 MachineCodeEmitter &MCE);
697 // getPrologEpilogInsertionPass - Inserts prolog/epilog code.
698 FunctionPass* getPrologEpilogInsertionPass();
700 // getFunctionAsmPrinterPass - Writes out machine code for a single function
701 Pass* getFunctionAsmPrinterPass(std::ostream &Out);
703 // getModuleAsmPrinterPass - Writes generated machine code to assembly file.
704 Pass* getModuleAsmPrinterPass(std::ostream &Out);
706 // getEmitBytecodeToAsmPass - Emits final LLVM bytecode to assembly file.
707 Pass* getEmitBytecodeToAsmPass(std::ostream &Out);
710 Pass *getFunctionInfo(std::ostream &out);