2 //***************************************************************************
7 // This file defines stuff that is to be private to the Sparc
8 // backend, but is shared among different portions of the backend.
9 //**************************************************************************/
12 #ifndef SPARC_INTERNALS_H
13 #define SPARC_INTERNALS_H
16 #include "SparcRegClassInfo.h"
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/MachineInstrInfo.h"
19 #include "llvm/Target/MachineSchedInfo.h"
20 #include "llvm/Target/MachineFrameInfo.h"
21 #include "llvm/Target/MachineCacheInfo.h"
22 #include "llvm/CodeGen/RegClass.h"
23 #include "llvm/Type.h"
25 #include <sys/types.h>
29 // OpCodeMask definitions for the Sparc V9
31 const OpCodeMask Immed = 0x00002000; // immed or reg operand?
32 const OpCodeMask Annul = 0x20000000; // annul delay instr?
33 const OpCodeMask PredictTaken = 0x00080000; // predict branch taken?
36 enum SparcInstrSchedClass {
37 SPARC_NONE, /* Instructions with no scheduling restrictions */
38 SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
39 SPARC_IEU0, /* Integer class IEU0 */
40 SPARC_IEU1, /* Integer class IEU1 */
41 SPARC_FPM, /* FP Multiply or Divide instructions */
42 SPARC_FPA, /* All other FP instructions */
43 SPARC_CTI, /* Control-transfer instructions */
44 SPARC_LD, /* Load instructions */
45 SPARC_ST, /* Store instructions */
46 SPARC_SINGLE, /* Instructions that must issue by themselves */
48 SPARC_INV, /* This should stay at the end for the next value */
49 SPARC_NUM_SCHED_CLASSES = SPARC_INV
53 //---------------------------------------------------------------------------
54 // enum SparcMachineOpCode.
55 // const MachineInstrDescriptor SparcMachineInstrDesc[]
58 // Description of UltraSparc machine instructions.
60 //---------------------------------------------------------------------------
62 enum SparcMachineOpCode {
63 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
64 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
66 #include "SparcInstr.def"
68 // End-of-array marker
70 NUM_REAL_OPCODES = PHI, // number of valid opcodes
71 NUM_TOTAL_OPCODES = INVALID_OPCODE
75 // Array of machine instruction descriptions...
76 extern const MachineInstrDescriptor SparcMachineInstrDesc[];
79 //---------------------------------------------------------------------------
80 // class UltraSparcInstrInfo
83 // Information about individual instructions.
84 // Most information is stored in the SparcMachineInstrDesc array above.
85 // Other information is computed on demand, and most such functions
86 // default to member functions in base class MachineInstrInfo.
87 //---------------------------------------------------------------------------
89 class UltraSparcInstrInfo : public MachineInstrInfo {
91 /*ctor*/ UltraSparcInstrInfo(const TargetMachine& tgt);
93 virtual bool hasResultInterlock (MachineOpCode opCode) const
95 // All UltraSPARC instructions have interlocks (note that delay slots
96 // are not considered here).
97 // However, instructions that use the result of an FCMP produce a
98 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
99 // Force the compiler to insert a software interlock (i.e., gap of
100 // 2 other groups, including NOPs if necessary).
101 return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
104 //-------------------------------------------------------------------------
105 // Code generation support for creating individual machine instructions
106 //-------------------------------------------------------------------------
108 // Create an instruction sequence to put the constant `val' into
109 // the virtual register `dest'. The generated instructions are
110 // returned in `minstrVec'. Any temporary registers (TmpInstruction)
111 // created are returned in `tempVec'.
113 virtual void CreateCodeToLoadConst(Value* val,
115 vector<MachineInstr*>& minstrVec,
116 vector<TmpInstruction*>& tempVec) const;
119 // Create an instruction sequence to copy an integer value `val'
120 // to a floating point value `dest' by copying to memory and back.
121 // val must be an integral type. dest must be a Float or Double.
122 // The generated instructions are returned in `minstrVec'.
123 // Any temp. registers (TmpInstruction) created are returned in `tempVec'.
125 virtual void CreateCodeToCopyIntToFloat(Method* method,
128 vector<MachineInstr*>& minstrVec,
129 vector<TmpInstruction*>& tempVec,
130 TargetMachine& target) const;
132 // Similarly, create an instruction sequence to copy an FP value
133 // `val' to an integer value `dest' by copying to memory and back.
134 // See the previous function for information about return values.
136 virtual void CreateCodeToCopyFloatToInt(Method* method,
139 vector<MachineInstr*>& minstrVec,
140 vector<TmpInstruction*>& tempVec,
141 TargetMachine& target) const;
143 // create copy instruction(s)
145 CreateCopyInstructionsByType(const TargetMachine& target,
148 vector<MachineInstr*>& minstrVec) const;
154 //----------------------------------------------------------------------------
155 // class UltraSparcRegInfo
157 //----------------------------------------------------------------------------
165 class UltraSparcRegInfo : public MachineRegInfo
170 // The actual register classes in the Sparc
180 // Type of registers available in Sparc. There can be several reg types
181 // in the same class. For instace, the float reg class has Single/Double
191 // the size of a value (int, float, etc..) stored in the stack frame
195 // WARNING: If the above enum order must be changed, also modify
196 // getRegisterClassOfValue method below since it assumes this particular
197 // order for efficiency.
200 // reverse pointer to get info about the ultra sparc machine
201 const UltraSparc *const UltraSparcInfo;
203 // Both int and float rguments can be passed in 6 int regs -
204 // %o0 to %o5 (cannot be changed)
205 unsigned const NumOfIntArgRegs;
206 unsigned const NumOfFloatArgRegs;
207 int const InvalidRegNum;
208 int SizeOfOperandOnStack;
212 //void setCallArgColor(LiveRange *const LR, const unsigned RegNo) const;
214 void setCallOrRetArgCol(LiveRange *const LR, const unsigned RegNo,
215 const MachineInstr *MI,AddedInstrMapType &AIMap)const;
217 MachineInstr * getCopy2RegMI(const Value *SrcVal, const unsigned Reg,
218 unsigned RegClassID) const ;
221 void suggestReg4RetAddr(const MachineInstr * RetMI,
222 LiveRangeInfo& LRI) const;
224 void suggestReg4CallAddr(const MachineInstr * CallMI, LiveRangeInfo& LRI,
225 vector<RegClass *> RCList) const;
228 Value *getValue4ReturnAddr( const MachineInstr * MInst ) const ;
230 int getRegType(const LiveRange *const LR) const {
234 switch( (LR->getRegClass())->getID() ) {
236 case IntRegClassID: return IntRegType;
238 case FloatRegClassID:
239 Typ = LR->getTypeID();
240 if( Typ == Type::FloatTyID )
241 return FPSingleRegType;
242 else if( Typ == Type::DoubleTyID )
243 return FPDoubleRegType;
244 else assert(0 && "Unknown type in FloatRegClass");
246 case IntCCRegClassID: return IntCCRegType;
248 case FloatCCRegClassID: return FloatCCRegType ;
250 default: assert( 0 && "Unknown reg class ID");
256 int getRegType(const Value *const Val) const {
260 switch( getRegClassIDOfValue(Val) ) {
262 case IntRegClassID: return IntRegType;
264 case FloatRegClassID:
265 Typ = (Val->getType())->getPrimitiveID();
266 if( Typ == Type::FloatTyID )
267 return FPSingleRegType;
268 else if( Typ == Type::DoubleTyID )
269 return FPDoubleRegType;
270 else assert(0 && "Unknown type in FloatRegClass");
272 case IntCCRegClassID: return IntCCRegType;
274 case FloatCCRegClassID: return FloatCCRegType ;
276 default: assert( 0 && "Unknown reg class ID");
283 int getRegType(int reg) const {
286 else if ( reg < (32 + 32) )
287 return FPSingleRegType;
288 else if ( reg < (64 + 32) )
289 return FPDoubleRegType;
290 else if( reg < (64+32+4) )
291 return FloatCCRegType;
292 else if( reg < (64+32+4+2) )
295 assert(0 && "Invalid register number in getRegType");
300 // ***TODO: See this method is necessary
302 MachineInstr * cpValue2RegMI(Value * Val, const unsigned DestReg,
303 const int RegType) const;
305 const Value *getCallInstRetAddr(const MachineInstr *CallMI) const;
306 const unsigned getCallInstNumArgs(const MachineInstr *CallMI) const;
309 MachineInstr * cpCCR2IntMI(const unsigned IntReg) const;
310 MachineInstr * cpInt2CCRMI(const unsigned IntReg) const;
314 void moveInst2OrdVec(vector<MachineInstr *> &OrdVec, MachineInstr *UnordInst,
315 PhyRegAlloc &PRA ) const;
317 void OrderAddedInstrns( vector<MachineInstr *> &UnordVec,
318 vector<MachineInstr *> &OrdVec,
319 PhyRegAlloc &PRA) const;
330 UltraSparcRegInfo(const TargetMachine& tgt ) : MachineRegInfo(tgt),
331 UltraSparcInfo(& (const UltraSparc&) tgt),
333 NumOfFloatArgRegs(32),
335 SizeOfOperandOnStack(8)
337 MachineRegClassArr.push_back( new SparcIntRegClass(IntRegClassID) );
338 MachineRegClassArr.push_back( new SparcFloatRegClass(FloatRegClassID) );
339 MachineRegClassArr.push_back( new SparcIntCCRegClass(IntCCRegClassID) );
340 MachineRegClassArr.push_back( new SparcFloatCCRegClass(FloatCCRegClassID));
342 assert( SparcFloatRegOrder::StartOfNonVolatileRegs == 32 &&
343 "32 Float regs are used for float arg passing");
348 ~UltraSparcRegInfo(void) { } // empty destructor
351 inline const UltraSparc & getUltraSparcInfo() const {
352 return *UltraSparcInfo;
357 inline unsigned getRegClassIDOfValue (const Value *const Val,
358 bool isCCReg = false) const {
360 Type::PrimitiveID ty = (Val->getType())->getPrimitiveID();
364 if( (ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
365 (ty == Type::MethodTyID) || (ty == Type::PointerTyID) )
366 res = IntRegClassID; // sparc int reg (ty=0: void)
367 else if( ty <= Type::DoubleTyID)
368 res = FloatRegClassID; // sparc float reg class
370 cerr << "TypeID: " << ty << endl;
371 assert(0 && "Cannot resolve register class for type");
376 return res + 2; // corresponidng condition code regiser
381 // returns the register tha contains always zero
382 // this is the unified register number
383 inline int getZeroRegNum() const { return SparcIntRegOrder::g0; }
385 // returns the reg used for pushing the address when a method is called.
386 // This can be used for other purposes between calls
387 unsigned getCallAddressReg() const { return SparcIntRegOrder::o7; }
390 // and when we return from a method. It should be made sure that this
391 // register contains the return value when a return instruction is reached.
392 unsigned getReturnAddressReg() const { return SparcIntRegOrder::i7; }
394 void suggestRegs4MethodArgs(const Method *const Meth,
395 LiveRangeInfo& LRI) const;
397 void suggestRegs4CallArgs(const MachineInstr *const CallMI,
398 LiveRangeInfo& LRI, vector<RegClass *> RCL) const;
400 void suggestReg4RetValue(const MachineInstr *const RetMI,
401 LiveRangeInfo& LRI ) const;
404 void colorMethodArgs(const Method *const Meth, LiveRangeInfo& LRI,
405 AddedInstrns *const FirstAI) const;
407 void colorCallArgs(const MachineInstr *const CallMI, LiveRangeInfo& LRI,
408 AddedInstrns *const CallAI, PhyRegAlloc &PRA) const;
410 void colorRetValue(const MachineInstr *const RetI, LiveRangeInfo& LRI,
411 AddedInstrns *const RetAI) const;
414 // bool handleSpecialMInstr(const MachineInstr * MInst,
415 // LiveRangeInfo& LRI, vector<RegClass *> RCL) const;
418 static void printReg(const LiveRange *const LR) ;
420 // this method provides a unique number for each register
421 inline int getUnifiedRegNum(int RegClassID, int reg) const {
423 if( RegClassID == IntRegClassID && reg < 32 )
425 else if ( RegClassID == FloatRegClassID && reg < 64)
426 return reg + 32; // we have 32 int regs
427 else if( RegClassID == FloatCCRegClassID && reg < 4)
428 return reg + 32 + 64; // 32 int, 64 float
429 else if( RegClassID == IntCCRegClassID )
430 return 4+ 32 + 64; // only int cc reg
431 else if (reg==InvalidRegNum)
432 return InvalidRegNum;
434 assert(0 && "Invalid register class or reg number");
438 // given the unified register number, this gives the name
439 inline const string getUnifiedRegName(int reg) const {
441 return SparcIntRegOrder::getRegName(reg);
442 else if ( reg < (64 + 32) )
443 return SparcFloatRegOrder::getRegName( reg - 32);
444 else if( reg < (64+32+4) )
445 return SparcFloatCCRegOrder::getRegName( reg -32 - 64);
446 else if( reg < (64+32+4+2) ) // two names: %xcc and %ccr
447 return SparcIntCCRegOrder::getRegName( reg -32 - 64 - 4);
448 else if (reg== InvalidRegNum) //****** TODO: Remove */
451 assert(0 && "Invalid register number");
455 inline unsigned int getRegNumInCallersWindow(int reg) {
456 if (reg == InvalidRegNum || reg >= 32)
458 return SparcIntRegOrder::getRegNumInCallersWindow(reg);
461 inline bool mustBeRemappedInCallersWindow(int reg) {
462 return (reg != InvalidRegNum && reg < 32);
465 const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
467 MachineInstr * cpReg2RegMI(const unsigned SrcReg, const unsigned DestReg,
468 const int RegType) const;
470 MachineInstr * cpReg2MemMI(const unsigned SrcReg, const unsigned DestPtrReg,
471 const int Offset, const int RegType) const;
473 MachineInstr * cpMem2RegMI(const unsigned SrcPtrReg, const int Offset,
474 const unsigned DestReg, const int RegType) const;
476 MachineInstr* cpValue2Value(Value *Src, Value *Dest) const;
479 inline bool isRegVolatile(const int RegClassID, const int Reg) const {
480 return (MachineRegClassArr[RegClassID])->isRegVolatile(Reg);
484 inline unsigned getFramePointer() const {
485 return SparcIntRegOrder::i6;
488 inline unsigned getStackPointer() const {
489 return SparcIntRegOrder::o6;
492 inline int getInvalidRegNum() const {
493 return InvalidRegNum;
497 void insertCallerSavingCode(const MachineInstr *MInst,
498 const BasicBlock *BB, PhyRegAlloc &PRA ) const;
505 /*---------------------------------------------------------------------------
506 Scheduling guidelines for SPARC IIi:
508 I-Cache alignment rules (pg 326)
509 -- Align a branch target instruction so that it's entire group is within
510 the same cache line (may be 1-4 instructions).
511 ** Don't let a branch that is predicted taken be the last instruction
512 on an I-cache line: delay slot will need an entire line to be fetched
513 -- Make a FP instruction or a branch be the 4th instruction in a group.
514 For branches, there are tradeoffs in reordering to make this happen
516 ** Don't put a branch in a group that crosses a 32-byte boundary!
517 An artificial branch is inserted after every 32 bytes, and having
518 another branch will force the group to be broken into 2 groups.
521 -- Don't let a loop span two memory pages, if possible
523 Branch prediction performance:
524 -- Don't make the branch in a delay slot the target of a branch
525 -- Try not to have 2 predicted branches within a group of 4 instructions
526 (because each such group has a single branch target field).
527 -- Try to align branches in slots 0, 2, 4 or 6 of a cache line (to avoid
528 the wrong prediction bits being used in some cases).
530 D-Cache timing constraints:
531 -- Signed int loads of less than 64 bits have 3 cycle latency, not 2
532 -- All other loads that hit in D-Cache have 2 cycle latency
533 -- All loads are returned IN ORDER, so a D-Cache miss will delay a later hit
534 -- Mis-aligned loads or stores cause a trap. In particular, replace
535 mis-aligned FP double precision l/s with 2 single-precision l/s.
536 -- Simulations of integer codes show increase in avg. group size of
537 33% when code (including esp. non-faulting loads) is moved across
538 one branch, and 50% across 2 branches.
540 E-Cache timing constraints:
541 -- Scheduling for E-cache (D-Cache misses) is effective (due to load buffering)
543 Store buffer timing constraints:
544 -- Stores can be executed in same cycle as instruction producing the value
545 -- Stores are buffered and have lower priority for E-cache until
546 highwater mark is reached in the store buffer (5 stores)
548 Pipeline constraints:
549 -- Shifts can only use IEU0.
550 -- CC setting instructions can only use IEU1.
551 -- Several other instructions must only use IEU1:
552 EDGE(?), ARRAY(?), CALL, JMPL, BPr, PST, and FCMP.
553 -- Two instructions cannot store to the same register file in a single cycle
554 (single write port per file).
556 Issue and grouping constraints:
557 -- FP and branch instructions must use slot 4.
558 -- Shift instructions cannot be grouped with other IEU0-specific instructions.
559 -- CC setting instructions cannot be grouped with other IEU1-specific instrs.
560 -- Several instructions must be issued in a single-instruction group:
561 MOVcc or MOVr, MULs/x and DIVs/x, SAVE/RESTORE, many others
562 -- A CALL or JMPL breaks a group, ie, is not combined with subsequent instrs.
566 Branch delay slot scheduling rules:
567 -- A CTI couple (two back-to-back CTI instructions in the dynamic stream)
568 has a 9-instruction penalty: the entire pipeline is flushed when the
569 second instruction reaches stage 9 (W-Writeback).
570 -- Avoid putting multicycle instructions, and instructions that may cause
571 load misses, in the delay slot of an annulling branch.
572 -- Avoid putting WR, SAVE..., RESTORE and RETURN instructions in the
573 delay slot of an annulling branch.
575 *--------------------------------------------------------------------------- */
577 //---------------------------------------------------------------------------
578 // List of CPUResources for UltraSPARC IIi.
579 //---------------------------------------------------------------------------
581 const CPUResource AllIssueSlots( "All Instr Slots", 4);
582 const CPUResource IntIssueSlots( "Int Instr Slots", 3);
583 const CPUResource First3IssueSlots("Instr Slots 0-3", 3);
584 const CPUResource LSIssueSlots( "Load-Store Instr Slot", 1);
585 const CPUResource CTIIssueSlots( "Ctrl Transfer Instr Slot", 1);
586 const CPUResource FPAIssueSlots( "Int Instr Slot 1", 1);
587 const CPUResource FPMIssueSlots( "Int Instr Slot 1", 1);
589 // IEUN instructions can use either Alu and should use IAluN.
590 // IEU0 instructions must use Alu 1 and should use both IAluN and IAlu0.
591 // IEU1 instructions must use Alu 2 and should use both IAluN and IAlu1.
592 const CPUResource IAluN("Int ALU 1or2", 2);
593 const CPUResource IAlu0("Int ALU 1", 1);
594 const CPUResource IAlu1("Int ALU 2", 1);
596 const CPUResource LSAluC1("Load/Store Unit Addr Cycle", 1);
597 const CPUResource LSAluC2("Load/Store Unit Issue Cycle", 1);
598 const CPUResource LdReturn("Load Return Unit", 1);
600 const CPUResource FPMAluC1("FP Mul/Div Alu Cycle 1", 1);
601 const CPUResource FPMAluC2("FP Mul/Div Alu Cycle 2", 1);
602 const CPUResource FPMAluC3("FP Mul/Div Alu Cycle 3", 1);
604 const CPUResource FPAAluC1("FP Other Alu Cycle 1", 1);
605 const CPUResource FPAAluC2("FP Other Alu Cycle 2", 1);
606 const CPUResource FPAAluC3("FP Other Alu Cycle 3", 1);
608 const CPUResource IRegReadPorts("Int Reg ReadPorts", INT_MAX); // CHECK
609 const CPUResource IRegWritePorts("Int Reg WritePorts", 2); // CHECK
610 const CPUResource FPRegReadPorts("FP Reg Read Ports", INT_MAX); // CHECK
611 const CPUResource FPRegWritePorts("FP Reg Write Ports", 1); // CHECK
613 const CPUResource CTIDelayCycle( "CTI delay cycle", 1);
614 const CPUResource FCMPDelayCycle("FCMP delay cycle", 1);
617 //---------------------------------------------------------------------------
618 // const InstrClassRUsage SparcRUsageDesc[]
621 // Resource usage information for instruction in each scheduling class.
622 // The InstrRUsage Objects for individual classes are specified first.
623 // Note that fetch and decode are decoupled from the execution pipelines
624 // via an instr buffer, so they are not included in the cycles below.
625 //---------------------------------------------------------------------------
627 const InstrClassRUsage NoneClassRUsage = {
632 /* isSingleIssue */ false,
633 /* breaksGroup */ false,
637 /* feasibleSlots[] */ { 0, 1, 2, 3 },
651 const InstrClassRUsage IEUNClassRUsage = {
656 /* isSingleIssue */ false,
657 /* breaksGroup */ false,
661 /* feasibleSlots[] */ { 0, 1, 2 },
665 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
666 { IntIssueSlots.rid, 0, 1 },
667 /*Cycle E */ { IAluN.rid, 1, 1 },
672 /*Cycle W */ { IRegWritePorts.rid, 6, 1 }
676 const InstrClassRUsage IEU0ClassRUsage = {
681 /* isSingleIssue */ false,
682 /* breaksGroup */ false,
686 /* feasibleSlots[] */ { 0, 1, 2 },
690 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
691 { IntIssueSlots.rid, 0, 1 },
692 /*Cycle E */ { IAluN.rid, 1, 1 },
698 /*Cycle W */ { IRegWritePorts.rid, 6, 1 }
702 const InstrClassRUsage IEU1ClassRUsage = {
707 /* isSingleIssue */ false,
708 /* breaksGroup */ false,
712 /* feasibleSlots[] */ { 0, 1, 2 },
716 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
717 { IntIssueSlots.rid, 0, 1 },
718 /*Cycle E */ { IAluN.rid, 1, 1 },
724 /*Cycle W */ { IRegWritePorts.rid, 6, 1 }
728 const InstrClassRUsage FPMClassRUsage = {
733 /* isSingleIssue */ false,
734 /* breaksGroup */ false,
738 /* feasibleSlots[] */ { 0, 1, 2, 3 },
742 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
743 { FPMIssueSlots.rid, 0, 1 },
744 /*Cycle E */ { FPRegReadPorts.rid, 1, 1 },
745 /*Cycle C */ { FPMAluC1.rid, 2, 1 },
746 /*Cycle N1*/ { FPMAluC2.rid, 3, 1 },
747 /*Cycle N1*/ { FPMAluC3.rid, 4, 1 },
749 /*Cycle W */ { FPRegWritePorts.rid, 6, 1 }
753 const InstrClassRUsage FPAClassRUsage = {
758 /* isSingleIssue */ false,
759 /* breaksGroup */ false,
763 /* feasibleSlots[] */ { 0, 1, 2, 3 },
767 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
768 { FPAIssueSlots.rid, 0, 1 },
769 /*Cycle E */ { FPRegReadPorts.rid, 1, 1 },
770 /*Cycle C */ { FPAAluC1.rid, 2, 1 },
771 /*Cycle N1*/ { FPAAluC2.rid, 3, 1 },
772 /*Cycle N1*/ { FPAAluC3.rid, 4, 1 },
774 /*Cycle W */ { FPRegWritePorts.rid, 6, 1 }
778 const InstrClassRUsage LDClassRUsage = {
783 /* isSingleIssue */ false,
784 /* breaksGroup */ false,
788 /* feasibleSlots[] */ { 0, 1, 2, },
792 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
793 { First3IssueSlots.rid, 0, 1 },
794 { LSIssueSlots.rid, 0, 1 },
795 /*Cycle E */ { LSAluC1.rid, 1, 1 },
796 /*Cycle C */ { LSAluC2.rid, 2, 1 },
797 { LdReturn.rid, 2, 1 },
801 /*Cycle W */ { IRegWritePorts.rid, 6, 1 }
805 const InstrClassRUsage STClassRUsage = {
810 /* isSingleIssue */ false,
811 /* breaksGroup */ false,
815 /* feasibleSlots[] */ { 0, 1, 2 },
819 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
820 { First3IssueSlots.rid, 0, 1 },
821 { LSIssueSlots.rid, 0, 1 },
822 /*Cycle E */ { LSAluC1.rid, 1, 1 },
823 /*Cycle C */ { LSAluC2.rid, 2, 1 }
831 const InstrClassRUsage CTIClassRUsage = {
836 /* isSingleIssue */ false,
837 /* breaksGroup */ false,
841 /* feasibleSlots[] */ { 0, 1, 2, 3 },
845 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
846 { CTIIssueSlots.rid, 0, 1 },
847 /*Cycle E */ { IAlu0.rid, 1, 1 },
848 /*Cycles E-C */ { CTIDelayCycle.rid, 1, 2 }
857 const InstrClassRUsage SingleClassRUsage = {
862 /* isSingleIssue */ true,
863 /* breaksGroup */ false,
867 /* feasibleSlots[] */ { 0 },
871 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
872 { AllIssueSlots.rid, 0, 1 },
873 { AllIssueSlots.rid, 0, 1 },
874 { AllIssueSlots.rid, 0, 1 },
875 /*Cycle E */ { IAlu0.rid, 1, 1 }
885 const InstrClassRUsage SparcRUsageDesc[] = {
899 //---------------------------------------------------------------------------
900 // const InstrIssueDelta SparcInstrIssueDeltas[]
903 // Changes to issue restrictions information in InstrClassRUsage for
904 // instructions that differ from other instructions in their class.
905 //---------------------------------------------------------------------------
907 const InstrIssueDelta SparcInstrIssueDeltas[] = {
909 // opCode, isSingleIssue, breaksGroup, numBubbles
911 // Special cases for single-issue only
912 // Other single issue cases are below.
913 //{ LDDA, true, true, 0 },
914 //{ STDA, true, true, 0 },
915 //{ LDDF, true, true, 0 },
916 //{ LDDFA, true, true, 0 },
917 { ADDC, true, true, 0 },
918 { ADDCcc, true, true, 0 },
919 { SUBC, true, true, 0 },
920 { SUBCcc, true, true, 0 },
921 //{ LDSTUB, true, true, 0 },
922 //{ SWAP, true, true, 0 },
923 //{ SWAPA, true, true, 0 },
924 //{ CAS, true, true, 0 },
925 //{ CASA, true, true, 0 },
926 //{ CASX, true, true, 0 },
927 //{ CASXA, true, true, 0 },
928 //{ LDFSR, true, true, 0 },
929 //{ LDFSRA, true, true, 0 },
930 //{ LDXFSR, true, true, 0 },
931 //{ LDXFSRA, true, true, 0 },
932 //{ STFSR, true, true, 0 },
933 //{ STFSRA, true, true, 0 },
934 //{ STXFSR, true, true, 0 },
935 //{ STXFSRA, true, true, 0 },
936 //{ SAVED, true, true, 0 },
937 //{ RESTORED, true, true, 0 },
938 //{ FLUSH, true, true, 9 },
939 //{ FLUSHW, true, true, 9 },
940 //{ ALIGNADDR, true, true, 0 },
941 { RETURN, true, true, 0 },
942 //{ DONE, true, true, 0 },
943 //{ RETRY, true, true, 0 },
944 //{ TCC, true, true, 0 },
945 //{ SHUTDOWN, true, true, 0 },
947 // Special cases for breaking group *before*
948 // CURRENTLY NOT SUPPORTED!
949 { CALL, false, false, 0 },
950 { JMPLCALL, false, false, 0 },
951 { JMPLRET, false, false, 0 },
953 // Special cases for breaking the group *after*
954 { MULX, true, true, (4+34)/2 },
955 { FDIVS, false, true, 0 },
956 { FDIVD, false, true, 0 },
957 { FDIVQ, false, true, 0 },
958 { FSQRTS, false, true, 0 },
959 { FSQRTD, false, true, 0 },
960 { FSQRTQ, false, true, 0 },
961 //{ FCMP{LE,GT,NE,EQ}, false, true, 0 },
963 // Instructions that introduce bubbles
964 //{ MULScc, true, true, 2 },
965 //{ SMULcc, true, true, (4+18)/2 },
966 //{ UMULcc, true, true, (4+19)/2 },
967 { SDIVX, true, true, 68 },
968 { UDIVX, true, true, 68 },
969 //{ SDIVcc, true, true, 36 },
970 //{ UDIVcc, true, true, 37 },
971 { WRCCR, true, true, 4 },
972 //{ WRPR, true, true, 4 },
973 //{ RDCCR, true, true, 0 }, // no bubbles after, but see below
974 //{ RDPR, true, true, 0 },
978 //---------------------------------------------------------------------------
979 // const InstrRUsageDelta SparcInstrUsageDeltas[]
982 // Changes to resource usage information in InstrClassRUsage for
983 // instructions that differ from other instructions in their class.
984 //---------------------------------------------------------------------------
986 const InstrRUsageDelta SparcInstrUsageDeltas[] = {
988 // MachineOpCode, Resource, Start cycle, Num cycles
991 // JMPL counts as a load/store instruction for issue!
993 { JMPLCALL, LSIssueSlots.rid, 0, 1 },
994 { JMPLRET, LSIssueSlots.rid, 0, 1 },
997 // Many instructions cannot issue for the next 2 cycles after an FCMP
998 // We model that with a fake resource FCMPDelayCycle.
1000 { FCMPS, FCMPDelayCycle.rid, 1, 3 },
1001 { FCMPD, FCMPDelayCycle.rid, 1, 3 },
1002 { FCMPQ, FCMPDelayCycle.rid, 1, 3 },
1004 { MULX, FCMPDelayCycle.rid, 1, 1 },
1005 { SDIVX, FCMPDelayCycle.rid, 1, 1 },
1006 { UDIVX, FCMPDelayCycle.rid, 1, 1 },
1007 //{ SMULcc, FCMPDelayCycle.rid, 1, 1 },
1008 //{ UMULcc, FCMPDelayCycle.rid, 1, 1 },
1009 //{ SDIVcc, FCMPDelayCycle.rid, 1, 1 },
1010 //{ UDIVcc, FCMPDelayCycle.rid, 1, 1 },
1011 { STD, FCMPDelayCycle.rid, 1, 1 },
1012 { FMOVRSZ, FCMPDelayCycle.rid, 1, 1 },
1013 { FMOVRSLEZ,FCMPDelayCycle.rid, 1, 1 },
1014 { FMOVRSLZ, FCMPDelayCycle.rid, 1, 1 },
1015 { FMOVRSNZ, FCMPDelayCycle.rid, 1, 1 },
1016 { FMOVRSGZ, FCMPDelayCycle.rid, 1, 1 },
1017 { FMOVRSGEZ,FCMPDelayCycle.rid, 1, 1 },
1020 // Some instructions are stalled in the GROUP stage if a CTI is in
1021 // the E or C stage. We model that with a fake resource CTIDelayCycle.
1023 { LDD, CTIDelayCycle.rid, 1, 1 },
1024 //{ LDDA, CTIDelayCycle.rid, 1, 1 },
1025 //{ LDDSTUB, CTIDelayCycle.rid, 1, 1 },
1026 //{ LDDSTUBA, CTIDelayCycle.rid, 1, 1 },
1027 //{ SWAP, CTIDelayCycle.rid, 1, 1 },
1028 //{ SWAPA, CTIDelayCycle.rid, 1, 1 },
1029 //{ CAS, CTIDelayCycle.rid, 1, 1 },
1030 //{ CASA, CTIDelayCycle.rid, 1, 1 },
1031 //{ CASX, CTIDelayCycle.rid, 1, 1 },
1032 //{ CASXA, CTIDelayCycle.rid, 1, 1 },
1035 // Signed int loads of less than dword size return data in cycle N1 (not C)
1036 // and put all loads in consecutive cycles into delayed load return mode.
1038 { LDSB, LdReturn.rid, 2, -1 },
1039 { LDSB, LdReturn.rid, 3, 1 },
1041 { LDSH, LdReturn.rid, 2, -1 },
1042 { LDSH, LdReturn.rid, 3, 1 },
1044 { LDSW, LdReturn.rid, 2, -1 },
1045 { LDSW, LdReturn.rid, 3, 1 },
1048 // RDPR from certain registers and RD from any register are not dispatchable
1049 // until four clocks after they reach the head of the instr. buffer.
1050 // Together with their single-issue requirement, this means all four issue
1051 // slots are effectively blocked for those cycles, plus the issue cycle.
1052 // This does not increase the latency of the instruction itself.
1054 { RDCCR, AllIssueSlots.rid, 0, 5 },
1055 { RDCCR, AllIssueSlots.rid, 0, 5 },
1056 { RDCCR, AllIssueSlots.rid, 0, 5 },
1057 { RDCCR, AllIssueSlots.rid, 0, 5 },
1059 #undef EXPLICIT_BUBBLES_NEEDED
1060 #ifdef EXPLICIT_BUBBLES_NEEDED
1062 // MULScc inserts one bubble.
1063 // This means it breaks the current group (captured in UltraSparcSchedInfo)
1064 // *and occupies all issue slots for the next cycle
1066 //{ MULScc, AllIssueSlots.rid, 2, 2-1 },
1067 //{ MULScc, AllIssueSlots.rid, 2, 2-1 },
1068 //{ MULScc, AllIssueSlots.rid, 2, 2-1 },
1069 //{ MULScc, AllIssueSlots.rid, 2, 2-1 },
1072 // SMULcc inserts between 4 and 18 bubbles, depending on #leading 0s in rs1.
1073 // We just model this with a simple average.
1075 //{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
1076 //{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
1077 //{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
1078 //{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
1080 // SMULcc inserts between 4 and 19 bubbles, depending on #leading 0s in rs1.
1081 //{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
1082 //{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
1083 //{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
1084 //{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
1087 // MULX inserts between 4 and 34 bubbles, depending on #leading 0s in rs1.
1089 { MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
1090 { MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
1091 { MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
1092 { MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
1095 // SDIVcc inserts 36 bubbles.
1097 //{ SDIVcc, AllIssueSlots.rid, 2, 36-1 },
1098 //{ SDIVcc, AllIssueSlots.rid, 2, 36-1 },
1099 //{ SDIVcc, AllIssueSlots.rid, 2, 36-1 },
1100 //{ SDIVcc, AllIssueSlots.rid, 2, 36-1 },
1102 // UDIVcc inserts 37 bubbles.
1103 //{ UDIVcc, AllIssueSlots.rid, 2, 37-1 },
1104 //{ UDIVcc, AllIssueSlots.rid, 2, 37-1 },
1105 //{ UDIVcc, AllIssueSlots.rid, 2, 37-1 },
1106 //{ UDIVcc, AllIssueSlots.rid, 2, 37-1 },
1109 // SDIVX inserts 68 bubbles.
1111 { SDIVX, AllIssueSlots.rid, 2, 68-1 },
1112 { SDIVX, AllIssueSlots.rid, 2, 68-1 },
1113 { SDIVX, AllIssueSlots.rid, 2, 68-1 },
1114 { SDIVX, AllIssueSlots.rid, 2, 68-1 },
1117 // UDIVX inserts 68 bubbles.
1119 { UDIVX, AllIssueSlots.rid, 2, 68-1 },
1120 { UDIVX, AllIssueSlots.rid, 2, 68-1 },
1121 { UDIVX, AllIssueSlots.rid, 2, 68-1 },
1122 { UDIVX, AllIssueSlots.rid, 2, 68-1 },
1125 // WR inserts 4 bubbles.
1127 //{ WR, AllIssueSlots.rid, 2, 68-1 },
1128 //{ WR, AllIssueSlots.rid, 2, 68-1 },
1129 //{ WR, AllIssueSlots.rid, 2, 68-1 },
1130 //{ WR, AllIssueSlots.rid, 2, 68-1 },
1133 // WRPR inserts 4 bubbles.
1135 //{ WRPR, AllIssueSlots.rid, 2, 68-1 },
1136 //{ WRPR, AllIssueSlots.rid, 2, 68-1 },
1137 //{ WRPR, AllIssueSlots.rid, 2, 68-1 },
1138 //{ WRPR, AllIssueSlots.rid, 2, 68-1 },
1141 // DONE inserts 9 bubbles.
1143 //{ DONE, AllIssueSlots.rid, 2, 9-1 },
1144 //{ DONE, AllIssueSlots.rid, 2, 9-1 },
1145 //{ DONE, AllIssueSlots.rid, 2, 9-1 },
1146 //{ DONE, AllIssueSlots.rid, 2, 9-1 },
1149 // RETRY inserts 9 bubbles.
1151 //{ RETRY, AllIssueSlots.rid, 2, 9-1 },
1152 //{ RETRY, AllIssueSlots.rid, 2, 9-1 },
1153 //{ RETRY, AllIssueSlots.rid, 2, 9-1 },
1154 //{ RETRY, AllIssueSlots.rid, 2, 9-1 },
1156 #endif /*EXPLICIT_BUBBLES_NEEDED */
1161 // Additional delays to be captured in code:
1162 // 1. RDPR from several state registers (page 349)
1163 // 2. RD from *any* register (page 349)
1164 // 3. Writes to TICK, PSTATE, TL registers and FLUSH{W} instr (page 349)
1165 // 4. Integer store can be in same group as instr producing value to store.
1166 // 5. BICC and BPICC can be in the same group as instr producing CC (pg 350)
1167 // 6. FMOVr cannot be in the same or next group as an IEU instr (pg 351).
1168 // 7. The second instr. of a CTI group inserts 9 bubbles (pg 351)
1169 // 8. WR{PR}, SVAE, SAVED, RESTORE, RESTORED, RETURN, RETRY, and DONE that
1170 // follow an annulling branch cannot be issued in the same group or in
1171 // the 3 groups following the branch.
1172 // 9. A predicted annulled load does not stall dependent instructions.
1173 // Other annulled delay slot instructions *do* stall dependents, so
1174 // nothing special needs to be done for them during scheduling.
1175 //10. Do not put a load use that may be annulled in the same group as the
1176 // branch. The group will stall until the load returns.
1177 //11. Single-prec. FP loads lock 2 registers, for dependency checking.
1180 // Additional delays we cannot or will not capture:
1181 // 1. If DCTI is last word of cache line, it is delayed until next line can be
1182 // fetched. Also, other DCTI alignment-related delays (pg 352)
1183 // 2. Load-after-store is delayed by 7 extra cycles if load hits in D-Cache.
1184 // Also, several other store-load and load-store conflicts (pg 358)
1185 // 3. MEMBAR, LD{X}FSR, LDD{A} and a bunch of other load stalls (pg 358)
1186 // 4. There can be at most 8 outstanding buffered store instructions
1187 // (including some others like MEMBAR, LDSTUB, CAS{AX}, and FLUSH)
1191 //---------------------------------------------------------------------------
1192 // class UltraSparcSchedInfo
1195 // Interface to instruction scheduling information for UltraSPARC.
1196 // The parameter values above are based on UltraSPARC IIi.
1197 //---------------------------------------------------------------------------
1200 class UltraSparcSchedInfo: public MachineSchedInfo {
1202 /*ctor*/ UltraSparcSchedInfo (const TargetMachine& tgt);
1203 /*dtor*/ virtual ~UltraSparcSchedInfo () {}
1205 virtual void initializeResources ();
1209 //---------------------------------------------------------------------------
1210 // class UltraSparcFrameInfo
1213 // Interface to stack frame layout info for the UltraSPARC.
1214 //---------------------------------------------------------------------------
1216 class UltraSparcFrameInfo: public MachineFrameInfo {
1218 /*ctor*/ UltraSparcFrameInfo(const TargetMachine& tgt) : MachineFrameInfo(tgt) {}
1221 int getStackFrameSizeAlignment () const { return StackFrameSizeAlignment;}
1222 int getMinStackFrameSize () const { return MinStackFrameSize; }
1223 int getNumFixedOutgoingArgs () const { return NumFixedOutgoingArgs; }
1224 int getSizeOfEachArgOnStack () const { return SizeOfEachArgOnStack; }
1225 bool argsOnStackHaveFixedSize () const { return true; }
1228 // These methods compute offsets using the frame contents for a
1229 // particular method. The frame contents are obtained from the
1230 // MachineCodeInfoForMethod object for the given method.
1232 int getFirstIncomingArgOffset (MachineCodeForMethod& mcInfo,
1235 pos = true; // arguments area grows upwards
1236 return FirstIncomingArgOffsetFromFP;
1238 int getFirstOutgoingArgOffset (MachineCodeForMethod& mcInfo,
1241 pos = true; // arguments area grows upwards
1242 return FirstOutgoingArgOffsetFromSP;
1244 int getFirstOptionalOutgoingArgOffset(MachineCodeForMethod& mcInfo,
1247 pos = true; // arguments area grows upwards
1248 return FirstOptionalOutgoingArgOffsetFromSP;
1251 int getFirstAutomaticVarOffset (MachineCodeForMethod& mcInfo,
1253 int getRegSpillAreaOffset (MachineCodeForMethod& mcInfo,
1255 int getTmpAreaOffset (MachineCodeForMethod& mcInfo,
1257 int getDynamicAreaOffset (MachineCodeForMethod& mcInfo,
1261 // These methods specify the base register used for each stack area
1262 // (generally FP or SP)
1264 virtual int getIncomingArgBaseRegNum() const {
1265 return (int) target.getRegInfo().getFramePointer();
1267 virtual int getOutgoingArgBaseRegNum() const {
1268 return (int) target.getRegInfo().getStackPointer();
1270 virtual int getOptionalOutgoingArgBaseRegNum() const {
1271 return (int) target.getRegInfo().getStackPointer();
1273 virtual int getAutomaticVarBaseRegNum() const {
1274 return (int) target.getRegInfo().getFramePointer();
1276 virtual int getRegSpillAreaBaseRegNum() const {
1277 return (int) target.getRegInfo().getFramePointer();
1279 virtual int getDynamicAreaBaseRegNum() const {
1280 return (int) target.getRegInfo().getStackPointer();
1284 // All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
1285 static const int OFFSET = (int) 0x7ff;
1286 static const int StackFrameSizeAlignment = 16;
1287 static const int MinStackFrameSize = 176;
1288 static const int NumFixedOutgoingArgs = 6;
1289 static const int SizeOfEachArgOnStack = 8;
1290 static const int StaticAreaOffsetFromFP = 0 + OFFSET;
1291 static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
1292 static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
1293 static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
1294 static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
1298 //---------------------------------------------------------------------------
1299 // class UltraSparcCacheInfo
1302 // Interface to cache parameters for the UltraSPARC.
1303 // Just use defaults for now.
1304 //---------------------------------------------------------------------------
1306 class UltraSparcCacheInfo: public MachineCacheInfo {
1308 /*ctor*/ UltraSparcCacheInfo (const TargetMachine& target) :
1309 MachineCacheInfo(target) {}
1313 //---------------------------------------------------------------------------
1314 // class UltraSparcMachine
1317 // Primary interface to machine description for the UltraSPARC.
1318 // Primarily just initializes machine-dependent parameters in
1319 // class TargetMachine, and creates machine-dependent subclasses
1320 // for classes such as InstrInfo, SchedInfo and RegInfo.
1321 //---------------------------------------------------------------------------
1323 class UltraSparc : public TargetMachine {
1325 UltraSparcInstrInfo instrInfo;
1326 UltraSparcSchedInfo schedInfo;
1327 UltraSparcRegInfo regInfo;
1328 UltraSparcFrameInfo frameInfo;
1329 UltraSparcCacheInfo cacheInfo;
1332 virtual ~UltraSparc() {}
1334 virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
1335 virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
1336 virtual const MachineRegInfo &getRegInfo() const { return regInfo; }
1337 virtual const MachineFrameInfo &getFrameInfo() const { return frameInfo; }
1338 virtual const MachineCacheInfo &getCacheInfo() const { return cacheInfo; }
1340 // compileMethod - For the sparc, we do instruction selection, followed by
1341 // delay slot scheduling, then register allocation.
1343 virtual bool compileMethod(Method *M);
1346 // emitAssembly - Output assembly language code (a .s file) for the specified
1347 // module. The specified module must have been compiled before this may be
1350 virtual void emitAssembly(const Module *M, ostream &OutStr) const;