1 //===-- SparcInternals.h ----------------------------------------*- C++ -*-===//
3 // This file defines stuff that is to be private to the Sparc backend, but is
4 // shared among different portions of the backend.
6 //===----------------------------------------------------------------------===//
8 #ifndef SPARC_INTERNALS_H
9 #define SPARC_INTERNALS_H
11 #include "llvm/CodeGen/MachineInstrBuilder.h"
12 #include "llvm/Target/TargetMachine.h"
13 #include "llvm/Target/TargetSchedInfo.h"
14 #include "llvm/Target/TargetFrameInfo.h"
15 #include "llvm/Target/TargetCacheInfo.h"
16 #include "llvm/Target/TargetRegInfo.h"
17 #include "llvm/Type.h"
18 #include "SparcRegClassInfo.h"
19 #include "Config/sys/types.h"
25 enum SparcInstrSchedClass {
26 SPARC_NONE, /* Instructions with no scheduling restrictions */
27 SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
28 SPARC_IEU0, /* Integer class IEU0 */
29 SPARC_IEU1, /* Integer class IEU1 */
30 SPARC_FPM, /* FP Multiply or Divide instructions */
31 SPARC_FPA, /* All other FP instructions */
32 SPARC_CTI, /* Control-transfer instructions */
33 SPARC_LD, /* Load instructions */
34 SPARC_ST, /* Store instructions */
35 SPARC_SINGLE, /* Instructions that must issue by themselves */
37 SPARC_INV, /* This should stay at the end for the next value */
38 SPARC_NUM_SCHED_CLASSES = SPARC_INV
42 //---------------------------------------------------------------------------
43 // enum SparcMachineOpCode.
44 // const TargetInstrDescriptor SparcMachineInstrDesc[]
47 // Description of UltraSparc machine instructions.
49 //---------------------------------------------------------------------------
52 enum SparcMachineOpCode {
53 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
54 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
56 #include "SparcInstr.def"
58 // End-of-array marker
60 NUM_REAL_OPCODES = PHI, // number of valid opcodes
61 NUM_TOTAL_OPCODES = INVALID_OPCODE
66 // Array of machine instruction descriptions...
67 extern const TargetInstrDescriptor SparcMachineInstrDesc[];
70 //---------------------------------------------------------------------------
71 // class UltraSparcInstrInfo
74 // Information about individual instructions.
75 // Most information is stored in the SparcMachineInstrDesc array above.
76 // Other information is computed on demand, and most such functions
77 // default to member functions in base class TargetInstrInfo.
78 //---------------------------------------------------------------------------
80 struct UltraSparcInstrInfo : public TargetInstrInfo {
81 UltraSparcInstrInfo();
84 // All immediate constants are in position 1 except the
85 // store instructions and SETxx.
87 virtual int getImmedConstantPos(MachineOpCode opCode) const {
89 if (this->maxImmedConstant(opCode, ignore) != 0) {
91 assert(! this->isStore((MachineOpCode) V9::STBr - 1));
93 assert(! this->isStore((MachineOpCode) V9::STXFSRi + 1));
95 if (opCode == V9::SETSW || opCode == V9::SETUW ||
96 opCode == V9::SETX || opCode == V9::SETHI)
98 if (opCode >= V9::STBr && opCode <= V9::STXFSRi)
106 /// createNOPinstr - returns the target's implementation of NOP, which is
107 /// usually a pseudo-instruction, implemented by a degenerate version of
108 /// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi 0, g0
110 MachineInstr* createNOPinstr() const {
111 return BuildMI(V9::SETHI, 2).addZImm(0).addReg(SparcIntRegClass::g0);
114 /// isNOPinstr - not having a special NOP opcode, we need to know if a given
115 /// instruction is interpreted as an `official' NOP instr, i.e., there may be
116 /// more than one way to `do nothing' but only one canonical way to slack off.
118 bool isNOPinstr(const MachineInstr &MI) const {
119 // Make sure the instruction is EXACTLY `sethi g0, 0'
120 if (MI.getOpcode() == V9::SETHI && MI.getNumOperands() == 2) {
121 const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
122 if (op0.isImmediate() && op0.getImmedValue() == 0 &&
123 op1.isMachineRegister() &&
124 op1.getMachineRegNum() == SparcIntRegClass::g0)
132 virtual bool hasResultInterlock(MachineOpCode opCode) const
134 // All UltraSPARC instructions have interlocks (note that delay slots
135 // are not considered here).
136 // However, instructions that use the result of an FCMP produce a
137 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
138 // Force the compiler to insert a software interlock (i.e., gap of
139 // 2 other groups, including NOPs if necessary).
140 return (opCode == V9::FCMPS || opCode == V9::FCMPD || opCode == V9::FCMPQ);
143 //-------------------------------------------------------------------------
144 // Queries about representation of LLVM quantities (e.g., constants)
145 //-------------------------------------------------------------------------
147 virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
148 const Instruction* I) const;
150 //-------------------------------------------------------------------------
151 // Code generation support for creating individual machine instructions
152 //-------------------------------------------------------------------------
154 // Get certain common op codes for the current target. This and all the
155 // Create* methods below should be moved to a machine code generation class
157 virtual MachineOpCode getNOPOpCode() const { return V9::NOP; }
159 // Get the value of an integral constant in the form that must
160 // be put into the machine register. The specified constant is interpreted
161 // as (i.e., converted if necessary to) the specified destination type. The
162 // result is always returned as an uint64_t, since the representation of
163 // int64_t and uint64_t are identical. The argument can be any known const.
165 // isValidConstant is set to true if a valid constant was found.
167 virtual uint64_t ConvertConstantToIntType(const TargetMachine &target,
169 const Type *destType,
170 bool &isValidConstant) const;
172 // Create an instruction sequence to put the constant `val' into
173 // the virtual register `dest'. `val' may be a Constant or a
174 // GlobalValue, viz., the constant address of a global variable or function.
175 // The generated instructions are returned in `mvec'.
176 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
177 // Any stack space required is allocated via mcff.
179 virtual void CreateCodeToLoadConst(const TargetMachine& target,
183 std::vector<MachineInstr*>& mvec,
184 MachineCodeForInstruction& mcfi) const;
186 // Create an instruction sequence to copy an integer value `val'
187 // to a floating point value `dest' by copying to memory and back.
188 // val must be an integral type. dest must be a Float or Double.
189 // The generated instructions are returned in `mvec'.
190 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
191 // Any stack space required is allocated via mcff.
193 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
197 std::vector<MachineInstr*>& mvec,
198 MachineCodeForInstruction& mcfi) const;
200 // Similarly, create an instruction sequence to copy an FP value
201 // `val' to an integer value `dest' by copying to memory and back.
202 // The generated instructions are returned in `mvec'.
203 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
204 // Any stack space required is allocated via mcff.
206 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
210 std::vector<MachineInstr*>& mvec,
211 MachineCodeForInstruction& mcfi) const;
213 // Create instruction(s) to copy src to dest, for arbitrary types
214 // The generated instructions are returned in `mvec'.
215 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
216 // Any stack space required is allocated via mcff.
218 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
222 std::vector<MachineInstr*>& mvec,
223 MachineCodeForInstruction& mcfi) const;
225 // Create instruction sequence to produce a sign-extended register value
226 // from an arbitrary sized value (sized in bits, not bytes).
227 // The generated instructions are appended to `mvec'.
228 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
229 // Any stack space required is allocated via mcff.
231 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
235 unsigned int numLowBits,
236 std::vector<MachineInstr*>& mvec,
237 MachineCodeForInstruction& mcfi) const;
239 // Create instruction sequence to produce a zero-extended register value
240 // from an arbitrary sized value (sized in bits, not bytes).
241 // The generated instructions are appended to `mvec'.
242 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
243 // Any stack space required is allocated via mcff.
245 virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
249 unsigned int numLowBits,
250 std::vector<MachineInstr*>& mvec,
251 MachineCodeForInstruction& mcfi) const;
255 //----------------------------------------------------------------------------
256 // class UltraSparcRegInfo
258 // This class implements the virtual class TargetRegInfo for Sparc.
260 //----------------------------------------------------------------------------
262 class UltraSparcRegInfo : public TargetRegInfo {
266 // Number of registers used for passing int args (usually 6: %o0 - %o5)
268 unsigned const NumOfIntArgRegs;
270 // Number of registers used for passing float args (usually 32: %f0 - %f31)
272 unsigned const NumOfFloatArgRegs;
274 // ======================== Private Methods =============================
276 // The following methods are used to color special live ranges (e.g.
277 // function args and return values etc.) with specific hardware registers
278 // as required. See SparcRegInfo.cpp for the implementation.
280 void suggestReg4RetAddr(MachineInstr *RetMI,
281 LiveRangeInfo &LRI) const;
283 void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI) const;
285 // Helper used by the all the getRegType() functions.
286 int getRegTypeForClassAndType(unsigned regClassID, const Type* type) const;
289 // Type of registers available in Sparc. There can be several reg types
290 // in the same class. For instace, the float reg class has Single/Double
302 // The actual register classes in the Sparc
304 // **** WARNING: If this enum order is changed, also modify
305 // getRegisterClassOfValue method below since it assumes this particular
306 // order for efficiency.
309 IntRegClassID, // Integer
310 FloatRegClassID, // Float (both single/double)
311 IntCCRegClassID, // Int Condition Code
312 FloatCCRegClassID, // Float Condition code
313 SpecialRegClassID // Special (unallocated) registers
316 UltraSparcRegInfo(const UltraSparc &tgt);
318 // To find the register class used for a specified Type
320 unsigned getRegClassIDOfType(const Type *type,
321 bool isCCReg = false) const;
323 // To find the register class to which a specified register belongs
325 unsigned getRegClassIDOfRegType(int regType) const;
327 // getZeroRegNum - returns the register that contains always zero this is the
328 // unified register number
330 virtual int getZeroRegNum() const;
332 // getCallAddressReg - returns the reg used for pushing the address when a
333 // function is called. This can be used for other purposes between calls
335 unsigned getCallAddressReg() const;
337 // Returns the register containing the return address.
338 // It should be made sure that this register contains the return
339 // value when a return instruction is reached.
341 unsigned getReturnAddressReg() const;
343 // Number of registers used for passing int args (usually 6: %o0 - %o5)
344 // and float args (usually 32: %f0 - %f31)
346 unsigned const getNumOfIntArgRegs() const { return NumOfIntArgRegs; }
347 unsigned const getNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
349 // Compute which register can be used for an argument, if any
351 int regNumForIntArg(bool inCallee, bool isVarArgsCall,
352 unsigned argNo, unsigned& regClassId) const;
354 int regNumForFPArg(unsigned RegType, bool inCallee, bool isVarArgsCall,
355 unsigned argNo, unsigned& regClassId) const;
357 // The following methods are used to color special live ranges (e.g.
358 // function args and return values etc.) with specific hardware registers
359 // as required. See SparcRegInfo.cpp for the implementation for Sparc.
361 void suggestRegs4MethodArgs(const Function *Meth,
362 LiveRangeInfo& LRI) const;
364 void suggestRegs4CallArgs(MachineInstr *CallMI,
365 LiveRangeInfo& LRI) const;
367 void suggestReg4RetValue(MachineInstr *RetMI,
368 LiveRangeInfo& LRI) const;
370 void colorMethodArgs(const Function *Meth, LiveRangeInfo& LRI,
371 std::vector<MachineInstr*>& InstrnsBefore,
372 std::vector<MachineInstr*>& InstrnsAfter) const;
374 // method used for printing a register for debugging purposes
376 void printReg(const LiveRange *LR) const;
378 // returns the # of bytes of stack space allocated for each register
379 // type. For Sparc, currently we allocate 8 bytes on stack for all
380 // register types. We can optimize this later if necessary to save stack
381 // space (However, should make sure that stack alignment is correct)
383 inline int getSpilledRegSize(int RegType) const {
388 // To obtain the return value and the indirect call address (if any)
389 // contained in a CALL machine instruction
391 const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
392 const Value * getCallInstIndirectAddrVal(const MachineInstr *CallMI) const;
394 // The following methods are used to generate "copy" machine instructions
395 // for an architecture.
397 // The function regTypeNeedsScratchReg() can be used to check whether a
398 // scratch register is needed to copy a register of type `regType' to
399 // or from memory. If so, such a scratch register can be provided by
400 // the caller (e.g., if it knows which regsiters are free); otherwise
401 // an arbitrary one will be chosen and spilled by the copy instructions.
403 bool regTypeNeedsScratchReg(int RegType,
404 int& scratchRegClassId) const;
406 void cpReg2RegMI(std::vector<MachineInstr*>& mvec,
407 unsigned SrcReg, unsigned DestReg,
410 void cpReg2MemMI(std::vector<MachineInstr*>& mvec,
411 unsigned SrcReg, unsigned DestPtrReg,
412 int Offset, int RegType, int scratchReg = -1) const;
414 void cpMem2RegMI(std::vector<MachineInstr*>& mvec,
415 unsigned SrcPtrReg, int Offset, unsigned DestReg,
416 int RegType, int scratchReg = -1) const;
418 void cpValue2Value(Value *Src, Value *Dest,
419 std::vector<MachineInstr*>& mvec) const;
421 // Get the register type for a register identified different ways.
422 // Note that getRegTypeForLR(LR) != getRegTypeForDataType(LR->getType())!
423 // The reg class of a LR depends both on the Value types in it and whether
424 // they are CC registers or not (for example).
425 int getRegTypeForDataType(const Type* type) const;
426 int getRegTypeForLR(const LiveRange *LR) const;
427 int getRegType(int unifiedRegNum) const;
429 virtual unsigned getFramePointer() const;
430 virtual unsigned getStackPointer() const;
436 //---------------------------------------------------------------------------
437 // class UltraSparcSchedInfo
440 // Interface to instruction scheduling information for UltraSPARC.
441 // The parameter values above are based on UltraSPARC IIi.
442 //---------------------------------------------------------------------------
445 class UltraSparcSchedInfo: public TargetSchedInfo {
447 UltraSparcSchedInfo(const TargetMachine &tgt);
449 virtual void initializeResources();
453 //---------------------------------------------------------------------------
454 // class UltraSparcFrameInfo
457 // Interface to stack frame layout info for the UltraSPARC.
458 // Starting offsets for each area of the stack frame are aligned at
459 // a multiple of getStackFrameSizeAlignment().
460 //---------------------------------------------------------------------------
462 class UltraSparcFrameInfo: public TargetFrameInfo {
463 const TargetMachine ⌖
465 UltraSparcFrameInfo(const TargetMachine &TM)
466 : TargetFrameInfo(StackGrowsDown, StackFrameSizeAlignment, 0), target(TM) {}
469 // These methods provide constant parameters of the frame layout.
471 int getStackFrameSizeAlignment() const { return StackFrameSizeAlignment;}
472 int getMinStackFrameSize() const { return MinStackFrameSize; }
473 int getNumFixedOutgoingArgs() const { return NumFixedOutgoingArgs; }
474 int getSizeOfEachArgOnStack() const { return SizeOfEachArgOnStack; }
475 bool argsOnStackHaveFixedSize() const { return true; }
477 // This method adjusts a stack offset to meet alignment rules of target.
478 // The fixed OFFSET (0x7ff) must be subtracted and the result aligned.
479 virtual int adjustAlignment (int unalignedOffset,
481 unsigned int align) const {
482 return unalignedOffset + (growUp? +1:-1)*((unalignedOffset-OFFSET) % align);
485 // These methods compute offsets using the frame contents for a
486 // particular function. The frame contents are obtained from the
487 // MachineCodeInfoForMethod object for the given function.
489 int getFirstIncomingArgOffset (MachineFunction& mcInfo,
492 growUp = true; // arguments area grows upwards
493 return FirstIncomingArgOffsetFromFP;
495 int getFirstOutgoingArgOffset (MachineFunction& mcInfo,
498 growUp = true; // arguments area grows upwards
499 return FirstOutgoingArgOffsetFromSP;
501 int getFirstOptionalOutgoingArgOffset(MachineFunction& mcInfo,
504 growUp = true; // arguments area grows upwards
505 return FirstOptionalOutgoingArgOffsetFromSP;
508 int getFirstAutomaticVarOffset (MachineFunction& mcInfo,
510 int getRegSpillAreaOffset (MachineFunction& mcInfo,
512 int getTmpAreaOffset (MachineFunction& mcInfo,
514 int getDynamicAreaOffset (MachineFunction& mcInfo,
518 // These methods specify the base register used for each stack area
519 // (generally FP or SP)
521 virtual int getIncomingArgBaseRegNum() const {
522 return (int) target.getRegInfo().getFramePointer();
524 virtual int getOutgoingArgBaseRegNum() const {
525 return (int) target.getRegInfo().getStackPointer();
527 virtual int getOptionalOutgoingArgBaseRegNum() const {
528 return (int) target.getRegInfo().getStackPointer();
530 virtual int getAutomaticVarBaseRegNum() const {
531 return (int) target.getRegInfo().getFramePointer();
533 virtual int getRegSpillAreaBaseRegNum() const {
534 return (int) target.getRegInfo().getFramePointer();
536 virtual int getDynamicAreaBaseRegNum() const {
537 return (int) target.getRegInfo().getStackPointer();
540 virtual int getIncomingArgOffset(MachineFunction& mcInfo,
541 unsigned argNum) const {
542 assert(argsOnStackHaveFixedSize());
544 unsigned relativeOffset = argNum * getSizeOfEachArgOnStack();
545 bool growUp; // do args grow up or down
546 int firstArg = getFirstIncomingArgOffset(mcInfo, growUp);
547 return growUp ? firstArg + relativeOffset : firstArg - relativeOffset;
550 virtual int getOutgoingArgOffset(MachineFunction& mcInfo,
551 unsigned argNum) const {
552 assert(argsOnStackHaveFixedSize());
553 //assert(((int) argNum - this->getNumFixedOutgoingArgs())
554 // <= (int) mcInfo.getInfo()->getMaxOptionalNumArgs());
556 unsigned relativeOffset = argNum * getSizeOfEachArgOnStack();
557 bool growUp; // do args grow up or down
558 int firstArg = getFirstOutgoingArgOffset(mcInfo, growUp);
559 return growUp ? firstArg + relativeOffset : firstArg - relativeOffset;
563 /*----------------------------------------------------------------------
564 This diagram shows the stack frame layout used by llc on Sparc V9.
565 Note that only the location of automatic variables, spill area,
566 temporary storage, and dynamically allocated stack area are chosen
567 by us. The rest conform to the Sparc V9 ABI.
568 All stack addresses are offset by OFFSET = 0x7ff (2047).
570 Alignment assumptions and other invariants:
571 (1) %sp+OFFSET and %fp+OFFSET are always aligned on 16-byte boundary
572 (2) Variables in automatic, spill, temporary, or dynamic regions
573 are aligned according to their size as in all memory accesses.
574 (3) Everything below the dynamically allocated stack area is only used
575 during a call to another function, so it is never needed when
576 the current function is active. This is why space can be allocated
577 dynamically by incrementing %sp any time within the function.
582 %fp+OFFSET+176 Optional extra incoming arguments# 1..N
583 %fp+OFFSET+168 Incoming argument #6
585 %fp+OFFSET+128 Incoming argument #1
587 ---%fp+OFFSET-0--------Bottom of caller's stack frame--------------------
588 %fp+OFFSET-8 Automatic variables <-- ****TOP OF STACK FRAME****
593 %sp+OFFSET+176+8N Bottom of dynamically allocated stack area
594 %sp+OFFSET+168+8N Optional extra outgoing argument# N
596 %sp+OFFSET+176 Optional extra outgoing argument# 1
597 %sp+OFFSET+168 Outgoing argument #6
599 %sp+OFFSET+128 Outgoing argument #1
600 %sp+OFFSET+120 Save area for %i7
602 %sp+OFFSET+0 Save area for %l0 <-- ****BOTTOM OF STACK FRAME****
604 *----------------------------------------------------------------------*/
606 // All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
607 static const int OFFSET = (int) 0x7ff;
608 static const int StackFrameSizeAlignment = 16;
609 static const int MinStackFrameSize = 176;
610 static const int NumFixedOutgoingArgs = 6;
611 static const int SizeOfEachArgOnStack = 8;
612 static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
613 static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
614 static const int StaticAreaOffsetFromFP = 0 + OFFSET;
615 static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
616 static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
620 //---------------------------------------------------------------------------
621 // class UltraSparcCacheInfo
624 // Interface to cache parameters for the UltraSPARC.
625 // Just use defaults for now.
626 //---------------------------------------------------------------------------
628 struct UltraSparcCacheInfo: public TargetCacheInfo {
629 UltraSparcCacheInfo(const TargetMachine &T) : TargetCacheInfo(T) {}
633 /// createAddRegNumToValuesPass - this pass adds unsigned register numbers to
634 /// instructions, since that's not done by the Sparc InstSelector, but that's
635 /// how the target-independent register allocator in the JIT likes to see
636 /// instructions. This pass enables the usage of the JIT register allocator(s).
637 Pass *createAddRegNumToValuesPass();
639 /// createStackSlotsPass - External interface to stack-slots pass that enters 2
640 /// empty slots at the top of each function stack
641 Pass *createStackSlotsPass(const TargetMachine &TM);
643 // Interface to pre-selection pass that specializes LLVM code for a target
645 Pass *createPreSelectionPass(TargetMachine &Target);
647 // External interface to peephole optimization pass operating on machine code.
648 FunctionPass *createPeepholeOptsPass(TargetMachine &Target);
651 //---------------------------------------------------------------------------
655 // Primary interface to machine description for the UltraSPARC.
656 // Primarily just initializes machine-dependent parameters in
657 // class TargetMachine, and creates machine-dependent subclasses
658 // for classes such as InstrInfo, SchedInfo and RegInfo.
659 //---------------------------------------------------------------------------
661 class UltraSparc : public TargetMachine {
662 UltraSparcInstrInfo instrInfo;
663 UltraSparcSchedInfo schedInfo;
664 UltraSparcRegInfo regInfo;
665 UltraSparcFrameInfo frameInfo;
666 UltraSparcCacheInfo cacheInfo;
670 virtual const TargetInstrInfo &getInstrInfo() const { return instrInfo; }
671 virtual const TargetSchedInfo &getSchedInfo() const { return schedInfo; }
672 virtual const TargetRegInfo &getRegInfo() const { return regInfo; }
673 virtual const TargetFrameInfo &getFrameInfo() const { return frameInfo; }
674 virtual const TargetCacheInfo &getCacheInfo() const { return cacheInfo; }
676 virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
677 virtual bool addPassesToJITCompile(FunctionPassManager &PM);
678 virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
679 MachineCodeEmitter &MCE);
681 // getPrologEpilogInsertionPass - Inserts prolog/epilog code.
682 FunctionPass* getPrologEpilogInsertionPass();
684 // getFunctionAsmPrinterPass - Writes out machine code for a single function
685 Pass* getFunctionAsmPrinterPass(std::ostream &Out);
687 // getModuleAsmPrinterPass - Writes generated machine code to assembly file.
688 Pass* getModuleAsmPrinterPass(std::ostream &Out);
690 // getBytecodeAsmPrinterPass - Emits final LLVM bytecode to assembly file.
691 Pass* getBytecodeAsmPrinterPass(std::ostream &Out);