1 //===-- SparcInternals.h ----------------------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines stuff that is to be private to the Sparc backend, but is
11 // shared among different portions of the backend.
13 //===----------------------------------------------------------------------===//
15 #ifndef SPARC_INTERNALS_H
16 #define SPARC_INTERNALS_H
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetSchedInfo.h"
21 #include "llvm/Target/TargetFrameInfo.h"
22 #include "llvm/Target/TargetCacheInfo.h"
23 #include "llvm/Target/TargetRegInfo.h"
24 #include "llvm/Type.h"
25 #include "SparcRegClassInfo.h"
26 #include "Config/sys/types.h"
32 enum SparcInstrSchedClass {
33 SPARC_NONE, /* Instructions with no scheduling restrictions */
34 SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
35 SPARC_IEU0, /* Integer class IEU0 */
36 SPARC_IEU1, /* Integer class IEU1 */
37 SPARC_FPM, /* FP Multiply or Divide instructions */
38 SPARC_FPA, /* All other FP instructions */
39 SPARC_CTI, /* Control-transfer instructions */
40 SPARC_LD, /* Load instructions */
41 SPARC_ST, /* Store instructions */
42 SPARC_SINGLE, /* Instructions that must issue by themselves */
44 SPARC_INV, /* This should stay at the end for the next value */
45 SPARC_NUM_SCHED_CLASSES = SPARC_INV
49 //---------------------------------------------------------------------------
50 // enum SparcMachineOpCode.
51 // const TargetInstrDescriptor SparcMachineInstrDesc[]
54 // Description of UltraSparc machine instructions.
56 //---------------------------------------------------------------------------
59 enum SparcMachineOpCode {
60 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
61 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
63 #include "SparcInstr.def"
65 // End-of-array marker
67 NUM_REAL_OPCODES = PHI, // number of valid opcodes
68 NUM_TOTAL_OPCODES = INVALID_OPCODE
73 // Array of machine instruction descriptions...
74 extern const TargetInstrDescriptor SparcMachineInstrDesc[];
77 //---------------------------------------------------------------------------
78 // class UltraSparcInstrInfo
81 // Information about individual instructions.
82 // Most information is stored in the SparcMachineInstrDesc array above.
83 // Other information is computed on demand, and most such functions
84 // default to member functions in base class TargetInstrInfo.
85 //---------------------------------------------------------------------------
87 struct UltraSparcInstrInfo : public TargetInstrInfo {
88 UltraSparcInstrInfo();
91 // All immediate constants are in position 1 except the
92 // store instructions and SETxx.
94 virtual int getImmedConstantPos(MachineOpCode opCode) const {
96 if (this->maxImmedConstant(opCode, ignore) != 0) {
98 assert(! this->isStore((MachineOpCode) V9::STBr - 1));
100 assert(! this->isStore((MachineOpCode) V9::STXFSRi + 1));
102 if (opCode == V9::SETSW || opCode == V9::SETUW ||
103 opCode == V9::SETX || opCode == V9::SETHI)
105 if (opCode >= V9::STBr && opCode <= V9::STXFSRi)
113 /// createNOPinstr - returns the target's implementation of NOP, which is
114 /// usually a pseudo-instruction, implemented by a degenerate version of
115 /// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi 0, g0
117 MachineInstr* createNOPinstr() const {
118 return BuildMI(V9::SETHI, 2).addZImm(0).addReg(SparcIntRegClass::g0);
121 /// isNOPinstr - not having a special NOP opcode, we need to know if a given
122 /// instruction is interpreted as an `official' NOP instr, i.e., there may be
123 /// more than one way to `do nothing' but only one canonical way to slack off.
125 bool isNOPinstr(const MachineInstr &MI) const {
126 // Make sure the instruction is EXACTLY `sethi g0, 0'
127 if (MI.getOpcode() == V9::SETHI && MI.getNumOperands() == 2) {
128 const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
129 if (op0.isImmediate() && op0.getImmedValue() == 0 &&
130 op1.isMachineRegister() &&
131 op1.getMachineRegNum() == SparcIntRegClass::g0)
139 virtual bool hasResultInterlock(MachineOpCode opCode) const
141 // All UltraSPARC instructions have interlocks (note that delay slots
142 // are not considered here).
143 // However, instructions that use the result of an FCMP produce a
144 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
145 // Force the compiler to insert a software interlock (i.e., gap of
146 // 2 other groups, including NOPs if necessary).
147 return (opCode == V9::FCMPS || opCode == V9::FCMPD || opCode == V9::FCMPQ);
150 //-------------------------------------------------------------------------
151 // Queries about representation of LLVM quantities (e.g., constants)
152 //-------------------------------------------------------------------------
154 virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
155 const Instruction* I) const;
157 //-------------------------------------------------------------------------
158 // Code generation support for creating individual machine instructions
159 //-------------------------------------------------------------------------
161 // Get certain common op codes for the current target. This and all the
162 // Create* methods below should be moved to a machine code generation class
164 virtual MachineOpCode getNOPOpCode() const { return V9::NOP; }
166 // Get the value of an integral constant in the form that must
167 // be put into the machine register. The specified constant is interpreted
168 // as (i.e., converted if necessary to) the specified destination type. The
169 // result is always returned as an uint64_t, since the representation of
170 // int64_t and uint64_t are identical. The argument can be any known const.
172 // isValidConstant is set to true if a valid constant was found.
174 virtual uint64_t ConvertConstantToIntType(const TargetMachine &target,
176 const Type *destType,
177 bool &isValidConstant) const;
179 // Create an instruction sequence to put the constant `val' into
180 // the virtual register `dest'. `val' may be a Constant or a
181 // GlobalValue, viz., the constant address of a global variable or function.
182 // The generated instructions are returned in `mvec'.
183 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
184 // Any stack space required is allocated via mcff.
186 virtual void CreateCodeToLoadConst(const TargetMachine& target,
190 std::vector<MachineInstr*>& mvec,
191 MachineCodeForInstruction& mcfi) const;
193 // Create an instruction sequence to copy an integer value `val'
194 // to a floating point value `dest' by copying to memory and back.
195 // val must be an integral type. dest must be a Float or Double.
196 // The generated instructions are returned in `mvec'.
197 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
198 // Any stack space required is allocated via mcff.
200 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
204 std::vector<MachineInstr*>& mvec,
205 MachineCodeForInstruction& mcfi) const;
207 // Similarly, create an instruction sequence to copy an FP value
208 // `val' to an integer value `dest' by copying to memory and back.
209 // The generated instructions are returned in `mvec'.
210 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
211 // Any stack space required is allocated via mcff.
213 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
217 std::vector<MachineInstr*>& mvec,
218 MachineCodeForInstruction& mcfi) const;
220 // Create instruction(s) to copy src to dest, for arbitrary types
221 // The generated instructions are returned in `mvec'.
222 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
223 // Any stack space required is allocated via mcff.
225 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
229 std::vector<MachineInstr*>& mvec,
230 MachineCodeForInstruction& mcfi) const;
232 // Create instruction sequence to produce a sign-extended register value
233 // from an arbitrary sized value (sized in bits, not bytes).
234 // The generated instructions are appended to `mvec'.
235 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
236 // Any stack space required is allocated via mcff.
238 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
242 unsigned int numLowBits,
243 std::vector<MachineInstr*>& mvec,
244 MachineCodeForInstruction& mcfi) const;
246 // Create instruction sequence to produce a zero-extended register value
247 // from an arbitrary sized value (sized in bits, not bytes).
248 // The generated instructions are appended to `mvec'.
249 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
250 // Any stack space required is allocated via mcff.
252 virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
256 unsigned int numLowBits,
257 std::vector<MachineInstr*>& mvec,
258 MachineCodeForInstruction& mcfi) const;
262 //----------------------------------------------------------------------------
263 // class UltraSparcRegInfo
265 // This class implements the virtual class TargetRegInfo for Sparc.
267 //----------------------------------------------------------------------------
269 class UltraSparcRegInfo : public TargetRegInfo {
273 // Number of registers used for passing int args (usually 6: %o0 - %o5)
275 unsigned const NumOfIntArgRegs;
277 // Number of registers used for passing float args (usually 32: %f0 - %f31)
279 unsigned const NumOfFloatArgRegs;
281 // ======================== Private Methods =============================
283 // The following methods are used to color special live ranges (e.g.
284 // function args and return values etc.) with specific hardware registers
285 // as required. See SparcRegInfo.cpp for the implementation.
287 void suggestReg4RetAddr(MachineInstr *RetMI,
288 LiveRangeInfo &LRI) const;
290 void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI) const;
292 // Helper used by the all the getRegType() functions.
293 int getRegTypeForClassAndType(unsigned regClassID, const Type* type) const;
296 // Type of registers available in Sparc. There can be several reg types
297 // in the same class. For instace, the float reg class has Single/Double
309 // The actual register classes in the Sparc
311 // **** WARNING: If this enum order is changed, also modify
312 // getRegisterClassOfValue method below since it assumes this particular
313 // order for efficiency.
316 IntRegClassID, // Integer
317 FloatRegClassID, // Float (both single/double)
318 IntCCRegClassID, // Int Condition Code
319 FloatCCRegClassID, // Float Condition code
320 SpecialRegClassID // Special (unallocated) registers
323 UltraSparcRegInfo(const UltraSparc &tgt);
325 // To find the register class used for a specified Type
327 unsigned getRegClassIDOfType(const Type *type,
328 bool isCCReg = false) const;
330 // To find the register class to which a specified register belongs
332 unsigned getRegClassIDOfRegType(int regType) const;
334 // getZeroRegNum - returns the register that contains always zero this is the
335 // unified register number
337 virtual int getZeroRegNum() const;
339 // getCallAddressReg - returns the reg used for pushing the address when a
340 // function is called. This can be used for other purposes between calls
342 unsigned getCallAddressReg() const;
344 // Returns the register containing the return address.
345 // It should be made sure that this register contains the return
346 // value when a return instruction is reached.
348 unsigned getReturnAddressReg() const;
350 // Number of registers used for passing int args (usually 6: %o0 - %o5)
351 // and float args (usually 32: %f0 - %f31)
353 unsigned const getNumOfIntArgRegs() const { return NumOfIntArgRegs; }
354 unsigned const getNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
356 // Compute which register can be used for an argument, if any
358 int regNumForIntArg(bool inCallee, bool isVarArgsCall,
359 unsigned argNo, unsigned& regClassId) const;
361 int regNumForFPArg(unsigned RegType, bool inCallee, bool isVarArgsCall,
362 unsigned argNo, unsigned& regClassId) const;
364 // The following methods are used to color special live ranges (e.g.
365 // function args and return values etc.) with specific hardware registers
366 // as required. See SparcRegInfo.cpp for the implementation for Sparc.
368 void suggestRegs4MethodArgs(const Function *Meth,
369 LiveRangeInfo& LRI) const;
371 void suggestRegs4CallArgs(MachineInstr *CallMI,
372 LiveRangeInfo& LRI) const;
374 void suggestReg4RetValue(MachineInstr *RetMI,
375 LiveRangeInfo& LRI) const;
377 void colorMethodArgs(const Function *Meth, LiveRangeInfo& LRI,
378 std::vector<MachineInstr*>& InstrnsBefore,
379 std::vector<MachineInstr*>& InstrnsAfter) const;
381 // method used for printing a register for debugging purposes
383 void printReg(const LiveRange *LR) const;
385 // returns the # of bytes of stack space allocated for each register
386 // type. For Sparc, currently we allocate 8 bytes on stack for all
387 // register types. We can optimize this later if necessary to save stack
388 // space (However, should make sure that stack alignment is correct)
390 inline int getSpilledRegSize(int RegType) const {
395 // To obtain the return value and the indirect call address (if any)
396 // contained in a CALL machine instruction
398 const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
399 const Value * getCallInstIndirectAddrVal(const MachineInstr *CallMI) const;
401 // The following methods are used to generate "copy" machine instructions
402 // for an architecture.
404 // The function regTypeNeedsScratchReg() can be used to check whether a
405 // scratch register is needed to copy a register of type `regType' to
406 // or from memory. If so, such a scratch register can be provided by
407 // the caller (e.g., if it knows which regsiters are free); otherwise
408 // an arbitrary one will be chosen and spilled by the copy instructions.
410 bool regTypeNeedsScratchReg(int RegType,
411 int& scratchRegClassId) const;
413 void cpReg2RegMI(std::vector<MachineInstr*>& mvec,
414 unsigned SrcReg, unsigned DestReg,
417 void cpReg2MemMI(std::vector<MachineInstr*>& mvec,
418 unsigned SrcReg, unsigned DestPtrReg,
419 int Offset, int RegType, int scratchReg = -1) const;
421 void cpMem2RegMI(std::vector<MachineInstr*>& mvec,
422 unsigned SrcPtrReg, int Offset, unsigned DestReg,
423 int RegType, int scratchReg = -1) const;
425 void cpValue2Value(Value *Src, Value *Dest,
426 std::vector<MachineInstr*>& mvec) const;
428 // Get the register type for a register identified different ways.
429 // Note that getRegTypeForLR(LR) != getRegTypeForDataType(LR->getType())!
430 // The reg class of a LR depends both on the Value types in it and whether
431 // they are CC registers or not (for example).
432 int getRegTypeForDataType(const Type* type) const;
433 int getRegTypeForLR(const LiveRange *LR) const;
434 int getRegType(int unifiedRegNum) const;
436 virtual unsigned getFramePointer() const;
437 virtual unsigned getStackPointer() const;
443 //---------------------------------------------------------------------------
444 // class UltraSparcSchedInfo
447 // Interface to instruction scheduling information for UltraSPARC.
448 // The parameter values above are based on UltraSPARC IIi.
449 //---------------------------------------------------------------------------
452 class UltraSparcSchedInfo: public TargetSchedInfo {
454 UltraSparcSchedInfo(const TargetMachine &tgt);
456 virtual void initializeResources();
460 //---------------------------------------------------------------------------
461 // class UltraSparcFrameInfo
464 // Interface to stack frame layout info for the UltraSPARC.
465 // Starting offsets for each area of the stack frame are aligned at
466 // a multiple of getStackFrameSizeAlignment().
467 //---------------------------------------------------------------------------
469 class UltraSparcFrameInfo: public TargetFrameInfo {
470 const TargetMachine ⌖
472 UltraSparcFrameInfo(const TargetMachine &TM)
473 : TargetFrameInfo(StackGrowsDown, StackFrameSizeAlignment, 0), target(TM) {}
476 // These methods provide constant parameters of the frame layout.
478 int getStackFrameSizeAlignment() const { return StackFrameSizeAlignment;}
479 int getMinStackFrameSize() const { return MinStackFrameSize; }
480 int getNumFixedOutgoingArgs() const { return NumFixedOutgoingArgs; }
481 int getSizeOfEachArgOnStack() const { return SizeOfEachArgOnStack; }
482 bool argsOnStackHaveFixedSize() const { return true; }
484 // This method adjusts a stack offset to meet alignment rules of target.
485 // The fixed OFFSET (0x7ff) must be subtracted and the result aligned.
486 virtual int adjustAlignment (int unalignedOffset,
488 unsigned int align) const {
489 return unalignedOffset + (growUp? +1:-1)*((unalignedOffset-OFFSET) % align);
492 // These methods compute offsets using the frame contents for a
493 // particular function. The frame contents are obtained from the
494 // MachineCodeInfoForMethod object for the given function.
496 int getFirstIncomingArgOffset (MachineFunction& mcInfo,
499 growUp = true; // arguments area grows upwards
500 return FirstIncomingArgOffsetFromFP;
502 int getFirstOutgoingArgOffset (MachineFunction& mcInfo,
505 growUp = true; // arguments area grows upwards
506 return FirstOutgoingArgOffsetFromSP;
508 int getFirstOptionalOutgoingArgOffset(MachineFunction& mcInfo,
511 growUp = true; // arguments area grows upwards
512 return FirstOptionalOutgoingArgOffsetFromSP;
515 int getFirstAutomaticVarOffset (MachineFunction& mcInfo,
517 int getRegSpillAreaOffset (MachineFunction& mcInfo,
519 int getTmpAreaOffset (MachineFunction& mcInfo,
521 int getDynamicAreaOffset (MachineFunction& mcInfo,
525 // These methods specify the base register used for each stack area
526 // (generally FP or SP)
528 virtual int getIncomingArgBaseRegNum() const {
529 return (int) target.getRegInfo().getFramePointer();
531 virtual int getOutgoingArgBaseRegNum() const {
532 return (int) target.getRegInfo().getStackPointer();
534 virtual int getOptionalOutgoingArgBaseRegNum() const {
535 return (int) target.getRegInfo().getStackPointer();
537 virtual int getAutomaticVarBaseRegNum() const {
538 return (int) target.getRegInfo().getFramePointer();
540 virtual int getRegSpillAreaBaseRegNum() const {
541 return (int) target.getRegInfo().getFramePointer();
543 virtual int getDynamicAreaBaseRegNum() const {
544 return (int) target.getRegInfo().getStackPointer();
547 virtual int getIncomingArgOffset(MachineFunction& mcInfo,
548 unsigned argNum) const {
549 assert(argsOnStackHaveFixedSize());
551 unsigned relativeOffset = argNum * getSizeOfEachArgOnStack();
552 bool growUp; // do args grow up or down
553 int firstArg = getFirstIncomingArgOffset(mcInfo, growUp);
554 return growUp ? firstArg + relativeOffset : firstArg - relativeOffset;
557 virtual int getOutgoingArgOffset(MachineFunction& mcInfo,
558 unsigned argNum) const {
559 assert(argsOnStackHaveFixedSize());
560 //assert(((int) argNum - this->getNumFixedOutgoingArgs())
561 // <= (int) mcInfo.getInfo()->getMaxOptionalNumArgs());
563 unsigned relativeOffset = argNum * getSizeOfEachArgOnStack();
564 bool growUp; // do args grow up or down
565 int firstArg = getFirstOutgoingArgOffset(mcInfo, growUp);
566 return growUp ? firstArg + relativeOffset : firstArg - relativeOffset;
570 /*----------------------------------------------------------------------
571 This diagram shows the stack frame layout used by llc on Sparc V9.
572 Note that only the location of automatic variables, spill area,
573 temporary storage, and dynamically allocated stack area are chosen
574 by us. The rest conform to the Sparc V9 ABI.
575 All stack addresses are offset by OFFSET = 0x7ff (2047).
577 Alignment assumptions and other invariants:
578 (1) %sp+OFFSET and %fp+OFFSET are always aligned on 16-byte boundary
579 (2) Variables in automatic, spill, temporary, or dynamic regions
580 are aligned according to their size as in all memory accesses.
581 (3) Everything below the dynamically allocated stack area is only used
582 during a call to another function, so it is never needed when
583 the current function is active. This is why space can be allocated
584 dynamically by incrementing %sp any time within the function.
589 %fp+OFFSET+176 Optional extra incoming arguments# 1..N
590 %fp+OFFSET+168 Incoming argument #6
592 %fp+OFFSET+128 Incoming argument #1
594 ---%fp+OFFSET-0--------Bottom of caller's stack frame--------------------
595 %fp+OFFSET-8 Automatic variables <-- ****TOP OF STACK FRAME****
600 %sp+OFFSET+176+8N Bottom of dynamically allocated stack area
601 %sp+OFFSET+168+8N Optional extra outgoing argument# N
603 %sp+OFFSET+176 Optional extra outgoing argument# 1
604 %sp+OFFSET+168 Outgoing argument #6
606 %sp+OFFSET+128 Outgoing argument #1
607 %sp+OFFSET+120 Save area for %i7
609 %sp+OFFSET+0 Save area for %l0 <-- ****BOTTOM OF STACK FRAME****
611 *----------------------------------------------------------------------*/
613 // All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
614 static const int OFFSET = (int) 0x7ff;
615 static const int StackFrameSizeAlignment = 16;
616 static const int MinStackFrameSize = 176;
617 static const int NumFixedOutgoingArgs = 6;
618 static const int SizeOfEachArgOnStack = 8;
619 static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
620 static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
621 static const int StaticAreaOffsetFromFP = 0 + OFFSET;
622 static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
623 static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
627 //---------------------------------------------------------------------------
628 // class UltraSparcCacheInfo
631 // Interface to cache parameters for the UltraSPARC.
632 // Just use defaults for now.
633 //---------------------------------------------------------------------------
635 struct UltraSparcCacheInfo: public TargetCacheInfo {
636 UltraSparcCacheInfo(const TargetMachine &T) : TargetCacheInfo(T) {}
640 /// createStackSlotsPass - External interface to stack-slots pass that enters 2
641 /// empty slots at the top of each function stack
642 Pass *createStackSlotsPass(const TargetMachine &TM);
644 // Interface to pre-selection pass that specializes LLVM code for a target
646 FunctionPass *createPreSelectionPass(const TargetMachine &TM);
648 // External interface to peephole optimization pass operating on machine code.
649 FunctionPass *createPeepholeOptsPass(const TargetMachine &TM);
652 //---------------------------------------------------------------------------
656 // Primary interface to machine description for the UltraSPARC.
657 // Primarily just initializes machine-dependent parameters in
658 // class TargetMachine, and creates machine-dependent subclasses
659 // for classes such as InstrInfo, SchedInfo and RegInfo.
660 //---------------------------------------------------------------------------
662 class UltraSparc : public TargetMachine {
663 UltraSparcInstrInfo instrInfo;
664 UltraSparcSchedInfo schedInfo;
665 UltraSparcRegInfo regInfo;
666 UltraSparcFrameInfo frameInfo;
667 UltraSparcCacheInfo cacheInfo;
671 virtual const TargetInstrInfo &getInstrInfo() const { return instrInfo; }
672 virtual const TargetSchedInfo &getSchedInfo() const { return schedInfo; }
673 virtual const TargetRegInfo &getRegInfo() const { return regInfo; }
674 virtual const TargetFrameInfo &getFrameInfo() const { return frameInfo; }
675 virtual const TargetCacheInfo &getCacheInfo() const { return cacheInfo; }
677 virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
678 virtual bool addPassesToJITCompile(FunctionPassManager &PM);
679 virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
680 MachineCodeEmitter &MCE);
681 virtual void replaceMachineCodeForFunction(void *Old, void *New);
683 // getPrologEpilogInsertionPass - Inserts prolog/epilog code.
684 FunctionPass* getPrologEpilogInsertionPass();
686 // getFunctionAsmPrinterPass - Writes out machine code for a single function
687 Pass* getFunctionAsmPrinterPass(std::ostream &Out);
689 // getModuleAsmPrinterPass - Writes generated machine code to assembly file.
690 Pass* getModuleAsmPrinterPass(std::ostream &Out);
692 // getBytecodeAsmPrinterPass - Emits final LLVM bytecode to assembly file.
693 Pass* getBytecodeAsmPrinterPass(std::ostream &Out);