2 //***************************************************************************
7 // This file defines stuff that is to be private to the Sparc
8 // backend, but is shared among different portions of the backend.
9 //**************************************************************************/
12 #ifndef SPARC_INTERNALS_H
13 #define SPARC_INTERNALS_H
16 #include "SparcRegClassInfo.h"
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/MachineInstrInfo.h"
19 #include "llvm/Target/MachineSchedInfo.h"
20 #include "llvm/Target/MachineFrameInfo.h"
21 #include "llvm/Target/MachineCacheInfo.h"
22 #include "llvm/CodeGen/RegClass.h"
23 #include "llvm/Type.h"
25 #include <sys/types.h>
29 // OpCodeMask definitions for the Sparc V9
31 const OpCodeMask Immed = 0x00002000; // immed or reg operand?
32 const OpCodeMask Annul = 0x20000000; // annul delay instr?
33 const OpCodeMask PredictTaken = 0x00080000; // predict branch taken?
36 enum SparcInstrSchedClass {
37 SPARC_NONE, /* Instructions with no scheduling restrictions */
38 SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
39 SPARC_IEU0, /* Integer class IEU0 */
40 SPARC_IEU1, /* Integer class IEU1 */
41 SPARC_FPM, /* FP Multiply or Divide instructions */
42 SPARC_FPA, /* All other FP instructions */
43 SPARC_CTI, /* Control-transfer instructions */
44 SPARC_LD, /* Load instructions */
45 SPARC_ST, /* Store instructions */
46 SPARC_SINGLE, /* Instructions that must issue by themselves */
48 SPARC_INV, /* This should stay at the end for the next value */
49 SPARC_NUM_SCHED_CLASSES = SPARC_INV
53 //---------------------------------------------------------------------------
54 // enum SparcMachineOpCode.
55 // const MachineInstrDescriptor SparcMachineInstrDesc[]
58 // Description of UltraSparc machine instructions.
60 //---------------------------------------------------------------------------
62 enum SparcMachineOpCode {
63 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
64 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
66 #include "SparcInstr.def"
68 // End-of-array marker
70 NUM_REAL_OPCODES = PHI, // number of valid opcodes
71 NUM_TOTAL_OPCODES = INVALID_OPCODE
75 // Array of machine instruction descriptions...
76 extern const MachineInstrDescriptor SparcMachineInstrDesc[];
79 //---------------------------------------------------------------------------
80 // class UltraSparcInstrInfo
83 // Information about individual instructions.
84 // Most information is stored in the SparcMachineInstrDesc array above.
85 // Other information is computed on demand, and most such functions
86 // default to member functions in base class MachineInstrInfo.
87 //---------------------------------------------------------------------------
89 class UltraSparcInstrInfo : public MachineInstrInfo {
91 /*ctor*/ UltraSparcInstrInfo(const TargetMachine& tgt);
93 virtual bool hasResultInterlock (MachineOpCode opCode) const
95 // All UltraSPARC instructions have interlocks (note that delay slots
96 // are not considered here).
97 // However, instructions that use the result of an FCMP produce a
98 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
99 // Force the compiler to insert a software interlock (i.e., gap of
100 // 2 other groups, including NOPs if necessary).
101 return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
104 //-------------------------------------------------------------------------
105 // Code generation support for creating individual machine instructions
106 //-------------------------------------------------------------------------
108 // Create an instruction sequence to put the constant `val' into
109 // the virtual register `dest'. The generated instructions are
110 // returned in `minstrVec'. Any temporary registers (TmpInstruction)
111 // created are returned in `tempVec'.
113 virtual void CreateCodeToLoadConst(Value* val,
115 vector<MachineInstr*>& minstrVec,
116 vector<TmpInstruction*>& tempVec) const;
119 // Create an instruction sequence to copy an integer value `val'
120 // to a floating point value `dest' by copying to memory and back.
121 // val must be an integral type. dest must be a Float or Double.
122 // The generated instructions are returned in `minstrVec'.
123 // Any temp. registers (TmpInstruction) created are returned in `tempVec'.
125 virtual void CreateCodeToCopyIntToFloat(Method* method,
128 vector<MachineInstr*>& minstrVec,
129 vector<TmpInstruction*>& tempVec,
130 TargetMachine& target) const;
132 // Similarly, create an instruction sequence to copy an FP value
133 // `val' to an integer value `dest' by copying to memory and back.
134 // See the previous function for information about return values.
136 virtual void CreateCodeToCopyFloatToInt(Method* method,
139 vector<MachineInstr*>& minstrVec,
140 vector<TmpInstruction*>& tempVec,
141 TargetMachine& target) const;
145 //----------------------------------------------------------------------------
146 // class UltraSparcRegInfo
148 //----------------------------------------------------------------------------
156 class UltraSparcRegInfo : public MachineRegInfo
161 // The actual register classes in the Sparc
171 // Type of registers available in Sparc. There can be several reg types
172 // in the same class. For instace, the float reg class has Single/Double
182 // the size of a value (int, float, etc..) stored in the stack frame
186 // WARNING: If the above enum order must be changed, also modify
187 // getRegisterClassOfValue method below since it assumes this particular
188 // order for efficiency.
191 // reverse pointer to get info about the ultra sparc machine
192 const UltraSparc *const UltraSparcInfo;
194 // Both int and float rguments can be passed in 6 int regs -
195 // %o0 to %o5 (cannot be changed)
196 unsigned const NumOfIntArgRegs;
197 unsigned const NumOfFloatArgRegs;
198 int const InvalidRegNum;
199 int SizeOfOperandOnStack;
203 //void setCallArgColor(LiveRange *const LR, const unsigned RegNo) const;
205 void setCallOrRetArgCol(LiveRange *const LR, const unsigned RegNo,
206 const MachineInstr *MI,AddedInstrMapType &AIMap)const;
208 MachineInstr * getCopy2RegMI(const Value *SrcVal, const unsigned Reg,
209 unsigned RegClassID) const ;
212 void suggestReg4RetAddr(const MachineInstr * RetMI,
213 LiveRangeInfo& LRI) const;
215 void suggestReg4CallAddr(const MachineInstr * CallMI, LiveRangeInfo& LRI,
216 vector<RegClass *> RCList) const;
219 Value *getValue4ReturnAddr( const MachineInstr * MInst ) const ;
221 int getRegType(const LiveRange *const LR) const {
225 switch( (LR->getRegClass())->getID() ) {
227 case IntRegClassID: return IntRegType;
229 case FloatRegClassID:
230 Typ = LR->getTypeID();
231 if( Typ == Type::FloatTyID )
232 return FPSingleRegType;
233 else if( Typ == Type::DoubleTyID )
234 return FPDoubleRegType;
235 else assert(0 && "Unknown type in FloatRegClass");
237 case IntCCRegClassID: return IntCCRegType;
239 case FloatCCRegClassID: return FloatCCRegType ;
241 default: assert( 0 && "Unknown reg class ID");
247 int getRegType(const Value *const Val) const {
251 switch( getRegClassIDOfValue(Val) ) {
253 case IntRegClassID: return IntRegType;
255 case FloatRegClassID:
256 Typ = (Val->getType())->getPrimitiveID();
257 if( Typ == Type::FloatTyID )
258 return FPSingleRegType;
259 else if( Typ == Type::DoubleTyID )
260 return FPDoubleRegType;
261 else assert(0 && "Unknown type in FloatRegClass");
263 case IntCCRegClassID: return IntCCRegType;
265 case FloatCCRegClassID: return FloatCCRegType ;
267 default: assert( 0 && "Unknown reg class ID");
274 int getRegType(int reg) const {
277 else if ( reg < (32 + 32) )
278 return FPSingleRegType;
279 else if ( reg < (64 + 32) )
280 return FPDoubleRegType;
281 else if( reg < (64+32+4) )
282 return FloatCCRegType;
283 else if( reg < (64+32+4+2) )
286 assert(0 && "Invalid register number in getRegType");
291 // ***TODO: See this method is necessary
293 MachineInstr * cpValue2RegMI(Value * Val, const unsigned DestReg,
294 const int RegType) const;
296 const Value *getCallInstRetAddr(const MachineInstr *CallMI) const;
297 const unsigned getCallInstNumArgs(const MachineInstr *CallMI) const;
300 MachineInstr * cpCCR2IntMI(const unsigned IntReg) const;
301 MachineInstr * cpInt2CCRMI(const unsigned IntReg) const;
305 void moveInst2OrdVec(vector<MachineInstr *> &OrdVec, MachineInstr *UnordInst,
306 PhyRegAlloc &PRA ) const;
308 void OrderAddedInstrns( vector<MachineInstr *> &UnordVec,
309 vector<MachineInstr *> &OrdVec,
310 PhyRegAlloc &PRA) const;
321 UltraSparcRegInfo(const TargetMachine& tgt ) : MachineRegInfo(tgt),
322 UltraSparcInfo(& (const UltraSparc&) tgt),
324 NumOfFloatArgRegs(32),
326 SizeOfOperandOnStack(8)
328 MachineRegClassArr.push_back( new SparcIntRegClass(IntRegClassID) );
329 MachineRegClassArr.push_back( new SparcFloatRegClass(FloatRegClassID) );
330 MachineRegClassArr.push_back( new SparcIntCCRegClass(IntCCRegClassID) );
331 MachineRegClassArr.push_back( new SparcFloatCCRegClass(FloatCCRegClassID));
333 assert( SparcFloatRegOrder::StartOfNonVolatileRegs == 32 &&
334 "32 Float regs are used for float arg passing");
339 ~UltraSparcRegInfo(void) { } // empty destructor
342 inline const UltraSparc & getUltraSparcInfo() const {
343 return *UltraSparcInfo;
348 inline unsigned getRegClassIDOfValue (const Value *const Val,
349 bool isCCReg = false) const {
351 Type::PrimitiveID ty = (Val->getType())->getPrimitiveID();
355 if( (ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
356 (ty == Type::MethodTyID) || (ty == Type::PointerTyID) )
357 res = IntRegClassID; // sparc int reg (ty=0: void)
358 else if( ty <= Type::DoubleTyID)
359 res = FloatRegClassID; // sparc float reg class
361 cerr << "TypeID: " << ty << endl;
362 assert(0 && "Cannot resolve register class for type");
367 return res + 2; // corresponidng condition code regiser
372 // returns the register tha contains always zero
373 // this is the unified register number
374 inline int getZeroRegNum() const { return SparcIntRegOrder::g0; }
376 // returns the reg used for pushing the address when a method is called.
377 // This can be used for other purposes between calls
378 unsigned getCallAddressReg() const { return SparcIntRegOrder::o7; }
381 // and when we return from a method. It should be made sure that this
382 // register contains the return value when a return instruction is reached.
383 unsigned getReturnAddressReg() const { return SparcIntRegOrder::i7; }
385 void suggestRegs4MethodArgs(const Method *const Meth,
386 LiveRangeInfo& LRI) const;
388 void suggestRegs4CallArgs(const MachineInstr *const CallMI,
389 LiveRangeInfo& LRI, vector<RegClass *> RCL) const;
391 void suggestReg4RetValue(const MachineInstr *const RetMI,
392 LiveRangeInfo& LRI ) const;
395 void colorMethodArgs(const Method *const Meth, LiveRangeInfo& LRI,
396 AddedInstrns *const FirstAI) const;
398 void colorCallArgs(const MachineInstr *const CallMI, LiveRangeInfo& LRI,
399 AddedInstrns *const CallAI, PhyRegAlloc &PRA) const;
401 void colorRetValue(const MachineInstr *const RetI, LiveRangeInfo& LRI,
402 AddedInstrns *const RetAI) const;
405 // bool handleSpecialMInstr(const MachineInstr * MInst,
406 // LiveRangeInfo& LRI, vector<RegClass *> RCL) const;
409 static void printReg(const LiveRange *const LR) ;
411 // this method provides a unique number for each register
412 inline int getUnifiedRegNum(int RegClassID, int reg) const {
414 if( RegClassID == IntRegClassID && reg < 32 )
416 else if ( RegClassID == FloatRegClassID && reg < 64)
417 return reg + 32; // we have 32 int regs
418 else if( RegClassID == FloatCCRegClassID && reg < 4)
419 return reg + 32 + 64; // 32 int, 64 float
420 else if( RegClassID == IntCCRegClassID )
421 return 4+ 32 + 64; // only int cc reg
422 else if (reg==InvalidRegNum)
423 return InvalidRegNum;
425 assert(0 && "Invalid register class or reg number");
429 // given the unified register number, this gives the name
430 inline const string getUnifiedRegName(int reg) const {
432 return SparcIntRegOrder::getRegName(reg);
433 else if ( reg < (64 + 32) )
434 return SparcFloatRegOrder::getRegName( reg - 32);
435 else if( reg < (64+32+4) )
436 return SparcFloatCCRegOrder::getRegName( reg -32 - 64);
437 else if( reg < (64+32+4+2) ) // two names: %xcc and %ccr
438 return SparcIntCCRegOrder::getRegName( reg -32 - 64 - 4);
439 else if (reg== InvalidRegNum) //****** TODO: Remove */
442 assert(0 && "Invalid register number");
446 inline unsigned int getRegNumInCallersWindow(int reg) {
447 if (reg == InvalidRegNum || reg >= 32)
449 return SparcIntRegOrder::getRegNumInCallersWindow(reg);
452 inline bool mustBeRemappedInCallersWindow(int reg) {
453 return (reg != InvalidRegNum && reg < 32);
456 const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
458 MachineInstr * cpReg2RegMI(const unsigned SrcReg, const unsigned DestReg,
459 const int RegType) const;
461 MachineInstr * cpReg2MemMI(const unsigned SrcReg, const unsigned DestPtrReg,
462 const int Offset, const int RegType) const;
464 MachineInstr * cpMem2RegMI(const unsigned SrcPtrReg, const int Offset,
465 const unsigned DestReg, const int RegType) const;
467 MachineInstr* cpValue2Value(Value *Src, Value *Dest) const;
470 inline bool isRegVolatile(const int RegClassID, const int Reg) const {
471 return (MachineRegClassArr[RegClassID])->isRegVolatile(Reg);
475 inline unsigned getFramePointer() const {
476 return SparcIntRegOrder::i6;
479 inline unsigned getStackPointer() const {
480 return SparcIntRegOrder::o6;
483 inline int getInvalidRegNum() const {
484 return InvalidRegNum;
488 void insertCallerSavingCode(const MachineInstr *MInst,
489 const BasicBlock *BB, PhyRegAlloc &PRA ) const;
496 /*---------------------------------------------------------------------------
497 Scheduling guidelines for SPARC IIi:
499 I-Cache alignment rules (pg 326)
500 -- Align a branch target instruction so that it's entire group is within
501 the same cache line (may be 1-4 instructions).
502 ** Don't let a branch that is predicted taken be the last instruction
503 on an I-cache line: delay slot will need an entire line to be fetched
504 -- Make a FP instruction or a branch be the 4th instruction in a group.
505 For branches, there are tradeoffs in reordering to make this happen
507 ** Don't put a branch in a group that crosses a 32-byte boundary!
508 An artificial branch is inserted after every 32 bytes, and having
509 another branch will force the group to be broken into 2 groups.
512 -- Don't let a loop span two memory pages, if possible
514 Branch prediction performance:
515 -- Don't make the branch in a delay slot the target of a branch
516 -- Try not to have 2 predicted branches within a group of 4 instructions
517 (because each such group has a single branch target field).
518 -- Try to align branches in slots 0, 2, 4 or 6 of a cache line (to avoid
519 the wrong prediction bits being used in some cases).
521 D-Cache timing constraints:
522 -- Signed int loads of less than 64 bits have 3 cycle latency, not 2
523 -- All other loads that hit in D-Cache have 2 cycle latency
524 -- All loads are returned IN ORDER, so a D-Cache miss will delay a later hit
525 -- Mis-aligned loads or stores cause a trap. In particular, replace
526 mis-aligned FP double precision l/s with 2 single-precision l/s.
527 -- Simulations of integer codes show increase in avg. group size of
528 33% when code (including esp. non-faulting loads) is moved across
529 one branch, and 50% across 2 branches.
531 E-Cache timing constraints:
532 -- Scheduling for E-cache (D-Cache misses) is effective (due to load buffering)
534 Store buffer timing constraints:
535 -- Stores can be executed in same cycle as instruction producing the value
536 -- Stores are buffered and have lower priority for E-cache until
537 highwater mark is reached in the store buffer (5 stores)
539 Pipeline constraints:
540 -- Shifts can only use IEU0.
541 -- CC setting instructions can only use IEU1.
542 -- Several other instructions must only use IEU1:
543 EDGE(?), ARRAY(?), CALL, JMPL, BPr, PST, and FCMP.
544 -- Two instructions cannot store to the same register file in a single cycle
545 (single write port per file).
547 Issue and grouping constraints:
548 -- FP and branch instructions must use slot 4.
549 -- Shift instructions cannot be grouped with other IEU0-specific instructions.
550 -- CC setting instructions cannot be grouped with other IEU1-specific instrs.
551 -- Several instructions must be issued in a single-instruction group:
552 MOVcc or MOVr, MULs/x and DIVs/x, SAVE/RESTORE, many others
553 -- A CALL or JMPL breaks a group, ie, is not combined with subsequent instrs.
557 Branch delay slot scheduling rules:
558 -- A CTI couple (two back-to-back CTI instructions in the dynamic stream)
559 has a 9-instruction penalty: the entire pipeline is flushed when the
560 second instruction reaches stage 9 (W-Writeback).
561 -- Avoid putting multicycle instructions, and instructions that may cause
562 load misses, in the delay slot of an annulling branch.
563 -- Avoid putting WR, SAVE..., RESTORE and RETURN instructions in the
564 delay slot of an annulling branch.
566 *--------------------------------------------------------------------------- */
568 //---------------------------------------------------------------------------
569 // List of CPUResources for UltraSPARC IIi.
570 //---------------------------------------------------------------------------
572 const CPUResource AllIssueSlots( "All Instr Slots", 4);
573 const CPUResource IntIssueSlots( "Int Instr Slots", 3);
574 const CPUResource First3IssueSlots("Instr Slots 0-3", 3);
575 const CPUResource LSIssueSlots( "Load-Store Instr Slot", 1);
576 const CPUResource CTIIssueSlots( "Ctrl Transfer Instr Slot", 1);
577 const CPUResource FPAIssueSlots( "Int Instr Slot 1", 1);
578 const CPUResource FPMIssueSlots( "Int Instr Slot 1", 1);
580 // IEUN instructions can use either Alu and should use IAluN.
581 // IEU0 instructions must use Alu 1 and should use both IAluN and IAlu0.
582 // IEU1 instructions must use Alu 2 and should use both IAluN and IAlu1.
583 const CPUResource IAluN("Int ALU 1or2", 2);
584 const CPUResource IAlu0("Int ALU 1", 1);
585 const CPUResource IAlu1("Int ALU 2", 1);
587 const CPUResource LSAluC1("Load/Store Unit Addr Cycle", 1);
588 const CPUResource LSAluC2("Load/Store Unit Issue Cycle", 1);
589 const CPUResource LdReturn("Load Return Unit", 1);
591 const CPUResource FPMAluC1("FP Mul/Div Alu Cycle 1", 1);
592 const CPUResource FPMAluC2("FP Mul/Div Alu Cycle 2", 1);
593 const CPUResource FPMAluC3("FP Mul/Div Alu Cycle 3", 1);
595 const CPUResource FPAAluC1("FP Other Alu Cycle 1", 1);
596 const CPUResource FPAAluC2("FP Other Alu Cycle 2", 1);
597 const CPUResource FPAAluC3("FP Other Alu Cycle 3", 1);
599 const CPUResource IRegReadPorts("Int Reg ReadPorts", INT_MAX); // CHECK
600 const CPUResource IRegWritePorts("Int Reg WritePorts", 2); // CHECK
601 const CPUResource FPRegReadPorts("FP Reg Read Ports", INT_MAX); // CHECK
602 const CPUResource FPRegWritePorts("FP Reg Write Ports", 1); // CHECK
604 const CPUResource CTIDelayCycle( "CTI delay cycle", 1);
605 const CPUResource FCMPDelayCycle("FCMP delay cycle", 1);
608 //---------------------------------------------------------------------------
609 // const InstrClassRUsage SparcRUsageDesc[]
612 // Resource usage information for instruction in each scheduling class.
613 // The InstrRUsage Objects for individual classes are specified first.
614 // Note that fetch and decode are decoupled from the execution pipelines
615 // via an instr buffer, so they are not included in the cycles below.
616 //---------------------------------------------------------------------------
618 const InstrClassRUsage NoneClassRUsage = {
623 /* isSingleIssue */ false,
624 /* breaksGroup */ false,
628 /* feasibleSlots[] */ { 0, 1, 2, 3 },
642 const InstrClassRUsage IEUNClassRUsage = {
647 /* isSingleIssue */ false,
648 /* breaksGroup */ false,
652 /* feasibleSlots[] */ { 0, 1, 2 },
656 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
657 { IntIssueSlots.rid, 0, 1 },
658 /*Cycle E */ { IAluN.rid, 1, 1 },
663 /*Cycle W */ { IRegWritePorts.rid, 6, 1 }
667 const InstrClassRUsage IEU0ClassRUsage = {
672 /* isSingleIssue */ false,
673 /* breaksGroup */ false,
677 /* feasibleSlots[] */ { 0, 1, 2 },
681 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
682 { IntIssueSlots.rid, 0, 1 },
683 /*Cycle E */ { IAluN.rid, 1, 1 },
689 /*Cycle W */ { IRegWritePorts.rid, 6, 1 }
693 const InstrClassRUsage IEU1ClassRUsage = {
698 /* isSingleIssue */ false,
699 /* breaksGroup */ false,
703 /* feasibleSlots[] */ { 0, 1, 2 },
707 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
708 { IntIssueSlots.rid, 0, 1 },
709 /*Cycle E */ { IAluN.rid, 1, 1 },
715 /*Cycle W */ { IRegWritePorts.rid, 6, 1 }
719 const InstrClassRUsage FPMClassRUsage = {
724 /* isSingleIssue */ false,
725 /* breaksGroup */ false,
729 /* feasibleSlots[] */ { 0, 1, 2, 3 },
733 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
734 { FPMIssueSlots.rid, 0, 1 },
735 /*Cycle E */ { FPRegReadPorts.rid, 1, 1 },
736 /*Cycle C */ { FPMAluC1.rid, 2, 1 },
737 /*Cycle N1*/ { FPMAluC2.rid, 3, 1 },
738 /*Cycle N1*/ { FPMAluC3.rid, 4, 1 },
740 /*Cycle W */ { FPRegWritePorts.rid, 6, 1 }
744 const InstrClassRUsage FPAClassRUsage = {
749 /* isSingleIssue */ false,
750 /* breaksGroup */ false,
754 /* feasibleSlots[] */ { 0, 1, 2, 3 },
758 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
759 { FPAIssueSlots.rid, 0, 1 },
760 /*Cycle E */ { FPRegReadPorts.rid, 1, 1 },
761 /*Cycle C */ { FPAAluC1.rid, 2, 1 },
762 /*Cycle N1*/ { FPAAluC2.rid, 3, 1 },
763 /*Cycle N1*/ { FPAAluC3.rid, 4, 1 },
765 /*Cycle W */ { FPRegWritePorts.rid, 6, 1 }
769 const InstrClassRUsage LDClassRUsage = {
774 /* isSingleIssue */ false,
775 /* breaksGroup */ false,
779 /* feasibleSlots[] */ { 0, 1, 2, },
783 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
784 { First3IssueSlots.rid, 0, 1 },
785 { LSIssueSlots.rid, 0, 1 },
786 /*Cycle E */ { LSAluC1.rid, 1, 1 },
787 /*Cycle C */ { LSAluC2.rid, 2, 1 },
788 { LdReturn.rid, 2, 1 },
792 /*Cycle W */ { IRegWritePorts.rid, 6, 1 }
796 const InstrClassRUsage STClassRUsage = {
801 /* isSingleIssue */ false,
802 /* breaksGroup */ false,
806 /* feasibleSlots[] */ { 0, 1, 2 },
810 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
811 { First3IssueSlots.rid, 0, 1 },
812 { LSIssueSlots.rid, 0, 1 },
813 /*Cycle E */ { LSAluC1.rid, 1, 1 },
814 /*Cycle C */ { LSAluC2.rid, 2, 1 }
822 const InstrClassRUsage CTIClassRUsage = {
827 /* isSingleIssue */ false,
828 /* breaksGroup */ false,
832 /* feasibleSlots[] */ { 0, 1, 2, 3 },
836 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
837 { CTIIssueSlots.rid, 0, 1 },
838 /*Cycle E */ { IAlu0.rid, 1, 1 },
839 /*Cycles E-C */ { CTIDelayCycle.rid, 1, 2 }
848 const InstrClassRUsage SingleClassRUsage = {
853 /* isSingleIssue */ true,
854 /* breaksGroup */ false,
858 /* feasibleSlots[] */ { 0 },
862 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
863 { AllIssueSlots.rid, 0, 1 },
864 { AllIssueSlots.rid, 0, 1 },
865 { AllIssueSlots.rid, 0, 1 },
866 /*Cycle E */ { IAlu0.rid, 1, 1 }
876 const InstrClassRUsage SparcRUsageDesc[] = {
890 //---------------------------------------------------------------------------
891 // const InstrIssueDelta SparcInstrIssueDeltas[]
894 // Changes to issue restrictions information in InstrClassRUsage for
895 // instructions that differ from other instructions in their class.
896 //---------------------------------------------------------------------------
898 const InstrIssueDelta SparcInstrIssueDeltas[] = {
900 // opCode, isSingleIssue, breaksGroup, numBubbles
902 // Special cases for single-issue only
903 // Other single issue cases are below.
904 //{ LDDA, true, true, 0 },
905 //{ STDA, true, true, 0 },
906 //{ LDDF, true, true, 0 },
907 //{ LDDFA, true, true, 0 },
908 { ADDC, true, true, 0 },
909 { ADDCcc, true, true, 0 },
910 { SUBC, true, true, 0 },
911 { SUBCcc, true, true, 0 },
912 //{ LDSTUB, true, true, 0 },
913 //{ SWAP, true, true, 0 },
914 //{ SWAPA, true, true, 0 },
915 //{ CAS, true, true, 0 },
916 //{ CASA, true, true, 0 },
917 //{ CASX, true, true, 0 },
918 //{ CASXA, true, true, 0 },
919 //{ LDFSR, true, true, 0 },
920 //{ LDFSRA, true, true, 0 },
921 //{ LDXFSR, true, true, 0 },
922 //{ LDXFSRA, true, true, 0 },
923 //{ STFSR, true, true, 0 },
924 //{ STFSRA, true, true, 0 },
925 //{ STXFSR, true, true, 0 },
926 //{ STXFSRA, true, true, 0 },
927 //{ SAVED, true, true, 0 },
928 //{ RESTORED, true, true, 0 },
929 //{ FLUSH, true, true, 9 },
930 //{ FLUSHW, true, true, 9 },
931 //{ ALIGNADDR, true, true, 0 },
932 { RETURN, true, true, 0 },
933 //{ DONE, true, true, 0 },
934 //{ RETRY, true, true, 0 },
935 //{ TCC, true, true, 0 },
936 //{ SHUTDOWN, true, true, 0 },
938 // Special cases for breaking group *before*
939 // CURRENTLY NOT SUPPORTED!
940 { CALL, false, false, 0 },
941 { JMPLCALL, false, false, 0 },
942 { JMPLRET, false, false, 0 },
944 // Special cases for breaking the group *after*
945 { MULX, true, true, (4+34)/2 },
946 { FDIVS, false, true, 0 },
947 { FDIVD, false, true, 0 },
948 { FDIVQ, false, true, 0 },
949 { FSQRTS, false, true, 0 },
950 { FSQRTD, false, true, 0 },
951 { FSQRTQ, false, true, 0 },
952 //{ FCMP{LE,GT,NE,EQ}, false, true, 0 },
954 // Instructions that introduce bubbles
955 //{ MULScc, true, true, 2 },
956 //{ SMULcc, true, true, (4+18)/2 },
957 //{ UMULcc, true, true, (4+19)/2 },
958 { SDIVX, true, true, 68 },
959 { UDIVX, true, true, 68 },
960 //{ SDIVcc, true, true, 36 },
961 //{ UDIVcc, true, true, 37 },
962 { WRCCR, true, true, 4 },
963 //{ WRPR, true, true, 4 },
964 //{ RDCCR, true, true, 0 }, // no bubbles after, but see below
965 //{ RDPR, true, true, 0 },
969 //---------------------------------------------------------------------------
970 // const InstrRUsageDelta SparcInstrUsageDeltas[]
973 // Changes to resource usage information in InstrClassRUsage for
974 // instructions that differ from other instructions in their class.
975 //---------------------------------------------------------------------------
977 const InstrRUsageDelta SparcInstrUsageDeltas[] = {
979 // MachineOpCode, Resource, Start cycle, Num cycles
982 // JMPL counts as a load/store instruction for issue!
984 { JMPLCALL, LSIssueSlots.rid, 0, 1 },
985 { JMPLRET, LSIssueSlots.rid, 0, 1 },
988 // Many instructions cannot issue for the next 2 cycles after an FCMP
989 // We model that with a fake resource FCMPDelayCycle.
991 { FCMPS, FCMPDelayCycle.rid, 1, 3 },
992 { FCMPD, FCMPDelayCycle.rid, 1, 3 },
993 { FCMPQ, FCMPDelayCycle.rid, 1, 3 },
995 { MULX, FCMPDelayCycle.rid, 1, 1 },
996 { SDIVX, FCMPDelayCycle.rid, 1, 1 },
997 { UDIVX, FCMPDelayCycle.rid, 1, 1 },
998 //{ SMULcc, FCMPDelayCycle.rid, 1, 1 },
999 //{ UMULcc, FCMPDelayCycle.rid, 1, 1 },
1000 //{ SDIVcc, FCMPDelayCycle.rid, 1, 1 },
1001 //{ UDIVcc, FCMPDelayCycle.rid, 1, 1 },
1002 { STD, FCMPDelayCycle.rid, 1, 1 },
1003 { FMOVRSZ, FCMPDelayCycle.rid, 1, 1 },
1004 { FMOVRSLEZ,FCMPDelayCycle.rid, 1, 1 },
1005 { FMOVRSLZ, FCMPDelayCycle.rid, 1, 1 },
1006 { FMOVRSNZ, FCMPDelayCycle.rid, 1, 1 },
1007 { FMOVRSGZ, FCMPDelayCycle.rid, 1, 1 },
1008 { FMOVRSGEZ,FCMPDelayCycle.rid, 1, 1 },
1011 // Some instructions are stalled in the GROUP stage if a CTI is in
1012 // the E or C stage. We model that with a fake resource CTIDelayCycle.
1014 { LDD, CTIDelayCycle.rid, 1, 1 },
1015 //{ LDDA, CTIDelayCycle.rid, 1, 1 },
1016 //{ LDDSTUB, CTIDelayCycle.rid, 1, 1 },
1017 //{ LDDSTUBA, CTIDelayCycle.rid, 1, 1 },
1018 //{ SWAP, CTIDelayCycle.rid, 1, 1 },
1019 //{ SWAPA, CTIDelayCycle.rid, 1, 1 },
1020 //{ CAS, CTIDelayCycle.rid, 1, 1 },
1021 //{ CASA, CTIDelayCycle.rid, 1, 1 },
1022 //{ CASX, CTIDelayCycle.rid, 1, 1 },
1023 //{ CASXA, CTIDelayCycle.rid, 1, 1 },
1026 // Signed int loads of less than dword size return data in cycle N1 (not C)
1027 // and put all loads in consecutive cycles into delayed load return mode.
1029 { LDSB, LdReturn.rid, 2, -1 },
1030 { LDSB, LdReturn.rid, 3, 1 },
1032 { LDSH, LdReturn.rid, 2, -1 },
1033 { LDSH, LdReturn.rid, 3, 1 },
1035 { LDSW, LdReturn.rid, 2, -1 },
1036 { LDSW, LdReturn.rid, 3, 1 },
1039 // RDPR from certain registers and RD from any register are not dispatchable
1040 // until four clocks after they reach the head of the instr. buffer.
1041 // Together with their single-issue requirement, this means all four issue
1042 // slots are effectively blocked for those cycles, plus the issue cycle.
1043 // This does not increase the latency of the instruction itself.
1045 { RDCCR, AllIssueSlots.rid, 0, 5 },
1046 { RDCCR, AllIssueSlots.rid, 0, 5 },
1047 { RDCCR, AllIssueSlots.rid, 0, 5 },
1048 { RDCCR, AllIssueSlots.rid, 0, 5 },
1050 #undef EXPLICIT_BUBBLES_NEEDED
1051 #ifdef EXPLICIT_BUBBLES_NEEDED
1053 // MULScc inserts one bubble.
1054 // This means it breaks the current group (captured in UltraSparcSchedInfo)
1055 // *and occupies all issue slots for the next cycle
1057 //{ MULScc, AllIssueSlots.rid, 2, 2-1 },
1058 //{ MULScc, AllIssueSlots.rid, 2, 2-1 },
1059 //{ MULScc, AllIssueSlots.rid, 2, 2-1 },
1060 //{ MULScc, AllIssueSlots.rid, 2, 2-1 },
1063 // SMULcc inserts between 4 and 18 bubbles, depending on #leading 0s in rs1.
1064 // We just model this with a simple average.
1066 //{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
1067 //{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
1068 //{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
1069 //{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
1071 // SMULcc inserts between 4 and 19 bubbles, depending on #leading 0s in rs1.
1072 //{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
1073 //{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
1074 //{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
1075 //{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
1078 // MULX inserts between 4 and 34 bubbles, depending on #leading 0s in rs1.
1080 { MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
1081 { MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
1082 { MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
1083 { MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
1086 // SDIVcc inserts 36 bubbles.
1088 //{ SDIVcc, AllIssueSlots.rid, 2, 36-1 },
1089 //{ SDIVcc, AllIssueSlots.rid, 2, 36-1 },
1090 //{ SDIVcc, AllIssueSlots.rid, 2, 36-1 },
1091 //{ SDIVcc, AllIssueSlots.rid, 2, 36-1 },
1093 // UDIVcc inserts 37 bubbles.
1094 //{ UDIVcc, AllIssueSlots.rid, 2, 37-1 },
1095 //{ UDIVcc, AllIssueSlots.rid, 2, 37-1 },
1096 //{ UDIVcc, AllIssueSlots.rid, 2, 37-1 },
1097 //{ UDIVcc, AllIssueSlots.rid, 2, 37-1 },
1100 // SDIVX inserts 68 bubbles.
1102 { SDIVX, AllIssueSlots.rid, 2, 68-1 },
1103 { SDIVX, AllIssueSlots.rid, 2, 68-1 },
1104 { SDIVX, AllIssueSlots.rid, 2, 68-1 },
1105 { SDIVX, AllIssueSlots.rid, 2, 68-1 },
1108 // UDIVX inserts 68 bubbles.
1110 { UDIVX, AllIssueSlots.rid, 2, 68-1 },
1111 { UDIVX, AllIssueSlots.rid, 2, 68-1 },
1112 { UDIVX, AllIssueSlots.rid, 2, 68-1 },
1113 { UDIVX, AllIssueSlots.rid, 2, 68-1 },
1116 // WR inserts 4 bubbles.
1118 //{ WR, AllIssueSlots.rid, 2, 68-1 },
1119 //{ WR, AllIssueSlots.rid, 2, 68-1 },
1120 //{ WR, AllIssueSlots.rid, 2, 68-1 },
1121 //{ WR, AllIssueSlots.rid, 2, 68-1 },
1124 // WRPR inserts 4 bubbles.
1126 //{ WRPR, AllIssueSlots.rid, 2, 68-1 },
1127 //{ WRPR, AllIssueSlots.rid, 2, 68-1 },
1128 //{ WRPR, AllIssueSlots.rid, 2, 68-1 },
1129 //{ WRPR, AllIssueSlots.rid, 2, 68-1 },
1132 // DONE inserts 9 bubbles.
1134 //{ DONE, AllIssueSlots.rid, 2, 9-1 },
1135 //{ DONE, AllIssueSlots.rid, 2, 9-1 },
1136 //{ DONE, AllIssueSlots.rid, 2, 9-1 },
1137 //{ DONE, AllIssueSlots.rid, 2, 9-1 },
1140 // RETRY inserts 9 bubbles.
1142 //{ RETRY, AllIssueSlots.rid, 2, 9-1 },
1143 //{ RETRY, AllIssueSlots.rid, 2, 9-1 },
1144 //{ RETRY, AllIssueSlots.rid, 2, 9-1 },
1145 //{ RETRY, AllIssueSlots.rid, 2, 9-1 },
1147 #endif /*EXPLICIT_BUBBLES_NEEDED */
1152 // Additional delays to be captured in code:
1153 // 1. RDPR from several state registers (page 349)
1154 // 2. RD from *any* register (page 349)
1155 // 3. Writes to TICK, PSTATE, TL registers and FLUSH{W} instr (page 349)
1156 // 4. Integer store can be in same group as instr producing value to store.
1157 // 5. BICC and BPICC can be in the same group as instr producing CC (pg 350)
1158 // 6. FMOVr cannot be in the same or next group as an IEU instr (pg 351).
1159 // 7. The second instr. of a CTI group inserts 9 bubbles (pg 351)
1160 // 8. WR{PR}, SVAE, SAVED, RESTORE, RESTORED, RETURN, RETRY, and DONE that
1161 // follow an annulling branch cannot be issued in the same group or in
1162 // the 3 groups following the branch.
1163 // 9. A predicted annulled load does not stall dependent instructions.
1164 // Other annulled delay slot instructions *do* stall dependents, so
1165 // nothing special needs to be done for them during scheduling.
1166 //10. Do not put a load use that may be annulled in the same group as the
1167 // branch. The group will stall until the load returns.
1168 //11. Single-prec. FP loads lock 2 registers, for dependency checking.
1171 // Additional delays we cannot or will not capture:
1172 // 1. If DCTI is last word of cache line, it is delayed until next line can be
1173 // fetched. Also, other DCTI alignment-related delays (pg 352)
1174 // 2. Load-after-store is delayed by 7 extra cycles if load hits in D-Cache.
1175 // Also, several other store-load and load-store conflicts (pg 358)
1176 // 3. MEMBAR, LD{X}FSR, LDD{A} and a bunch of other load stalls (pg 358)
1177 // 4. There can be at most 8 outstanding buffered store instructions
1178 // (including some others like MEMBAR, LDSTUB, CAS{AX}, and FLUSH)
1182 //---------------------------------------------------------------------------
1183 // class UltraSparcSchedInfo
1186 // Interface to instruction scheduling information for UltraSPARC.
1187 // The parameter values above are based on UltraSPARC IIi.
1188 //---------------------------------------------------------------------------
1191 class UltraSparcSchedInfo: public MachineSchedInfo {
1193 /*ctor*/ UltraSparcSchedInfo (const TargetMachine& tgt);
1194 /*dtor*/ virtual ~UltraSparcSchedInfo () {}
1196 virtual void initializeResources ();
1200 //---------------------------------------------------------------------------
1201 // class UltraSparcFrameInfo
1204 // Interface to stack frame layout info for the UltraSPARC.
1205 //---------------------------------------------------------------------------
1207 class UltraSparcFrameInfo: public MachineFrameInfo {
1209 /*ctor*/ UltraSparcFrameInfo(const TargetMachine& tgt) : MachineFrameInfo(tgt) {}
1212 int getStackFrameSizeAlignment () const { return StackFrameSizeAlignment;}
1213 int getMinStackFrameSize () const { return MinStackFrameSize; }
1214 int getNumFixedOutgoingArgs () const { return NumFixedOutgoingArgs; }
1215 int getSizeOfEachArgOnStack () const { return SizeOfEachArgOnStack; }
1216 bool argsOnStackHaveFixedSize () const { return true; }
1219 // These methods compute offsets using the frame contents for a
1220 // particular method. The frame contents are obtained from the
1221 // MachineCodeInfoForMethod object for the given method.
1223 int getFirstIncomingArgOffset (MachineCodeForMethod& mcInfo,
1226 pos = true; // arguments area grows upwards
1227 return FirstIncomingArgOffsetFromFP;
1229 int getFirstOutgoingArgOffset (MachineCodeForMethod& mcInfo,
1232 pos = true; // arguments area grows upwards
1233 return FirstOutgoingArgOffsetFromSP;
1235 int getFirstOptionalOutgoingArgOffset(MachineCodeForMethod& mcInfo,
1238 pos = true; // arguments area grows upwards
1239 return FirstOptionalOutgoingArgOffsetFromSP;
1242 int getFirstAutomaticVarOffset (MachineCodeForMethod& mcInfo,
1244 int getRegSpillAreaOffset (MachineCodeForMethod& mcInfo,
1246 int getTmpAreaOffset (MachineCodeForMethod& mcInfo,
1248 int getDynamicAreaOffset (MachineCodeForMethod& mcInfo,
1252 // These methods specify the base register used for each stack area
1253 // (generally FP or SP)
1255 virtual int getIncomingArgBaseRegNum() const {
1256 return (int) target.getRegInfo().getFramePointer();
1258 virtual int getOutgoingArgBaseRegNum() const {
1259 return (int) target.getRegInfo().getStackPointer();
1261 virtual int getOptionalOutgoingArgBaseRegNum() const {
1262 return (int) target.getRegInfo().getStackPointer();
1264 virtual int getAutomaticVarBaseRegNum() const {
1265 return (int) target.getRegInfo().getFramePointer();
1267 virtual int getRegSpillAreaBaseRegNum() const {
1268 return (int) target.getRegInfo().getFramePointer();
1270 virtual int getDynamicAreaBaseRegNum() const {
1271 return (int) target.getRegInfo().getStackPointer();
1275 // All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
1276 static const int OFFSET = (int) 0x7ff;
1277 static const int StackFrameSizeAlignment = 16;
1278 static const int MinStackFrameSize = 176;
1279 static const int NumFixedOutgoingArgs = 6;
1280 static const int SizeOfEachArgOnStack = 8;
1281 static const int StaticAreaOffsetFromFP = -1 + OFFSET;
1282 static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
1283 static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
1284 static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
1285 static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
1289 //---------------------------------------------------------------------------
1290 // class UltraSparcCacheInfo
1293 // Interface to cache parameters for the UltraSPARC.
1294 // Just use defaults for now.
1295 //---------------------------------------------------------------------------
1297 class UltraSparcCacheInfo: public MachineCacheInfo {
1299 /*ctor*/ UltraSparcCacheInfo (const TargetMachine& target) :
1300 MachineCacheInfo(target) {}
1304 //---------------------------------------------------------------------------
1305 // class UltraSparcMachine
1308 // Primary interface to machine description for the UltraSPARC.
1309 // Primarily just initializes machine-dependent parameters in
1310 // class TargetMachine, and creates machine-dependent subclasses
1311 // for classes such as InstrInfo, SchedInfo and RegInfo.
1312 //---------------------------------------------------------------------------
1314 class UltraSparc : public TargetMachine {
1316 UltraSparcInstrInfo instrInfo;
1317 UltraSparcSchedInfo schedInfo;
1318 UltraSparcRegInfo regInfo;
1319 UltraSparcFrameInfo frameInfo;
1320 UltraSparcCacheInfo cacheInfo;
1323 virtual ~UltraSparc() {}
1325 virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
1326 virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
1327 virtual const MachineRegInfo &getRegInfo() const { return regInfo; }
1328 virtual const MachineFrameInfo &getFrameInfo() const { return frameInfo; }
1329 virtual const MachineCacheInfo &getCacheInfo() const { return cacheInfo; }
1331 // compileMethod - For the sparc, we do instruction selection, followed by
1332 // delay slot scheduling, then register allocation.
1334 virtual bool compileMethod(Method *M);
1337 // emitAssembly - Output assembly language code (a .s file) for the specified
1338 // module. The specified module must have been compiled before this may be
1341 virtual void emitAssembly(const Module *M, ostream &OutStr) const;