1 //===-- SparcInternals.h ----------------------------------------*- C++ -*-===//
3 // This file defines stuff that is to be private to the Sparc backend, but is
4 // shared among different portions of the backend.
6 //===----------------------------------------------------------------------===//
8 #ifndef SPARC_INTERNALS_H
9 #define SPARC_INTERNALS_H
11 #include "llvm/CodeGen/MachineInstrBuilder.h"
12 #include "llvm/Target/TargetMachine.h"
13 #include "llvm/Target/TargetSchedInfo.h"
14 #include "llvm/Target/TargetFrameInfo.h"
15 #include "llvm/Target/TargetCacheInfo.h"
16 #include "llvm/Target/TargetRegInfo.h"
17 #include "llvm/Target/TargetOptInfo.h"
18 #include "llvm/Type.h"
19 #include "SparcRegClassInfo.h"
20 #include <sys/types.h>
27 enum SparcInstrSchedClass {
28 SPARC_NONE, /* Instructions with no scheduling restrictions */
29 SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
30 SPARC_IEU0, /* Integer class IEU0 */
31 SPARC_IEU1, /* Integer class IEU1 */
32 SPARC_FPM, /* FP Multiply or Divide instructions */
33 SPARC_FPA, /* All other FP instructions */
34 SPARC_CTI, /* Control-transfer instructions */
35 SPARC_LD, /* Load instructions */
36 SPARC_ST, /* Store instructions */
37 SPARC_SINGLE, /* Instructions that must issue by themselves */
39 SPARC_INV, /* This should stay at the end for the next value */
40 SPARC_NUM_SCHED_CLASSES = SPARC_INV
44 //---------------------------------------------------------------------------
45 // enum SparcMachineOpCode.
46 // const TargetInstrDescriptor SparcMachineInstrDesc[]
49 // Description of UltraSparc machine instructions.
51 //---------------------------------------------------------------------------
54 enum SparcMachineOpCode {
55 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
56 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
58 #include "SparcInstr.def"
60 // End-of-array marker
62 NUM_REAL_OPCODES = PHI, // number of valid opcodes
63 NUM_TOTAL_OPCODES = INVALID_OPCODE
68 // Array of machine instruction descriptions...
69 extern const TargetInstrDescriptor SparcMachineInstrDesc[];
72 //---------------------------------------------------------------------------
73 // class UltraSparcInstrInfo
76 // Information about individual instructions.
77 // Most information is stored in the SparcMachineInstrDesc array above.
78 // Other information is computed on demand, and most such functions
79 // default to member functions in base class TargetInstrInfo.
80 //---------------------------------------------------------------------------
82 struct UltraSparcInstrInfo : public TargetInstrInfo {
83 UltraSparcInstrInfo();
86 // All immediate constants are in position 1 except the
87 // store instructions and SETxx.
89 virtual int getImmedConstantPos(MachineOpCode opCode) const {
91 if (this->maxImmedConstant(opCode, ignore) != 0) {
93 assert(! this->isStore((MachineOpCode) V9::STBr - 1));
95 assert(! this->isStore((MachineOpCode) V9::STXFSRi + 1));
97 if (opCode == V9::SETSW || opCode == V9::SETUW ||
98 opCode == V9::SETX || opCode == V9::SETHI)
100 if (opCode >= V9::STBr && opCode <= V9::STXFSRi)
108 /// createNOPinstr - returns the target's implementation of NOP, which is
109 /// usually a pseudo-instruction, implemented by a degenerate version of
110 /// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi 0, g0
112 MachineInstr* createNOPinstr() const {
113 return BuildMI(V9::SETHI, 2).addZImm(0).addReg(SparcIntRegClass::g0);
116 /// isNOPinstr - not having a special NOP opcode, we need to know if a given
117 /// instruction is interpreted as an `official' NOP instr, i.e., there may be
118 /// more than one way to `do nothing' but only one canonical way to slack off.
120 bool isNOPinstr(const MachineInstr &MI) const {
121 // Make sure the instruction is EXACTLY `sethi g0, 0'
122 if (MI.getOpcode() == V9::SETHI && MI.getNumOperands() == 2) {
123 const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
124 if (op0.isImmediate() && op0.getImmedValue() == 0 &&
125 op1.isMachineRegister() &&
126 op1.getMachineRegNum() == SparcIntRegClass::g0)
134 virtual bool hasResultInterlock(MachineOpCode opCode) const
136 // All UltraSPARC instructions have interlocks (note that delay slots
137 // are not considered here).
138 // However, instructions that use the result of an FCMP produce a
139 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
140 // Force the compiler to insert a software interlock (i.e., gap of
141 // 2 other groups, including NOPs if necessary).
142 return (opCode == V9::FCMPS || opCode == V9::FCMPD || opCode == V9::FCMPQ);
145 //-------------------------------------------------------------------------
146 // Queries about representation of LLVM quantities (e.g., constants)
147 //-------------------------------------------------------------------------
149 virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
150 const Instruction* I) const;
152 //-------------------------------------------------------------------------
153 // Code generation support for creating individual machine instructions
154 //-------------------------------------------------------------------------
156 // Get certain common op codes for the current target. This and all the
157 // Create* methods below should be moved to a machine code generation class
159 virtual MachineOpCode getNOPOpCode() const { return V9::NOP; }
161 // Create an instruction sequence to put the constant `val' into
162 // the virtual register `dest'. `val' may be a Constant or a
163 // GlobalValue, viz., the constant address of a global variable or function.
164 // The generated instructions are returned in `mvec'.
165 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
166 // Any stack space required is allocated via mcff.
168 virtual void CreateCodeToLoadConst(const TargetMachine& target,
172 std::vector<MachineInstr*>& mvec,
173 MachineCodeForInstruction& mcfi) const;
175 // Create an instruction sequence to copy an integer value `val'
176 // to a floating point value `dest' by copying to memory and back.
177 // val must be an integral type. dest must be a Float or Double.
178 // The generated instructions are returned in `mvec'.
179 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
180 // Any stack space required is allocated via mcff.
182 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
186 std::vector<MachineInstr*>& mvec,
187 MachineCodeForInstruction& mcfi) const;
189 // Similarly, create an instruction sequence to copy an FP value
190 // `val' to an integer value `dest' by copying to memory and back.
191 // The generated instructions are returned in `mvec'.
192 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
193 // Any stack space required is allocated via mcff.
195 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
199 std::vector<MachineInstr*>& mvec,
200 MachineCodeForInstruction& mcfi) const;
202 // Create instruction(s) to copy src to dest, for arbitrary types
203 // The generated instructions are returned in `mvec'.
204 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
205 // Any stack space required is allocated via mcff.
207 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
211 std::vector<MachineInstr*>& mvec,
212 MachineCodeForInstruction& mcfi) const;
214 // Create instruction sequence to produce a sign-extended register value
215 // from an arbitrary sized value (sized in bits, not bytes).
216 // The generated instructions are appended to `mvec'.
217 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
218 // Any stack space required is allocated via mcff.
220 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
224 unsigned int numLowBits,
225 std::vector<MachineInstr*>& mvec,
226 MachineCodeForInstruction& mcfi) const;
228 // Create instruction sequence to produce a zero-extended register value
229 // from an arbitrary sized value (sized in bits, not bytes).
230 // The generated instructions are appended to `mvec'.
231 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
232 // Any stack space required is allocated via mcff.
234 virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
238 unsigned int numLowBits,
239 std::vector<MachineInstr*>& mvec,
240 MachineCodeForInstruction& mcfi) const;
244 //----------------------------------------------------------------------------
245 // class UltraSparcRegInfo
247 // This class implements the virtual class TargetRegInfo for Sparc.
249 //----------------------------------------------------------------------------
251 class UltraSparcRegInfo : public TargetRegInfo {
252 // The actual register classes in the Sparc
255 IntRegClassID, // Integer
256 FloatRegClassID, // Float (both single/double)
257 IntCCRegClassID, // Int Condition Code
258 FloatCCRegClassID, // Float Condition code
259 SpecialRegClassID // Special (unallocated) registers
262 // **** WARNING: If the above enum order is changed, also modify
263 // getRegisterClassOfValue method below since it assumes this particular
264 // order for efficiency.
267 // Number of registers used for passing int args (usually 6: %o0 - %o5)
269 unsigned const NumOfIntArgRegs;
271 // Number of registers used for passing float args (usually 32: %f0 - %f31)
273 unsigned const NumOfFloatArgRegs;
275 // ======================== Private Methods =============================
277 // The following methods are used to color special live ranges (e.g.
278 // function args and return values etc.) with specific hardware registers
279 // as required. See SparcRegInfo.cpp for the implementation.
281 void suggestReg4RetAddr(MachineInstr *RetMI,
282 LiveRangeInfo &LRI) const;
284 void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI) const;
286 void InitializeOutgoingArg(MachineInstr* CallMI, AddedInstrns *CallAI,
287 PhyRegAlloc &PRA, LiveRange* LR,
288 unsigned regType, unsigned RegClassID,
289 int UniArgReg, unsigned int argNo,
290 std::vector<MachineInstr *>& AddedInstrnsBefore)
293 // Helper used by the all the getRegType() functions.
294 int getRegTypeForClassAndType(unsigned regClassID, const Type* type) const;
296 // Used to generate a copy instruction based on the register class of
299 MachineInstr *cpValue2RegMI(Value *Val, unsigned DestReg,
303 // The following 2 methods are used to order the instructions addeed by
304 // the register allocator in association with function calling. See
305 // SparcRegInfo.cpp for more details
307 void moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
308 MachineInstr *UnordInst,
309 PhyRegAlloc &PRA) const;
311 void OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
312 std::vector<MachineInstr *> &OrdVec,
313 PhyRegAlloc &PRA) const;
316 // Type of registers available in Sparc. There can be several reg types
317 // in the same class. For instace, the float reg class has Single/Double
329 UltraSparcRegInfo(const UltraSparc &tgt);
331 // To find the register class used for a specified Type
333 unsigned getRegClassIDOfType(const Type *type,
334 bool isCCReg = false) const;
336 // To find the register class to which a specified register belongs
338 unsigned getRegClassIDOfRegType(int regType) const;
340 // getZeroRegNum - returns the register that contains always zero this is the
341 // unified register number
343 virtual int getZeroRegNum() const;
345 // getCallAddressReg - returns the reg used for pushing the address when a
346 // function is called. This can be used for other purposes between calls
348 unsigned getCallAddressReg() const;
350 // Returns the register containing the return address.
351 // It should be made sure that this register contains the return
352 // value when a return instruction is reached.
354 unsigned getReturnAddressReg() const;
356 // Number of registers used for passing int args (usually 6: %o0 - %o5)
357 // and float args (usually 32: %f0 - %f31)
359 unsigned const getNumOfIntArgRegs() const { return NumOfIntArgRegs; }
360 unsigned const getNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
362 // Compute which register can be used for an argument, if any
364 int regNumForIntArg(bool inCallee, bool isVarArgsCall,
365 unsigned argNo, unsigned& regClassId) const;
367 int regNumForFPArg(unsigned RegType, bool inCallee, bool isVarArgsCall,
368 unsigned argNo, unsigned& regClassId) const;
370 // The following methods are used to color special live ranges (e.g.
371 // function args and return values etc.) with specific hardware registers
372 // as required. See SparcRegInfo.cpp for the implementation for Sparc.
374 void suggestRegs4MethodArgs(const Function *Meth,
375 LiveRangeInfo& LRI) const;
377 void suggestRegs4CallArgs(MachineInstr *CallMI,
378 LiveRangeInfo& LRI) const;
380 void suggestReg4RetValue(MachineInstr *RetMI,
381 LiveRangeInfo& LRI) const;
383 void colorMethodArgs(const Function *Meth, LiveRangeInfo &LRI,
384 AddedInstrns *FirstAI) const;
386 void colorCallArgs(MachineInstr *CallMI, LiveRangeInfo &LRI,
387 AddedInstrns *CallAI, PhyRegAlloc &PRA,
388 const BasicBlock *BB) const;
390 void colorRetValue(MachineInstr *RetI, LiveRangeInfo& LRI,
391 AddedInstrns *RetAI) const;
394 // method used for printing a register for debugging purposes
396 void printReg(const LiveRange *LR) const;
398 // returns the # of bytes of stack space allocated for each register
399 // type. For Sparc, currently we allocate 8 bytes on stack for all
400 // register types. We can optimize this later if necessary to save stack
401 // space (However, should make sure that stack alignment is correct)
403 inline int getSpilledRegSize(int RegType) const {
408 // To obtain the return value and the indirect call address (if any)
409 // contained in a CALL machine instruction
411 const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
412 const Value * getCallInstIndirectAddrVal(const MachineInstr *CallMI) const;
414 // The following methods are used to generate "copy" machine instructions
415 // for an architecture.
417 // The function regTypeNeedsScratchReg() can be used to check whether a
418 // scratch register is needed to copy a register of type `regType' to
419 // or from memory. If so, such a scratch register can be provided by
420 // the caller (e.g., if it knows which regsiters are free); otherwise
421 // an arbitrary one will be chosen and spilled by the copy instructions.
423 bool regTypeNeedsScratchReg(int RegType,
424 int& scratchRegClassId) const;
426 void cpReg2RegMI(std::vector<MachineInstr*>& mvec,
427 unsigned SrcReg, unsigned DestReg,
430 void cpReg2MemMI(std::vector<MachineInstr*>& mvec,
431 unsigned SrcReg, unsigned DestPtrReg,
432 int Offset, int RegType, int scratchReg = -1) const;
434 void cpMem2RegMI(std::vector<MachineInstr*>& mvec,
435 unsigned SrcPtrReg, int Offset, unsigned DestReg,
436 int RegType, int scratchReg = -1) const;
438 void cpValue2Value(Value *Src, Value *Dest,
439 std::vector<MachineInstr*>& mvec) const;
441 // To see whether a register is a volatile (i.e., whehter it must be
442 // preserved acorss calls)
444 inline bool isRegVolatile(int RegClassID, int Reg) const {
445 return MachineRegClassArr[RegClassID]->isRegVolatile(Reg);
448 // Get the register type for a register identified different ways.
449 int getRegType(const Type* type) const;
450 int getRegType(const LiveRange *LR) const;
451 int getRegType(int unifiedRegNum) const;
453 virtual unsigned getFramePointer() const;
454 virtual unsigned getStackPointer() const;
456 // This method inserts the caller saving code for call instructions
458 void insertCallerSavingCode(std::vector<MachineInstr*>& instrnsBefore,
459 std::vector<MachineInstr*>& instrnsAfter,
461 const BasicBlock *BB, PhyRegAlloc &PRA ) const;
467 //---------------------------------------------------------------------------
468 // class UltraSparcSchedInfo
471 // Interface to instruction scheduling information for UltraSPARC.
472 // The parameter values above are based on UltraSPARC IIi.
473 //---------------------------------------------------------------------------
476 class UltraSparcSchedInfo: public TargetSchedInfo {
478 UltraSparcSchedInfo(const TargetMachine &tgt);
480 virtual void initializeResources();
484 //---------------------------------------------------------------------------
485 // class UltraSparcFrameInfo
488 // Interface to stack frame layout info for the UltraSPARC.
489 // Starting offsets for each area of the stack frame are aligned at
490 // a multiple of getStackFrameSizeAlignment().
491 //---------------------------------------------------------------------------
493 class UltraSparcFrameInfo: public TargetFrameInfo {
494 const TargetMachine ⌖
496 UltraSparcFrameInfo(const TargetMachine &TM)
497 : TargetFrameInfo(StackGrowsDown, StackFrameSizeAlignment, 0), target(TM) {}
500 // These methods provide constant parameters of the frame layout.
502 int getStackFrameSizeAlignment() const { return StackFrameSizeAlignment;}
503 int getMinStackFrameSize() const { return MinStackFrameSize; }
504 int getNumFixedOutgoingArgs() const { return NumFixedOutgoingArgs; }
505 int getSizeOfEachArgOnStack() const { return SizeOfEachArgOnStack; }
506 bool argsOnStackHaveFixedSize() const { return true; }
508 // This method adjusts a stack offset to meet alignment rules of target.
509 // The fixed OFFSET (0x7ff) must be subtracted and the result aligned.
510 virtual int adjustAlignment (int unalignedOffset,
512 unsigned int align) const {
513 return unalignedOffset + (growUp? +1:-1)*((unalignedOffset-OFFSET) % align);
516 // These methods compute offsets using the frame contents for a
517 // particular function. The frame contents are obtained from the
518 // MachineCodeInfoForMethod object for the given function.
520 int getFirstIncomingArgOffset (MachineFunction& mcInfo,
523 growUp = true; // arguments area grows upwards
524 return FirstIncomingArgOffsetFromFP;
526 int getFirstOutgoingArgOffset (MachineFunction& mcInfo,
529 growUp = true; // arguments area grows upwards
530 return FirstOutgoingArgOffsetFromSP;
532 int getFirstOptionalOutgoingArgOffset(MachineFunction& mcInfo,
535 growUp = true; // arguments area grows upwards
536 return FirstOptionalOutgoingArgOffsetFromSP;
539 int getFirstAutomaticVarOffset (MachineFunction& mcInfo,
541 int getRegSpillAreaOffset (MachineFunction& mcInfo,
543 int getTmpAreaOffset (MachineFunction& mcInfo,
545 int getDynamicAreaOffset (MachineFunction& mcInfo,
549 // These methods specify the base register used for each stack area
550 // (generally FP or SP)
552 virtual int getIncomingArgBaseRegNum() const {
553 return (int) target.getRegInfo().getFramePointer();
555 virtual int getOutgoingArgBaseRegNum() const {
556 return (int) target.getRegInfo().getStackPointer();
558 virtual int getOptionalOutgoingArgBaseRegNum() const {
559 return (int) target.getRegInfo().getStackPointer();
561 virtual int getAutomaticVarBaseRegNum() const {
562 return (int) target.getRegInfo().getFramePointer();
564 virtual int getRegSpillAreaBaseRegNum() const {
565 return (int) target.getRegInfo().getFramePointer();
567 virtual int getDynamicAreaBaseRegNum() const {
568 return (int) target.getRegInfo().getStackPointer();
571 virtual int getIncomingArgOffset(MachineFunction& mcInfo,
572 unsigned argNum) const {
573 assert(argsOnStackHaveFixedSize());
575 unsigned relativeOffset = argNum * getSizeOfEachArgOnStack();
576 bool growUp; // do args grow up or down
577 int firstArg = getFirstIncomingArgOffset(mcInfo, growUp);
578 return growUp ? firstArg + relativeOffset : firstArg - relativeOffset;
581 virtual int getOutgoingArgOffset(MachineFunction& mcInfo,
582 unsigned argNum) const {
583 assert(argsOnStackHaveFixedSize());
584 //assert(((int) argNum - this->getNumFixedOutgoingArgs())
585 // <= (int) mcInfo.getInfo()->getMaxOptionalNumArgs());
587 unsigned relativeOffset = argNum * getSizeOfEachArgOnStack();
588 bool growUp; // do args grow up or down
589 int firstArg = getFirstOutgoingArgOffset(mcInfo, growUp);
590 return growUp ? firstArg + relativeOffset : firstArg - relativeOffset;
594 /*----------------------------------------------------------------------
595 This diagram shows the stack frame layout used by llc on Sparc V9.
596 Note that only the location of automatic variables, spill area,
597 temporary storage, and dynamically allocated stack area are chosen
598 by us. The rest conform to the Sparc V9 ABI.
599 All stack addresses are offset by OFFSET = 0x7ff (2047).
601 Alignment assumptions and other invariants:
602 (1) %sp+OFFSET and %fp+OFFSET are always aligned on 16-byte boundary
603 (2) Variables in automatic, spill, temporary, or dynamic regions
604 are aligned according to their size as in all memory accesses.
605 (3) Everything below the dynamically allocated stack area is only used
606 during a call to another function, so it is never needed when
607 the current function is active. This is why space can be allocated
608 dynamically by incrementing %sp any time within the function.
613 %fp+OFFSET+176 Optional extra incoming arguments# 1..N
614 %fp+OFFSET+168 Incoming argument #6
616 %fp+OFFSET+128 Incoming argument #1
618 ---%fp+OFFSET-0--------Bottom of caller's stack frame--------------------
619 %fp+OFFSET-8 Automatic variables <-- ****TOP OF STACK FRAME****
624 %sp+OFFSET+176+8N Bottom of dynamically allocated stack area
625 %sp+OFFSET+168+8N Optional extra outgoing argument# N
627 %sp+OFFSET+176 Optional extra outgoing argument# 1
628 %sp+OFFSET+168 Outgoing argument #6
630 %sp+OFFSET+128 Outgoing argument #1
631 %sp+OFFSET+120 Save area for %i7
633 %sp+OFFSET+0 Save area for %l0 <-- ****BOTTOM OF STACK FRAME****
635 *----------------------------------------------------------------------*/
637 // All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
638 static const int OFFSET = (int) 0x7ff;
639 static const int StackFrameSizeAlignment = 16;
640 static const int MinStackFrameSize = 176;
641 static const int NumFixedOutgoingArgs = 6;
642 static const int SizeOfEachArgOnStack = 8;
643 static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
644 static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
645 static const int StaticAreaOffsetFromFP = 0 + OFFSET;
646 static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
647 static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
651 //---------------------------------------------------------------------------
652 // class UltraSparcCacheInfo
655 // Interface to cache parameters for the UltraSPARC.
656 // Just use defaults for now.
657 //---------------------------------------------------------------------------
659 struct UltraSparcCacheInfo: public TargetCacheInfo {
660 UltraSparcCacheInfo(const TargetMachine &T) : TargetCacheInfo(T) {}
664 //---------------------------------------------------------------------------
665 // class UltraSparcOptInfo
668 // Interface to machine-level optimization routines for the UltraSPARC.
669 //---------------------------------------------------------------------------
671 struct UltraSparcOptInfo: public TargetOptInfo {
672 UltraSparcOptInfo(const TargetMachine &T) : TargetOptInfo(T) {}
674 virtual bool IsUselessCopy (const MachineInstr* MI) const;
677 /// createAddRegNumToValuesPass - this pass adds unsigned register numbers to
678 /// instructions, since that's not done by the Sparc InstSelector, but that's
679 /// how the target-independent register allocator in the JIT likes to see
680 /// instructions. This pass enables the usage of the JIT register allocator(s).
681 Pass *createAddRegNumToValuesPass();
683 //---------------------------------------------------------------------------
684 // class UltraSparcMachine
687 // Primary interface to machine description for the UltraSPARC.
688 // Primarily just initializes machine-dependent parameters in
689 // class TargetMachine, and creates machine-dependent subclasses
690 // for classes such as InstrInfo, SchedInfo and RegInfo.
691 //---------------------------------------------------------------------------
693 class UltraSparc : public TargetMachine {
694 UltraSparcInstrInfo instrInfo;
695 UltraSparcSchedInfo schedInfo;
696 UltraSparcRegInfo regInfo;
697 UltraSparcFrameInfo frameInfo;
698 UltraSparcCacheInfo cacheInfo;
699 UltraSparcOptInfo optInfo;
703 virtual const TargetInstrInfo &getInstrInfo() const { return instrInfo; }
704 virtual const TargetSchedInfo &getSchedInfo() const { return schedInfo; }
705 virtual const TargetRegInfo &getRegInfo() const { return regInfo; }
706 virtual const TargetFrameInfo &getFrameInfo() const { return frameInfo; }
707 virtual const TargetCacheInfo &getCacheInfo() const { return cacheInfo; }
708 virtual const TargetOptInfo &getOptInfo() const { return optInfo; }
710 virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
711 virtual bool addPassesToJITCompile(PassManager &PM);
712 virtual bool addPassesToEmitMachineCode(PassManager &PM,
713 MachineCodeEmitter &MCE);
715 // getPrologEpilogInsertionPass - Inserts prolog/epilog code.
716 Pass* getPrologEpilogInsertionPass();
718 // getFunctionAsmPrinterPass - Writes out machine code for a single function
719 Pass* getFunctionAsmPrinterPass(std::ostream &Out);
721 // getModuleAsmPrinterPass - Writes generated machine code to assembly file.
722 Pass* getModuleAsmPrinterPass(std::ostream &Out);
724 // getEmitBytecodeToAsmPass - Emits final LLVM bytecode to assembly file.
725 Pass* getEmitBytecodeToAsmPass(std::ostream &Out);
728 int64_t GetConstantValueAsSignedInt(const Value *V, bool &isValidConstant);