1 //===-- SparcInternals.h ----------------------------------------*- C++ -*-===//
3 // This file defines stuff that is to be private to the Sparc backend, but is
4 // shared among different portions of the backend.
6 //===----------------------------------------------------------------------===//
8 #ifndef SPARC_INTERNALS_H
9 #define SPARC_INTERNALS_H
11 #include "llvm/Target/TargetMachine.h"
12 #include "llvm/Target/TargetSchedInfo.h"
13 #include "llvm/Target/TargetFrameInfo.h"
14 #include "llvm/Target/TargetCacheInfo.h"
15 #include "llvm/Target/TargetRegInfo.h"
16 #include "llvm/Target/TargetOptInfo.h"
17 #include "llvm/Type.h"
18 #include <sys/types.h>
25 enum SparcInstrSchedClass {
26 SPARC_NONE, /* Instructions with no scheduling restrictions */
27 SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
28 SPARC_IEU0, /* Integer class IEU0 */
29 SPARC_IEU1, /* Integer class IEU1 */
30 SPARC_FPM, /* FP Multiply or Divide instructions */
31 SPARC_FPA, /* All other FP instructions */
32 SPARC_CTI, /* Control-transfer instructions */
33 SPARC_LD, /* Load instructions */
34 SPARC_ST, /* Store instructions */
35 SPARC_SINGLE, /* Instructions that must issue by themselves */
37 SPARC_INV, /* This should stay at the end for the next value */
38 SPARC_NUM_SCHED_CLASSES = SPARC_INV
42 //---------------------------------------------------------------------------
43 // enum SparcMachineOpCode.
44 // const MachineInstrDescriptor SparcMachineInstrDesc[]
47 // Description of UltraSparc machine instructions.
49 //---------------------------------------------------------------------------
51 enum SparcMachineOpCode {
52 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
53 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
55 #include "SparcInstr.def"
57 // End-of-array marker
59 NUM_REAL_OPCODES = PHI, // number of valid opcodes
60 NUM_TOTAL_OPCODES = INVALID_OPCODE
64 // Array of machine instruction descriptions...
65 extern const MachineInstrDescriptor SparcMachineInstrDesc[];
68 //---------------------------------------------------------------------------
69 // class UltraSparcInstrInfo
72 // Information about individual instructions.
73 // Most information is stored in the SparcMachineInstrDesc array above.
74 // Other information is computed on demand, and most such functions
75 // default to member functions in base class MachineInstrInfo.
76 //---------------------------------------------------------------------------
78 struct UltraSparcInstrInfo : public MachineInstrInfo {
79 UltraSparcInstrInfo();
82 // All immediate constants are in position 1 except the
83 // store instructions and SETxx.
85 virtual int getImmedConstantPos(MachineOpCode opCode) const {
87 if (this->maxImmedConstant(opCode, ignore) != 0)
89 assert(! this->isStore((MachineOpCode) STB - 1)); // 1st store opcode
90 assert(! this->isStore((MachineOpCode) STXFSR+1));// last store opcode
91 if (opCode==SETSW || opCode==SETUW || opCode==SETX || opCode==SETHI)
93 if (opCode >= STB && opCode <= STXFSR)
101 virtual bool hasResultInterlock (MachineOpCode opCode) const
103 // All UltraSPARC instructions have interlocks (note that delay slots
104 // are not considered here).
105 // However, instructions that use the result of an FCMP produce a
106 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
107 // Force the compiler to insert a software interlock (i.e., gap of
108 // 2 other groups, including NOPs if necessary).
109 return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
112 //-------------------------------------------------------------------------
113 // Queries about representation of LLVM quantities (e.g., constants)
114 //-------------------------------------------------------------------------
116 virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
117 const Instruction* I) const;
119 //-------------------------------------------------------------------------
120 // Code generation support for creating individual machine instructions
121 //-------------------------------------------------------------------------
123 // Get certain common op codes for the current target. This and all the
124 // Create* methods below should be moved to a machine code generation class
126 virtual MachineOpCode getNOPOpCode() const { return NOP; }
128 // Create an instruction sequence to put the constant `val' into
129 // the virtual register `dest'. `val' may be a Constant or a
130 // GlobalValue, viz., the constant address of a global variable or function.
131 // The generated instructions are returned in `mvec'.
132 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
133 // Any stack space required is allocated via mcff.
135 virtual void CreateCodeToLoadConst(const TargetMachine& target,
139 std::vector<MachineInstr*>& mvec,
140 MachineCodeForInstruction& mcfi) const;
142 // Create an instruction sequence to copy an integer value `val'
143 // to a floating point value `dest' by copying to memory and back.
144 // val must be an integral type. dest must be a Float or Double.
145 // The generated instructions are returned in `mvec'.
146 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
147 // Any stack space required is allocated via mcff.
149 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
153 std::vector<MachineInstr*>& mvec,
154 MachineCodeForInstruction& mcfi) const;
156 // Similarly, create an instruction sequence to copy an FP value
157 // `val' to an integer value `dest' by copying to memory and back.
158 // The generated instructions are returned in `mvec'.
159 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
160 // Any stack space required is allocated via mcff.
162 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
166 std::vector<MachineInstr*>& mvec,
167 MachineCodeForInstruction& mcfi) const;
169 // Create instruction(s) to copy src to dest, for arbitrary types
170 // The generated instructions are returned in `mvec'.
171 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
172 // Any stack space required is allocated via mcff.
174 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
178 std::vector<MachineInstr*>& mvec,
179 MachineCodeForInstruction& mcfi) const;
181 // Create instruction sequence to produce a sign-extended register value
182 // from an arbitrary sized value (sized in bits, not bytes).
183 // The generated instructions are appended to `mvec'.
184 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
185 // Any stack space required is allocated via mcff.
187 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
191 unsigned int numLowBits,
192 std::vector<MachineInstr*>& mvec,
193 MachineCodeForInstruction& mcfi) const;
195 // Create instruction sequence to produce a zero-extended register value
196 // from an arbitrary sized value (sized in bits, not bytes).
197 // The generated instructions are appended to `mvec'.
198 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
199 // Any stack space required is allocated via mcff.
201 virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
205 unsigned int numLowBits,
206 std::vector<MachineInstr*>& mvec,
207 MachineCodeForInstruction& mcfi) const;
211 //----------------------------------------------------------------------------
212 // class UltraSparcRegInfo
214 // This class implements the virtual class TargetRegInfo for Sparc.
216 //----------------------------------------------------------------------------
218 class UltraSparcRegInfo : public TargetRegInfo {
219 // The actual register classes in the Sparc
222 IntRegClassID, // Integer
223 FloatRegClassID, // Float (both single/double)
224 IntCCRegClassID, // Int Condition Code
225 FloatCCRegClassID // Float Condition code
229 // Type of registers available in Sparc. There can be several reg types
230 // in the same class. For instace, the float reg class has Single/Double
241 // **** WARNING: If the above enum order is changed, also modify
242 // getRegisterClassOfValue method below since it assumes this particular
243 // order for efficiency.
246 // Number of registers used for passing int args (usually 6: %o0 - %o5)
248 unsigned const NumOfIntArgRegs;
250 // Number of registers used for passing float args (usually 32: %f0 - %f31)
252 unsigned const NumOfFloatArgRegs;
254 // An out of bound register number that can be used to initialize register
255 // numbers. Useful for error detection.
257 int const InvalidRegNum;
260 // ======================== Private Methods =============================
262 // The following methods are used to color special live ranges (e.g.
263 // function args and return values etc.) with specific hardware registers
264 // as required. See SparcRegInfo.cpp for the implementation.
266 void suggestReg4RetAddr(MachineInstr *RetMI,
267 LiveRangeInfo &LRI) const;
269 void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI) const;
271 void InitializeOutgoingArg(MachineInstr* CallMI, AddedInstrns *CallAI,
272 PhyRegAlloc &PRA, LiveRange* LR,
273 unsigned regType, unsigned RegClassID,
274 int UniArgReg, unsigned int argNo,
275 std::vector<MachineInstr *>& AddedInstrnsBefore)
278 // The following 4 methods are used to find the RegType (see enum above)
279 // for a reg class and a given primitive type, a LiveRange, a Value,
280 // or a particular machine register.
281 // The fifth function gives the reg class of the given RegType.
283 int getRegType(unsigned regClassID, const Type* type) const;
284 int getRegType(const LiveRange *LR) const;
285 int getRegType(const Value *Val) const;
286 int getRegType(int unifiedRegNum) const;
288 // Used to generate a copy instruction based on the register class of
291 MachineInstr *cpValue2RegMI(Value *Val, unsigned DestReg,
295 // The following 2 methods are used to order the instructions addeed by
296 // the register allocator in association with function calling. See
297 // SparcRegInfo.cpp for more details
299 void moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
300 MachineInstr *UnordInst,
301 PhyRegAlloc &PRA) const;
303 void OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
304 std::vector<MachineInstr *> &OrdVec,
305 PhyRegAlloc &PRA) const;
308 // Compute which register can be used for an argument, if any
310 int regNumForIntArg(bool inCallee, bool isVarArgsCall,
311 unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
312 unsigned& regClassId) const;
314 int regNumForFPArg(unsigned RegType, bool inCallee, bool isVarArgsCall,
315 unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
316 unsigned& regClassId) const;
319 UltraSparcRegInfo(const UltraSparc &tgt);
321 // To find the register class used for a specified Type
323 unsigned getRegClassIDOfType(const Type *type,
324 bool isCCReg = false) const;
326 // To find the register class of a Value
328 inline unsigned getRegClassIDOfValue(const Value *Val,
329 bool isCCReg = false) const {
330 return getRegClassIDOfType(Val->getType(), isCCReg);
333 // To find the register class to which a specified register belongs
335 unsigned getRegClassIDOfReg(int unifiedRegNum) const;
336 unsigned getRegClassIDOfRegType(int regType) const;
338 // getZeroRegNum - returns the register that contains always zero this is the
339 // unified register number
341 virtual int getZeroRegNum() const;
343 // getCallAddressReg - returns the reg used for pushing the address when a
344 // function is called. This can be used for other purposes between calls
346 unsigned getCallAddressReg() const;
348 // Returns the register containing the return address.
349 // It should be made sure that this register contains the return
350 // value when a return instruction is reached.
352 unsigned getReturnAddressReg() const;
354 // Number of registers used for passing int args (usually 6: %o0 - %o5)
355 // and float args (usually 32: %f0 - %f31)
357 unsigned const GetNumOfIntArgRegs() const { return NumOfIntArgRegs; }
358 unsigned const GetNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
360 // The following methods are used to color special live ranges (e.g.
361 // function args and return values etc.) with specific hardware registers
362 // as required. See SparcRegInfo.cpp for the implementation for Sparc.
364 void suggestRegs4MethodArgs(const Function *Meth,
365 LiveRangeInfo& LRI) const;
367 void suggestRegs4CallArgs(MachineInstr *CallMI,
368 LiveRangeInfo& LRI) const;
370 void suggestReg4RetValue(MachineInstr *RetMI,
371 LiveRangeInfo& LRI) const;
373 void colorMethodArgs(const Function *Meth, LiveRangeInfo &LRI,
374 AddedInstrns *FirstAI) const;
376 void colorCallArgs(MachineInstr *CallMI, LiveRangeInfo &LRI,
377 AddedInstrns *CallAI, PhyRegAlloc &PRA,
378 const BasicBlock *BB) const;
380 void colorRetValue(MachineInstr *RetI, LiveRangeInfo& LRI,
381 AddedInstrns *RetAI) const;
384 // method used for printing a register for debugging purposes
386 static void printReg(const LiveRange *LR);
388 // Each register class has a seperate space for register IDs. To convert
389 // a regId in a register class to a common Id, or vice versa,
390 // we use the folloing methods.
392 // This method provides a unique number for each register
393 inline int getUnifiedRegNum(unsigned regClassID, int reg) const {
395 if (regClassID == IntRegClassID) {
396 assert(reg < 32 && "Invalid reg. number");
399 else if (regClassID == FloatRegClassID) {
400 assert(reg < 64 && "Invalid reg. number");
401 return reg + 32; // we have 32 int regs
403 else if (regClassID == FloatCCRegClassID) {
404 assert(reg < 4 && "Invalid reg. number");
405 return reg + 32 + 64; // 32 int, 64 float
407 else if (regClassID == IntCCRegClassID ) {
408 assert(reg == 0 && "Invalid reg. number");
409 return reg + 4+ 32 + 64; // only one int CC reg
411 else if (reg==InvalidRegNum) {
412 return InvalidRegNum;
415 assert(0 && "Invalid register class");
419 // This method converts the unified number to the number in its class,
420 // and returns the class ID in regClassID.
421 inline int getClassRegNum(int ureg, unsigned& regClassID) const {
422 if (ureg < 32) { regClassID = IntRegClassID; return ureg; }
423 else if (ureg < 32+64) { regClassID = FloatRegClassID; return ureg-32; }
424 else if (ureg < 4 +96) { regClassID = FloatCCRegClassID; return ureg-96; }
425 else if (ureg < 1 +100) { regClassID = IntCCRegClassID; return ureg-100;}
426 else if (ureg == InvalidRegNum) { return InvalidRegNum; }
427 else { assert(0 && "Invalid unified register number"); }
431 // Returns the assembly-language name of the specified machine register.
433 virtual const char * const getUnifiedRegName(int reg) const;
436 // returns the # of bytes of stack space allocated for each register
437 // type. For Sparc, currently we allocate 8 bytes on stack for all
438 // register types. We can optimize this later if necessary to save stack
439 // space (However, should make sure that stack alignment is correct)
441 inline int getSpilledRegSize(int RegType) const {
446 // To obtain the return value and the indirect call address (if any)
447 // contained in a CALL machine instruction
449 const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
450 const Value * getCallInstIndirectAddrVal(const MachineInstr *CallMI) const;
452 // The following methods are used to generate "copy" machine instructions
453 // for an architecture.
455 // The function regTypeNeedsScratchReg() can be used to check whether a
456 // scratch register is needed to copy a register of type `regType' to
457 // or from memory. If so, such a scratch register can be provided by
458 // the caller (e.g., if it knows which regsiters are free); otherwise
459 // an arbitrary one will be chosen and spilled by the copy instructions.
461 bool regTypeNeedsScratchReg(int RegType,
462 int& scratchRegClassId) const;
464 void cpReg2RegMI(std::vector<MachineInstr*>& mvec,
465 unsigned SrcReg, unsigned DestReg,
468 void cpReg2MemMI(std::vector<MachineInstr*>& mvec,
469 unsigned SrcReg, unsigned DestPtrReg,
470 int Offset, int RegType, int scratchReg = -1) const;
472 void cpMem2RegMI(std::vector<MachineInstr*>& mvec,
473 unsigned SrcPtrReg, int Offset, unsigned DestReg,
474 int RegType, int scratchReg = -1) const;
476 void cpValue2Value(Value *Src, Value *Dest,
477 std::vector<MachineInstr*>& mvec) const;
479 // To see whether a register is a volatile (i.e., whehter it must be
480 // preserved acorss calls)
482 inline bool isRegVolatile(int RegClassID, int Reg) const {
483 return MachineRegClassArr[RegClassID]->isRegVolatile(Reg);
487 virtual unsigned getFramePointer() const;
488 virtual unsigned getStackPointer() const;
490 virtual int getInvalidRegNum() const {
491 return InvalidRegNum;
494 // This method inserts the caller saving code for call instructions
496 void insertCallerSavingCode(std::vector<MachineInstr*>& instrnsBefore,
497 std::vector<MachineInstr*>& instrnsAfter,
499 const BasicBlock *BB, PhyRegAlloc &PRA ) const;
505 //---------------------------------------------------------------------------
506 // class UltraSparcSchedInfo
509 // Interface to instruction scheduling information for UltraSPARC.
510 // The parameter values above are based on UltraSPARC IIi.
511 //---------------------------------------------------------------------------
514 class UltraSparcSchedInfo: public TargetSchedInfo {
516 UltraSparcSchedInfo(const TargetMachine &tgt);
518 virtual void initializeResources();
522 //---------------------------------------------------------------------------
523 // class UltraSparcFrameInfo
526 // Interface to stack frame layout info for the UltraSPARC.
527 // Starting offsets for each area of the stack frame are aligned at
528 // a multiple of getStackFrameSizeAlignment().
529 //---------------------------------------------------------------------------
531 class UltraSparcFrameInfo: public TargetFrameInfo {
532 const TargetMachine ⌖
534 UltraSparcFrameInfo(const TargetMachine &TM)
535 : TargetFrameInfo(StackGrowsDown, StackFrameSizeAlignment, 0), target(TM) {}
538 // These methods provide constant parameters of the frame layout.
540 int getStackFrameSizeAlignment() const { return StackFrameSizeAlignment;}
541 int getMinStackFrameSize() const { return MinStackFrameSize; }
542 int getNumFixedOutgoingArgs() const { return NumFixedOutgoingArgs; }
543 int getSizeOfEachArgOnStack() const { return SizeOfEachArgOnStack; }
544 bool argsOnStackHaveFixedSize() const { return true; }
546 // This method adjusts a stack offset to meet alignment rules of target.
547 // The fixed OFFSET (0x7ff) must be subtracted and the result aligned.
548 virtual int adjustAlignment (int unalignedOffset,
550 unsigned int align) const {
551 return unalignedOffset + (growUp? +1:-1)*((unalignedOffset-OFFSET) % align);
554 // These methods compute offsets using the frame contents for a
555 // particular function. The frame contents are obtained from the
556 // MachineCodeInfoForMethod object for the given function.
558 int getFirstIncomingArgOffset (MachineFunction& mcInfo,
561 growUp = true; // arguments area grows upwards
562 return FirstIncomingArgOffsetFromFP;
564 int getFirstOutgoingArgOffset (MachineFunction& mcInfo,
567 growUp = true; // arguments area grows upwards
568 return FirstOutgoingArgOffsetFromSP;
570 int getFirstOptionalOutgoingArgOffset(MachineFunction& mcInfo,
573 growUp = true; // arguments area grows upwards
574 return FirstOptionalOutgoingArgOffsetFromSP;
577 int getFirstAutomaticVarOffset (MachineFunction& mcInfo,
579 int getRegSpillAreaOffset (MachineFunction& mcInfo,
581 int getTmpAreaOffset (MachineFunction& mcInfo,
583 int getDynamicAreaOffset (MachineFunction& mcInfo,
587 // These methods specify the base register used for each stack area
588 // (generally FP or SP)
590 virtual int getIncomingArgBaseRegNum() const {
591 return (int) target.getRegInfo().getFramePointer();
593 virtual int getOutgoingArgBaseRegNum() const {
594 return (int) target.getRegInfo().getStackPointer();
596 virtual int getOptionalOutgoingArgBaseRegNum() const {
597 return (int) target.getRegInfo().getStackPointer();
599 virtual int getAutomaticVarBaseRegNum() const {
600 return (int) target.getRegInfo().getFramePointer();
602 virtual int getRegSpillAreaBaseRegNum() const {
603 return (int) target.getRegInfo().getFramePointer();
605 virtual int getDynamicAreaBaseRegNum() const {
606 return (int) target.getRegInfo().getStackPointer();
609 virtual int getIncomingArgOffset(MachineFunction& mcInfo,
610 unsigned argNum) const {
611 assert(argsOnStackHaveFixedSize());
613 unsigned relativeOffset = argNum * getSizeOfEachArgOnStack();
614 bool growUp; // do args grow up or down
615 int firstArg = getFirstIncomingArgOffset(mcInfo, growUp);
616 return growUp ? firstArg + relativeOffset : firstArg - relativeOffset;
619 virtual int getOutgoingArgOffset(MachineFunction& mcInfo,
620 unsigned argNum) const {
621 assert(argsOnStackHaveFixedSize());
622 //assert(((int) argNum - this->getNumFixedOutgoingArgs())
623 // <= (int) mcInfo.getInfo()->getMaxOptionalNumArgs());
625 unsigned relativeOffset = argNum * getSizeOfEachArgOnStack();
626 bool growUp; // do args grow up or down
627 int firstArg = getFirstOutgoingArgOffset(mcInfo, growUp);
628 return growUp ? firstArg + relativeOffset : firstArg - relativeOffset;
632 /*----------------------------------------------------------------------
633 This diagram shows the stack frame layout used by llc on Sparc V9.
634 Note that only the location of automatic variables, spill area,
635 temporary storage, and dynamically allocated stack area are chosen
636 by us. The rest conform to the Sparc V9 ABI.
637 All stack addresses are offset by OFFSET = 0x7ff (2047).
639 Alignment assumptions and other invariants:
640 (1) %sp+OFFSET and %fp+OFFSET are always aligned on 16-byte boundary
641 (2) Variables in automatic, spill, temporary, or dynamic regions
642 are aligned according to their size as in all memory accesses.
643 (3) Everything below the dynamically allocated stack area is only used
644 during a call to another function, so it is never needed when
645 the current function is active. This is why space can be allocated
646 dynamically by incrementing %sp any time within the function.
651 %fp+OFFSET+176 Optional extra incoming arguments# 1..N
652 %fp+OFFSET+168 Incoming argument #6
654 %fp+OFFSET+128 Incoming argument #1
656 ---%fp+OFFSET-0--------Bottom of caller's stack frame--------------------
657 %fp+OFFSET-8 Automatic variables <-- ****TOP OF STACK FRAME****
662 %sp+OFFSET+176+8N Bottom of dynamically allocated stack area
663 %sp+OFFSET+168+8N Optional extra outgoing argument# N
665 %sp+OFFSET+176 Optional extra outgoing argument# 1
666 %sp+OFFSET+168 Outgoing argument #6
668 %sp+OFFSET+128 Outgoing argument #1
669 %sp+OFFSET+120 Save area for %i7
671 %sp+OFFSET+0 Save area for %l0 <-- ****BOTTOM OF STACK FRAME****
673 *----------------------------------------------------------------------*/
675 // All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
676 static const int OFFSET = (int) 0x7ff;
677 static const int StackFrameSizeAlignment = 16;
678 static const int MinStackFrameSize = 176;
679 static const int NumFixedOutgoingArgs = 6;
680 static const int SizeOfEachArgOnStack = 8;
681 static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
682 static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
683 static const int StaticAreaOffsetFromFP = 0 + OFFSET;
684 static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
685 static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
689 //---------------------------------------------------------------------------
690 // class UltraSparcCacheInfo
693 // Interface to cache parameters for the UltraSPARC.
694 // Just use defaults for now.
695 //---------------------------------------------------------------------------
697 struct UltraSparcCacheInfo: public TargetCacheInfo {
698 UltraSparcCacheInfo(const TargetMachine &T) : TargetCacheInfo(T) {}
702 //---------------------------------------------------------------------------
703 // class UltraSparcOptInfo
706 // Interface to machine-level optimization routines for the UltraSPARC.
707 //---------------------------------------------------------------------------
709 struct UltraSparcOptInfo: public TargetOptInfo {
710 UltraSparcOptInfo(const TargetMachine &T) : TargetOptInfo(T) {}
712 virtual bool IsUselessCopy (const MachineInstr* MI) const;
716 //---------------------------------------------------------------------------
717 // class UltraSparcMachine
720 // Primary interface to machine description for the UltraSPARC.
721 // Primarily just initializes machine-dependent parameters in
722 // class TargetMachine, and creates machine-dependent subclasses
723 // for classes such as InstrInfo, SchedInfo and RegInfo.
724 //---------------------------------------------------------------------------
726 class UltraSparc : public TargetMachine {
727 UltraSparcInstrInfo instrInfo;
728 UltraSparcSchedInfo schedInfo;
729 UltraSparcRegInfo regInfo;
730 UltraSparcFrameInfo frameInfo;
731 UltraSparcCacheInfo cacheInfo;
732 UltraSparcOptInfo optInfo;
736 virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
737 virtual const TargetSchedInfo &getSchedInfo() const { return schedInfo; }
738 virtual const TargetRegInfo &getRegInfo() const { return regInfo; }
739 virtual const TargetFrameInfo &getFrameInfo() const { return frameInfo; }
740 virtual const TargetCacheInfo &getCacheInfo() const { return cacheInfo; }
741 virtual const TargetOptInfo &getOptInfo() const { return optInfo; }
743 virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
745 // getPrologEpilogInsertionPass - Inserts prolog/epilog code.
746 Pass* getPrologEpilogInsertionPass();
748 // getFunctionAsmPrinterPass - Writes out machine code for a single function
749 Pass* getFunctionAsmPrinterPass(std::ostream &Out);
751 // getModuleAsmPrinterPass - Writes generated machine code to assembly file.
752 Pass* getModuleAsmPrinterPass(std::ostream &Out);
754 // getEmitBytecodeToAsmPass - Emits final LLVM bytecode to assembly file.
755 Pass* getEmitBytecodeToAsmPass(std::ostream &Out);