1 //===-- SparcInternals.h - Header file for Sparc backend ---------*- C++ -*--=//
3 // This file defines stuff that is to be private to the Sparc backend, but is
4 // shared among different portions of the backend.
6 //===----------------------------------------------------------------------===//
8 #ifndef SPARC_INTERNALS_H
9 #define SPARC_INTERNALS_H
12 #include "SparcRegClassInfo.h"
13 #include "llvm/Target/TargetMachine.h"
14 #include "llvm/Target/MachineInstrInfo.h"
16 #include "llvm/Target/MachineSchedInfo.h"
17 #include "llvm/CodeGen/RegClass.h"
18 #include "llvm/Type.h"
20 #include <sys/types.h>
24 // OpCodeMask definitions for the Sparc V9
26 const OpCodeMask Immed = 0x00002000; // immed or reg operand?
27 const OpCodeMask Annul = 0x20000000; // annul delay instr?
28 const OpCodeMask PredictTaken = 0x00080000; // predict branch taken?
31 enum SparcInstrSchedClass {
32 SPARC_NONE, /* Instructions with no scheduling restrictions */
33 SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
34 SPARC_IEU0, /* Integer class IEU0 */
35 SPARC_IEU1, /* Integer class IEU1 */
36 SPARC_FPM, /* FP Multiply or Divide instructions */
37 SPARC_FPA, /* All other FP instructions */
38 SPARC_CTI, /* Control-transfer instructions */
39 SPARC_LD, /* Load instructions */
40 SPARC_ST, /* Store instructions */
41 SPARC_SINGLE, /* Instructions that must issue by themselves */
43 SPARC_INV, /* This should stay at the end for the next value */
44 SPARC_NUM_SCHED_CLASSES = SPARC_INV
48 //---------------------------------------------------------------------------
49 // enum SparcMachineOpCode.
50 // const MachineInstrDescriptor SparcMachineInstrDesc[]
53 // Description of UltraSparc machine instructions.
55 //---------------------------------------------------------------------------
57 enum SparcMachineOpCode {
58 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
59 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
61 #include "SparcInstr.def"
63 // End-of-array marker
65 NUM_REAL_OPCODES = PHI, // number of valid opcodes
66 NUM_TOTAL_OPCODES = INVALID_OPCODE
70 // Array of machine instruction descriptions...
71 extern const MachineInstrDescriptor SparcMachineInstrDesc[];
74 //---------------------------------------------------------------------------
75 // class UltraSparcInstrInfo
78 // Information about individual instructions.
79 // Most information is stored in the SparcMachineInstrDesc array above.
80 // Other information is computed on demand, and most such functions
81 // default to member functions in base class MachineInstrInfo.
82 //---------------------------------------------------------------------------
84 class UltraSparcInstrInfo : public MachineInstrInfo {
86 /*ctor*/ UltraSparcInstrInfo();
88 virtual bool hasResultInterlock (MachineOpCode opCode) const
90 // All UltraSPARC instructions have interlocks (note that delay slots
91 // are not considered here).
92 // However, instructions that use the result of an FCMP produce a
93 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
94 // Force the compiler to insert a software interlock (i.e., gap of
95 // 2 other groups, including NOPs if necessary).
96 return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
99 //-------------------------------------------------------------------------
100 // Code generation support for creating individual machine instructions
101 //-------------------------------------------------------------------------
103 // Create an instruction sequence to put the constant `val' into
104 // the virtual register `dest'. The generated instructions are
105 // returned in `minstrVec'. Any temporary registers (TmpInstruction)
106 // created are returned in `tempVec'.
108 virtual void CreateCodeToLoadConst(Value* val,
110 vector<MachineInstr*>& minstrVec,
111 vector<TmpInstruction*>& tempVec) const;
118 //----------------------------------------------------------------------------
119 // class UltraSparcRegInfo
121 //----------------------------------------------------------------------------
129 class UltraSparcRegInfo : public MachineRegInfo
134 // The actual register classes in the Sparc
144 // Type of registers available in Sparc. There can be several reg types
145 // in the same class. For instace, the float reg class has Single/Double
155 // the size of a value (int, float, etc..) stored in the stack frame
159 // WARNING: If the above enum order must be changed, also modify
160 // getRegisterClassOfValue method below since it assumes this particular
161 // order for efficiency.
164 // reverse pointer to get info about the ultra sparc machine
165 const UltraSparc *const UltraSparcInfo;
167 // Both int and float rguments can be passed in 6 int regs -
168 // %o0 to %o5 (cannot be changed)
169 unsigned const NumOfIntArgRegs;
170 unsigned const NumOfFloatArgRegs;
171 int const InvalidRegNum;
172 int SizeOfOperandOnStack;
176 //void setCallArgColor(LiveRange *const LR, const unsigned RegNo) const;
178 void setCallOrRetArgCol(LiveRange *const LR, const unsigned RegNo,
179 const MachineInstr *MI,AddedInstrMapType &AIMap)const;
181 MachineInstr * getCopy2RegMI(const Value *SrcVal, const unsigned Reg,
182 unsigned RegClassID) const ;
185 void suggestReg4RetAddr(const MachineInstr * RetMI,
186 LiveRangeInfo& LRI) const;
188 void suggestReg4CallAddr(const MachineInstr * CallMI, LiveRangeInfo& LRI,
189 vector<RegClass *> RCList) const;
192 Value *getValue4ReturnAddr( const MachineInstr * MInst ) const ;
194 int getRegType(const LiveRange *const LR) const {
198 switch( (LR->getRegClass())->getID() ) {
200 case IntRegClassID: return IntRegType;
202 case FloatRegClassID:
203 Typ = LR->getTypeID();
204 if( Typ == Type::FloatTyID )
205 return FPSingleRegType;
206 else if( Typ == Type::DoubleTyID )
207 return FPDoubleRegType;
208 else assert(0 && "Unknown type in FloatRegClass");
210 case IntCCRegClassID: return IntCCRegType;
212 case FloatCCRegClassID: return FloatCCRegType ;
214 default: assert( 0 && "Unknown reg class ID");
220 int getRegType(const Value *const Val) const {
224 switch( getRegClassIDOfValue(Val) ) {
226 case IntRegClassID: return IntRegType;
228 case FloatRegClassID:
229 Typ = (Val->getType())->getPrimitiveID();
230 if( Typ == Type::FloatTyID )
231 return FPSingleRegType;
232 else if( Typ == Type::DoubleTyID )
233 return FPDoubleRegType;
234 else assert(0 && "Unknown type in FloatRegClass");
236 case IntCCRegClassID: return IntCCRegType;
238 case FloatCCRegClassID: return FloatCCRegType ;
240 default: assert( 0 && "Unknown reg class ID");
248 // ***TODO: See this method is necessary
250 MachineInstr * cpValue2RegMI(Value * Val, const unsigned DestReg,
251 const int RegType) const;
253 const Value *getCallInstRetAddr(const MachineInstr *CallMI) const;
254 const unsigned getCallInstNumArgs(const MachineInstr *CallMI) const;
260 UltraSparcRegInfo(const UltraSparc *const USI ) : UltraSparcInfo(USI),
262 NumOfFloatArgRegs(32),
264 SizeOfOperandOnStack(8)
266 MachineRegClassArr.push_back( new SparcIntRegClass(IntRegClassID) );
267 MachineRegClassArr.push_back( new SparcFloatRegClass(FloatRegClassID) );
268 MachineRegClassArr.push_back( new SparcIntCCRegClass(IntCCRegClassID) );
269 MachineRegClassArr.push_back( new SparcFloatCCRegClass(FloatCCRegClassID));
271 assert( SparcFloatRegOrder::StartOfNonVolatileRegs == 32 &&
272 "32 Float regs are used for float arg passing");
277 ~UltraSparcRegInfo(void) { } // empty destructor
280 inline const UltraSparc & getUltraSparcInfo() const {
281 return *UltraSparcInfo;
286 inline unsigned getRegClassIDOfValue (const Value *const Val,
287 bool isCCReg = false) const {
289 Type::PrimitiveID ty = (Val->getType())->getPrimitiveID();
293 if( (ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
294 (ty == Type::MethodTyID) || (ty == Type::PointerTyID) )
295 res = IntRegClassID; // sparc int reg (ty=0: void)
296 else if( ty <= Type::DoubleTyID)
297 res = FloatRegClassID; // sparc float reg class
299 cerr << "TypeID: " << ty << endl;
300 assert(0 && "Cannot resolve register class for type");
304 return res + 2; // corresponidng condition code regiser
309 // returns the register tha contains always zero
310 // this is the unified register number
311 inline int getZeroRegNum() const { return SparcIntRegOrder::g0; }
313 // returns the reg used for pushing the address when a method is called.
314 // This can be used for other purposes between calls
315 unsigned getCallAddressReg() const { return SparcIntRegOrder::o7; }
318 // and when we return from a method. It should be made sure that this
319 // register contains the return value when a return instruction is reached.
320 unsigned getReturnAddressReg() const { return SparcIntRegOrder::i7; }
322 void suggestRegs4MethodArgs(const Method *const Meth,
323 LiveRangeInfo& LRI) const;
325 void suggestRegs4CallArgs(const MachineInstr *const CallMI,
326 LiveRangeInfo& LRI, vector<RegClass *> RCL) const;
328 void suggestReg4RetValue(const MachineInstr *const RetMI,
329 LiveRangeInfo& LRI ) const;
332 void colorMethodArgs(const Method *const Meth, LiveRangeInfo& LRI,
333 AddedInstrns *const FirstAI) const;
335 void colorCallArgs(const MachineInstr *const CallMI, LiveRangeInfo& LRI,
336 AddedInstrns *const CallAI, PhyRegAlloc &PRA) const;
338 void colorRetValue(const MachineInstr *const RetI, LiveRangeInfo& LRI,
339 AddedInstrns *const RetAI) const;
342 // bool handleSpecialMInstr(const MachineInstr * MInst,
343 // LiveRangeInfo& LRI, vector<RegClass *> RCL) const;
346 static void printReg(const LiveRange *const LR) ;
348 // this method provides a unique number for each register
349 inline int getUnifiedRegNum(int RegClassID, int reg) const {
351 if( RegClassID == IntRegClassID && reg < 32 )
353 else if ( RegClassID == FloatRegClassID && reg < 64)
354 return reg + 32; // we have 32 int regs
355 else if( RegClassID == FloatCCRegClassID && reg < 4)
356 return reg + 32 + 64; // 32 int, 64 float
357 else if( RegClassID == IntCCRegClassID )
358 return 4+ 32 + 64; // only int cc reg
359 else if (reg==InvalidRegNum)
360 return InvalidRegNum;
362 assert(0 && "Invalid register class or reg number");
366 // given the unified register number, this gives the name
367 inline const string getUnifiedRegName(int reg) const {
369 return SparcIntRegOrder::getRegName(reg);
370 else if ( reg < (64 + 32) )
371 return SparcFloatRegOrder::getRegName( reg - 32);
372 else if( reg < (64+32+4) )
373 return SparcFloatCCRegOrder::getRegName( reg -32 - 64);
374 else if ( reg == 64+32+4)
375 return "xcc"; // only integer cc reg
377 else if (reg== InvalidRegNum) //****** TODO: Remove */
380 assert(0 && "Invalid register number");
383 inline unsigned int getRegNumInCallersWindow(int reg) {
384 if (reg == InvalidRegNum || reg >= 32)
386 return SparcIntRegOrder::getRegNumInCallersWindow(reg);
389 inline bool mustBeRemappedInCallersWindow(int reg) {
390 return (reg != InvalidRegNum && reg < 32);
393 const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
395 MachineInstr * cpReg2RegMI(const unsigned SrcReg, const unsigned DestReg,
396 const int RegType) const;
398 MachineInstr * cpReg2MemMI(const unsigned SrcReg, const unsigned DestPtrReg,
399 const int Offset, const int RegType) const;
401 MachineInstr * cpMem2RegMI(const unsigned SrcPtrReg, const int Offset,
402 const unsigned DestReg, const int RegType) const;
404 MachineInstr* cpValue2Value(Value *Src, Value *Dest) const;
407 inline bool isRegVolatile(const int RegClassID, const int Reg) const {
408 return (MachineRegClassArr[RegClassID])->isRegVolatile(Reg);
412 inline unsigned getFramePointer() const {
413 return SparcIntRegOrder::i6;
416 inline unsigned getStackPointer() const {
417 return SparcIntRegOrder::o6;
420 inline int getInvalidRegNum() const {
421 return InvalidRegNum;
425 void insertCallerSavingCode(const MachineInstr *MInst,
426 const BasicBlock *BB, PhyRegAlloc &PRA ) const;
433 /*---------------------------------------------------------------------------
434 Scheduling guidelines for SPARC IIi:
436 I-Cache alignment rules (pg 326)
437 -- Align a branch target instruction so that it's entire group is within
438 the same cache line (may be 1-4 instructions).
439 ** Don't let a branch that is predicted taken be the last instruction
440 on an I-cache line: delay slot will need an entire line to be fetched
441 -- Make a FP instruction or a branch be the 4th instruction in a group.
442 For branches, there are tradeoffs in reordering to make this happen
444 ** Don't put a branch in a group that crosses a 32-byte boundary!
445 An artificial branch is inserted after every 32 bytes, and having
446 another branch will force the group to be broken into 2 groups.
449 -- Don't let a loop span two memory pages, if possible
451 Branch prediction performance:
452 -- Don't make the branch in a delay slot the target of a branch
453 -- Try not to have 2 predicted branches within a group of 4 instructions
454 (because each such group has a single branch target field).
455 -- Try to align branches in slots 0, 2, 4 or 6 of a cache line (to avoid
456 the wrong prediction bits being used in some cases).
458 D-Cache timing constraints:
459 -- Signed int loads of less than 64 bits have 3 cycle latency, not 2
460 -- All other loads that hit in D-Cache have 2 cycle latency
461 -- All loads are returned IN ORDER, so a D-Cache miss will delay a later hit
462 -- Mis-aligned loads or stores cause a trap. In particular, replace
463 mis-aligned FP double precision l/s with 2 single-precision l/s.
464 -- Simulations of integer codes show increase in avg. group size of
465 33% when code (including esp. non-faulting loads) is moved across
466 one branch, and 50% across 2 branches.
468 E-Cache timing constraints:
469 -- Scheduling for E-cache (D-Cache misses) is effective (due to load buffering)
471 Store buffer timing constraints:
472 -- Stores can be executed in same cycle as instruction producing the value
473 -- Stores are buffered and have lower priority for E-cache until
474 highwater mark is reached in the store buffer (5 stores)
476 Pipeline constraints:
477 -- Shifts can only use IEU0.
478 -- CC setting instructions can only use IEU1.
479 -- Several other instructions must only use IEU1:
480 EDGE(?), ARRAY(?), CALL, JMPL, BPr, PST, and FCMP.
481 -- Two instructions cannot store to the same register file in a single cycle
482 (single write port per file).
484 Issue and grouping constraints:
485 -- FP and branch instructions must use slot 4.
486 -- Shift instructions cannot be grouped with other IEU0-specific instructions.
487 -- CC setting instructions cannot be grouped with other IEU1-specific instrs.
488 -- Several instructions must be issued in a single-instruction group:
489 MOVcc or MOVr, MULs/x and DIVs/x, SAVE/RESTORE, many others
490 -- A CALL or JMPL breaks a group, ie, is not combined with subsequent instrs.
494 Branch delay slot scheduling rules:
495 -- A CTI couple (two back-to-back CTI instructions in the dynamic stream)
496 has a 9-instruction penalty: the entire pipeline is flushed when the
497 second instruction reaches stage 9 (W-Writeback).
498 -- Avoid putting multicycle instructions, and instructions that may cause
499 load misses, in the delay slot of an annulling branch.
500 -- Avoid putting WR, SAVE..., RESTORE and RETURN instructions in the
501 delay slot of an annulling branch.
503 *--------------------------------------------------------------------------- */
505 //---------------------------------------------------------------------------
506 // List of CPUResources for UltraSPARC IIi.
507 //---------------------------------------------------------------------------
509 const CPUResource AllIssueSlots( "All Instr Slots", 4);
510 const CPUResource IntIssueSlots( "Int Instr Slots", 3);
511 const CPUResource First3IssueSlots("Instr Slots 0-3", 3);
512 const CPUResource LSIssueSlots( "Load-Store Instr Slot", 1);
513 const CPUResource CTIIssueSlots( "Ctrl Transfer Instr Slot", 1);
514 const CPUResource FPAIssueSlots( "Int Instr Slot 1", 1);
515 const CPUResource FPMIssueSlots( "Int Instr Slot 1", 1);
517 // IEUN instructions can use either Alu and should use IAluN.
518 // IEU0 instructions must use Alu 1 and should use both IAluN and IAlu0.
519 // IEU1 instructions must use Alu 2 and should use both IAluN and IAlu1.
520 const CPUResource IAluN("Int ALU 1or2", 2);
521 const CPUResource IAlu0("Int ALU 1", 1);
522 const CPUResource IAlu1("Int ALU 2", 1);
524 const CPUResource LSAluC1("Load/Store Unit Addr Cycle", 1);
525 const CPUResource LSAluC2("Load/Store Unit Issue Cycle", 1);
526 const CPUResource LdReturn("Load Return Unit", 1);
528 const CPUResource FPMAluC1("FP Mul/Div Alu Cycle 1", 1);
529 const CPUResource FPMAluC2("FP Mul/Div Alu Cycle 2", 1);
530 const CPUResource FPMAluC3("FP Mul/Div Alu Cycle 3", 1);
532 const CPUResource FPAAluC1("FP Other Alu Cycle 1", 1);
533 const CPUResource FPAAluC2("FP Other Alu Cycle 2", 1);
534 const CPUResource FPAAluC3("FP Other Alu Cycle 3", 1);
536 const CPUResource IRegReadPorts("Int Reg ReadPorts", INT_MAX); // CHECK
537 const CPUResource IRegWritePorts("Int Reg WritePorts", 2); // CHECK
538 const CPUResource FPRegReadPorts("FP Reg Read Ports", INT_MAX); // CHECK
539 const CPUResource FPRegWritePorts("FP Reg Write Ports", 1); // CHECK
541 const CPUResource CTIDelayCycle( "CTI delay cycle", 1);
542 const CPUResource FCMPDelayCycle("FCMP delay cycle", 1);
545 //---------------------------------------------------------------------------
546 // const InstrClassRUsage SparcRUsageDesc[]
549 // Resource usage information for instruction in each scheduling class.
550 // The InstrRUsage Objects for individual classes are specified first.
551 // Note that fetch and decode are decoupled from the execution pipelines
552 // via an instr buffer, so they are not included in the cycles below.
553 //---------------------------------------------------------------------------
555 const InstrClassRUsage NoneClassRUsage = {
560 /* isSingleIssue */ false,
561 /* breaksGroup */ false,
565 /* feasibleSlots[] */ { 0, 1, 2, 3 },
579 const InstrClassRUsage IEUNClassRUsage = {
584 /* isSingleIssue */ false,
585 /* breaksGroup */ false,
589 /* feasibleSlots[] */ { 0, 1, 2 },
593 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
594 { IntIssueSlots.rid, 0, 1 },
595 /*Cycle E */ { IAluN.rid, 1, 1 },
600 /*Cycle W */ { IRegWritePorts.rid, 6, 1 }
604 const InstrClassRUsage IEU0ClassRUsage = {
609 /* isSingleIssue */ false,
610 /* breaksGroup */ false,
614 /* feasibleSlots[] */ { 0, 1, 2 },
618 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
619 { IntIssueSlots.rid, 0, 1 },
620 /*Cycle E */ { IAluN.rid, 1, 1 },
626 /*Cycle W */ { IRegWritePorts.rid, 6, 1 }
630 const InstrClassRUsage IEU1ClassRUsage = {
635 /* isSingleIssue */ false,
636 /* breaksGroup */ false,
640 /* feasibleSlots[] */ { 0, 1, 2 },
644 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
645 { IntIssueSlots.rid, 0, 1 },
646 /*Cycle E */ { IAluN.rid, 1, 1 },
652 /*Cycle W */ { IRegWritePorts.rid, 6, 1 }
656 const InstrClassRUsage FPMClassRUsage = {
661 /* isSingleIssue */ false,
662 /* breaksGroup */ false,
666 /* feasibleSlots[] */ { 0, 1, 2, 3 },
670 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
671 { FPMIssueSlots.rid, 0, 1 },
672 /*Cycle E */ { FPRegReadPorts.rid, 1, 1 },
673 /*Cycle C */ { FPMAluC1.rid, 2, 1 },
674 /*Cycle N1*/ { FPMAluC2.rid, 3, 1 },
675 /*Cycle N1*/ { FPMAluC3.rid, 4, 1 },
677 /*Cycle W */ { FPRegWritePorts.rid, 6, 1 }
681 const InstrClassRUsage FPAClassRUsage = {
686 /* isSingleIssue */ false,
687 /* breaksGroup */ false,
691 /* feasibleSlots[] */ { 0, 1, 2, 3 },
695 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
696 { FPAIssueSlots.rid, 0, 1 },
697 /*Cycle E */ { FPRegReadPorts.rid, 1, 1 },
698 /*Cycle C */ { FPAAluC1.rid, 2, 1 },
699 /*Cycle N1*/ { FPAAluC2.rid, 3, 1 },
700 /*Cycle N1*/ { FPAAluC3.rid, 4, 1 },
702 /*Cycle W */ { FPRegWritePorts.rid, 6, 1 }
706 const InstrClassRUsage LDClassRUsage = {
711 /* isSingleIssue */ false,
712 /* breaksGroup */ false,
716 /* feasibleSlots[] */ { 0, 1, 2, },
720 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
721 { First3IssueSlots.rid, 0, 1 },
722 { LSIssueSlots.rid, 0, 1 },
723 /*Cycle E */ { LSAluC1.rid, 1, 1 },
724 /*Cycle C */ { LSAluC2.rid, 2, 1 },
725 { LdReturn.rid, 2, 1 },
729 /*Cycle W */ { IRegWritePorts.rid, 6, 1 }
733 const InstrClassRUsage STClassRUsage = {
738 /* isSingleIssue */ false,
739 /* breaksGroup */ false,
743 /* feasibleSlots[] */ { 0, 1, 2 },
747 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
748 { First3IssueSlots.rid, 0, 1 },
749 { LSIssueSlots.rid, 0, 1 },
750 /*Cycle E */ { LSAluC1.rid, 1, 1 },
751 /*Cycle C */ { LSAluC2.rid, 2, 1 }
759 const InstrClassRUsage CTIClassRUsage = {
764 /* isSingleIssue */ false,
765 /* breaksGroup */ false,
769 /* feasibleSlots[] */ { 0, 1, 2, 3 },
773 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
774 { CTIIssueSlots.rid, 0, 1 },
775 /*Cycle E */ { IAlu0.rid, 1, 1 },
776 /*Cycles E-C */ { CTIDelayCycle.rid, 1, 2 }
785 const InstrClassRUsage SingleClassRUsage = {
790 /* isSingleIssue */ true,
791 /* breaksGroup */ false,
795 /* feasibleSlots[] */ { 0 },
799 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
800 { AllIssueSlots.rid, 0, 1 },
801 { AllIssueSlots.rid, 0, 1 },
802 { AllIssueSlots.rid, 0, 1 },
803 /*Cycle E */ { IAlu0.rid, 1, 1 }
813 const InstrClassRUsage SparcRUsageDesc[] = {
827 //---------------------------------------------------------------------------
828 // const InstrIssueDelta SparcInstrIssueDeltas[]
831 // Changes to issue restrictions information in InstrClassRUsage for
832 // instructions that differ from other instructions in their class.
833 //---------------------------------------------------------------------------
835 const InstrIssueDelta SparcInstrIssueDeltas[] = {
837 // opCode, isSingleIssue, breaksGroup, numBubbles
839 // Special cases for single-issue only
840 // Other single issue cases are below.
841 //{ LDDA, true, true, 0 },
842 //{ STDA, true, true, 0 },
843 //{ LDDF, true, true, 0 },
844 //{ LDDFA, true, true, 0 },
845 { ADDC, true, true, 0 },
846 { ADDCcc, true, true, 0 },
847 { SUBC, true, true, 0 },
848 { SUBCcc, true, true, 0 },
849 //{ LDSTUB, true, true, 0 },
850 //{ SWAP, true, true, 0 },
851 //{ SWAPA, true, true, 0 },
852 //{ CAS, true, true, 0 },
853 //{ CASA, true, true, 0 },
854 //{ CASX, true, true, 0 },
855 //{ CASXA, true, true, 0 },
856 //{ LDFSR, true, true, 0 },
857 //{ LDFSRA, true, true, 0 },
858 //{ LDXFSR, true, true, 0 },
859 //{ LDXFSRA, true, true, 0 },
860 //{ STFSR, true, true, 0 },
861 //{ STFSRA, true, true, 0 },
862 //{ STXFSR, true, true, 0 },
863 //{ STXFSRA, true, true, 0 },
864 //{ SAVED, true, true, 0 },
865 //{ RESTORED, true, true, 0 },
866 //{ FLUSH, true, true, 9 },
867 //{ FLUSHW, true, true, 9 },
868 //{ ALIGNADDR, true, true, 0 },
869 { RETURN, true, true, 0 },
870 //{ DONE, true, true, 0 },
871 //{ RETRY, true, true, 0 },
872 //{ WR, true, true, 0 },
873 //{ WRPR, true, true, 4 },
874 //{ RD, true, true, 0 },
875 //{ RDPR, true, true, 0 },
876 //{ TCC, true, true, 0 },
877 //{ SHUTDOWN, true, true, 0 },
879 // Special cases for breaking group *before*
880 // CURRENTLY NOT SUPPORTED!
881 { CALL, false, false, 0 },
882 { JMPLCALL, false, false, 0 },
883 { JMPLRET, false, false, 0 },
885 // Special cases for breaking the group *after*
886 { MULX, true, true, (4+34)/2 },
887 { FDIVS, false, true, 0 },
888 { FDIVD, false, true, 0 },
889 { FDIVQ, false, true, 0 },
890 { FSQRTS, false, true, 0 },
891 { FSQRTD, false, true, 0 },
892 { FSQRTQ, false, true, 0 },
893 //{ FCMP{LE,GT,NE,EQ}, false, true, 0 },
895 // Instructions that introduce bubbles
896 //{ MULScc, true, true, 2 },
897 //{ SMULcc, true, true, (4+18)/2 },
898 //{ UMULcc, true, true, (4+19)/2 },
899 { SDIVX, true, true, 68 },
900 { UDIVX, true, true, 68 },
901 //{ SDIVcc, true, true, 36 },
902 //{ UDIVcc, true, true, 37 },
903 //{ WR, false, false, 4 },
904 //{ WRPR, false, false, 4 },
908 //---------------------------------------------------------------------------
909 // const InstrRUsageDelta SparcInstrUsageDeltas[]
912 // Changes to resource usage information in InstrClassRUsage for
913 // instructions that differ from other instructions in their class.
914 //---------------------------------------------------------------------------
916 const InstrRUsageDelta SparcInstrUsageDeltas[] = {
918 // MachineOpCode, Resource, Start cycle, Num cycles
921 // JMPL counts as a load/store instruction for issue!
923 { JMPLCALL, LSIssueSlots.rid, 0, 1 },
924 { JMPLRET, LSIssueSlots.rid, 0, 1 },
927 // Many instructions cannot issue for the next 2 cycles after an FCMP
928 // We model that with a fake resource FCMPDelayCycle.
930 { FCMPS, FCMPDelayCycle.rid, 1, 3 },
931 { FCMPD, FCMPDelayCycle.rid, 1, 3 },
932 { FCMPQ, FCMPDelayCycle.rid, 1, 3 },
934 { MULX, FCMPDelayCycle.rid, 1, 1 },
935 { SDIVX, FCMPDelayCycle.rid, 1, 1 },
936 { UDIVX, FCMPDelayCycle.rid, 1, 1 },
937 //{ SMULcc, FCMPDelayCycle.rid, 1, 1 },
938 //{ UMULcc, FCMPDelayCycle.rid, 1, 1 },
939 //{ SDIVcc, FCMPDelayCycle.rid, 1, 1 },
940 //{ UDIVcc, FCMPDelayCycle.rid, 1, 1 },
941 { STD, FCMPDelayCycle.rid, 1, 1 },
942 { FMOVRSZ, FCMPDelayCycle.rid, 1, 1 },
943 { FMOVRSLEZ,FCMPDelayCycle.rid, 1, 1 },
944 { FMOVRSLZ, FCMPDelayCycle.rid, 1, 1 },
945 { FMOVRSNZ, FCMPDelayCycle.rid, 1, 1 },
946 { FMOVRSGZ, FCMPDelayCycle.rid, 1, 1 },
947 { FMOVRSGEZ,FCMPDelayCycle.rid, 1, 1 },
950 // Some instructions are stalled in the GROUP stage if a CTI is in
953 { LDD, CTIDelayCycle.rid, 1, 1 },
954 //{ LDDA, CTIDelayCycle.rid, 1, 1 },
955 //{ LDDSTUB, CTIDelayCycle.rid, 1, 1 },
956 //{ LDDSTUBA, CTIDelayCycle.rid, 1, 1 },
957 //{ SWAP, CTIDelayCycle.rid, 1, 1 },
958 //{ SWAPA, CTIDelayCycle.rid, 1, 1 },
959 //{ CAS, CTIDelayCycle.rid, 1, 1 },
960 //{ CASA, CTIDelayCycle.rid, 1, 1 },
961 //{ CASX, CTIDelayCycle.rid, 1, 1 },
962 //{ CASXA, CTIDelayCycle.rid, 1, 1 },
965 // Signed int loads of less than dword size return data in cycle N1 (not C)
966 // and put all loads in consecutive cycles into delayed load return mode.
968 { LDSB, LdReturn.rid, 2, -1 },
969 { LDSB, LdReturn.rid, 3, 1 },
971 { LDSH, LdReturn.rid, 2, -1 },
972 { LDSH, LdReturn.rid, 3, 1 },
974 { LDSW, LdReturn.rid, 2, -1 },
975 { LDSW, LdReturn.rid, 3, 1 },
978 #undef EXPLICIT_BUBBLES_NEEDED
979 #ifdef EXPLICIT_BUBBLES_NEEDED
981 // MULScc inserts one bubble.
982 // This means it breaks the current group (captured in UltraSparcSchedInfo)
983 // *and occupies all issue slots for the next cycle
985 //{ MULScc, AllIssueSlots.rid, 2, 2-1 },
986 //{ MULScc, AllIssueSlots.rid, 2, 2-1 },
987 //{ MULScc, AllIssueSlots.rid, 2, 2-1 },
988 //{ MULScc, AllIssueSlots.rid, 2, 2-1 },
991 // SMULcc inserts between 4 and 18 bubbles, depending on #leading 0s in rs1.
992 // We just model this with a simple average.
994 //{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
995 //{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
996 //{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
997 //{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
999 // SMULcc inserts between 4 and 19 bubbles, depending on #leading 0s in rs1.
1000 //{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
1001 //{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
1002 //{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
1003 //{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
1006 // MULX inserts between 4 and 34 bubbles, depending on #leading 0s in rs1.
1008 { MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
1009 { MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
1010 { MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
1011 { MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
1014 // SDIVcc inserts 36 bubbles.
1016 //{ SDIVcc, AllIssueSlots.rid, 2, 36-1 },
1017 //{ SDIVcc, AllIssueSlots.rid, 2, 36-1 },
1018 //{ SDIVcc, AllIssueSlots.rid, 2, 36-1 },
1019 //{ SDIVcc, AllIssueSlots.rid, 2, 36-1 },
1021 // UDIVcc inserts 37 bubbles.
1022 //{ UDIVcc, AllIssueSlots.rid, 2, 37-1 },
1023 //{ UDIVcc, AllIssueSlots.rid, 2, 37-1 },
1024 //{ UDIVcc, AllIssueSlots.rid, 2, 37-1 },
1025 //{ UDIVcc, AllIssueSlots.rid, 2, 37-1 },
1028 // SDIVX inserts 68 bubbles.
1030 { SDIVX, AllIssueSlots.rid, 2, 68-1 },
1031 { SDIVX, AllIssueSlots.rid, 2, 68-1 },
1032 { SDIVX, AllIssueSlots.rid, 2, 68-1 },
1033 { SDIVX, AllIssueSlots.rid, 2, 68-1 },
1036 // UDIVX inserts 68 bubbles.
1038 { UDIVX, AllIssueSlots.rid, 2, 68-1 },
1039 { UDIVX, AllIssueSlots.rid, 2, 68-1 },
1040 { UDIVX, AllIssueSlots.rid, 2, 68-1 },
1041 { UDIVX, AllIssueSlots.rid, 2, 68-1 },
1044 // WR inserts 4 bubbles.
1046 //{ WR, AllIssueSlots.rid, 2, 68-1 },
1047 //{ WR, AllIssueSlots.rid, 2, 68-1 },
1048 //{ WR, AllIssueSlots.rid, 2, 68-1 },
1049 //{ WR, AllIssueSlots.rid, 2, 68-1 },
1052 // WRPR inserts 4 bubbles.
1054 //{ WRPR, AllIssueSlots.rid, 2, 68-1 },
1055 //{ WRPR, AllIssueSlots.rid, 2, 68-1 },
1056 //{ WRPR, AllIssueSlots.rid, 2, 68-1 },
1057 //{ WRPR, AllIssueSlots.rid, 2, 68-1 },
1060 // DONE inserts 9 bubbles.
1062 //{ DONE, AllIssueSlots.rid, 2, 9-1 },
1063 //{ DONE, AllIssueSlots.rid, 2, 9-1 },
1064 //{ DONE, AllIssueSlots.rid, 2, 9-1 },
1065 //{ DONE, AllIssueSlots.rid, 2, 9-1 },
1068 // RETRY inserts 9 bubbles.
1070 //{ RETRY, AllIssueSlots.rid, 2, 9-1 },
1071 //{ RETRY, AllIssueSlots.rid, 2, 9-1 },
1072 //{ RETRY, AllIssueSlots.rid, 2, 9-1 },
1073 //{ RETRY, AllIssueSlots.rid, 2, 9-1 },
1075 #endif /*EXPLICIT_BUBBLES_NEEDED */
1080 // Additional delays to be captured in code:
1081 // 1. RDPR from several state registers (page 349)
1082 // 2. RD from *any* register (page 349)
1083 // 3. Writes to TICK, PSTATE, TL registers and FLUSH{W} instr (page 349)
1084 // 4. Integer store can be in same group as instr producing value to store.
1085 // 5. BICC and BPICC can be in the same group as instr producing CC (pg 350)
1086 // 6. FMOVr cannot be in the same or next group as an IEU instr (pg 351).
1087 // 7. The second instr. of a CTI group inserts 9 bubbles (pg 351)
1088 // 8. WR{PR}, SVAE, SAVED, RESTORE, RESTORED, RETURN, RETRY, and DONE that
1089 // follow an annulling branch cannot be issued in the same group or in
1090 // the 3 groups following the branch.
1091 // 9. A predicted annulled load does not stall dependent instructions.
1092 // Other annulled delay slot instructions *do* stall dependents, so
1093 // nothing special needs to be done for them during scheduling.
1094 //10. Do not put a load use that may be annulled in the same group as the
1095 // branch. The group will stall until the load returns.
1096 //11. Single-prec. FP loads lock 2 registers, for dependency checking.
1099 // Additional delays we cannot or will not capture:
1100 // 1. If DCTI is last word of cache line, it is delayed until next line can be
1101 // fetched. Also, other DCTI alignment-related delays (pg 352)
1102 // 2. Load-after-store is delayed by 7 extra cycles if load hits in D-Cache.
1103 // Also, several other store-load and load-store conflicts (pg 358)
1104 // 3. MEMBAR, LD{X}FSR, LDD{A} and a bunch of other load stalls (pg 358)
1105 // 4. There can be at most 8 outstanding buffered store instructions
1106 // (including some others like MEMBAR, LDSTUB, CAS{AX}, and FLUSH)
1110 //---------------------------------------------------------------------------
1111 // class UltraSparcSchedInfo
1114 // Interface to instruction scheduling information for UltraSPARC.
1115 // The parameter values above are based on UltraSPARC IIi.
1116 //---------------------------------------------------------------------------
1119 class UltraSparcSchedInfo: public MachineSchedInfo {
1121 /*ctor*/ UltraSparcSchedInfo (const MachineInstrInfo* mii);
1122 /*dtor*/ virtual ~UltraSparcSchedInfo () {}
1124 virtual void initializeResources ();
1128 //---------------------------------------------------------------------------
1129 // class UltraSparcFrameInfo
1132 // Interface to stack frame layout info for the UltraSPARC.
1133 // Note that there is no machine-independent interface to this information
1134 //---------------------------------------------------------------------------
1136 class UltraSparcFrameInfo: public NonCopyable {
1138 static const int MinStackFrameSize = 176;
1139 static const int FirstOutgoingArgOffsetFromSP = 128;
1140 static const int FirstOptionalOutgoingArgOffsetFromSP = 176;
1141 static const int StaticStackAreaOffsetFromFP = -1;
1143 static const int FirstIncomingArgOffsetFromFP = 126;
1145 static int getFirstAutomaticVarOffsetFromFP (const Method* method);
1146 static int getRegSpillAreaOffsetFromFP (const Method* method);
1147 static int getFrameSizeBelowDynamicArea (const Method* method);
1152 //---------------------------------------------------------------------------
1153 // class UltraSparcMachine
1156 // Primary interface to machine description for the UltraSPARC.
1157 // Primarily just initializes machine-dependent parameters in
1158 // class TargetMachine, and creates machine-dependent subclasses
1159 // for classes such as InstrInfo, SchedInfo and RegInfo.
1160 //---------------------------------------------------------------------------
1162 class UltraSparc : public TargetMachine {
1164 UltraSparcInstrInfo instrInfo;
1165 UltraSparcSchedInfo schedInfo;
1166 UltraSparcRegInfo regInfo;
1167 UltraSparcFrameInfo frameInfo;
1170 virtual ~UltraSparc() {}
1172 virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
1173 virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
1174 virtual const MachineRegInfo &getRegInfo() const { return regInfo; }
1175 const UltraSparcFrameInfo &getFrameInfo() const { return frameInfo; }
1178 // compileMethod - For the sparc, we do instruction selection, followed by
1179 // delay slot scheduling, then register allocation.
1181 virtual bool compileMethod(Method *M);
1184 // emitAssembly - Output assembly language code (a .s file) for the specified
1185 // module. The specified module must have been compiled before this may be
1188 virtual void emitAssembly(const Module *M, ostream &OutStr) const;