1 //===-- SparcRegClassInfo.h - Register class def'ns for Sparc ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the register classes used by the Sparc target description.
12 //===----------------------------------------------------------------------===//
14 #ifndef SPARC_REG_CLASS_INFO_H
15 #define SPARC_REG_CLASS_INFO_H
17 #include "llvm/Target/TargetRegInfo.h"
19 //-----------------------------------------------------------------------------
20 // Integer Register Class
21 //-----------------------------------------------------------------------------
23 struct SparcIntRegClass : public TargetRegClassInfo {
24 SparcIntRegClass(unsigned ID)
25 : TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) { }
27 void colorIGNode(IGNode *Node,
28 const std::vector<bool> &IsColorUsedArr) const;
30 inline bool isRegVolatile(int Reg) const {
31 return (Reg < (int)StartOfNonVolatileRegs);
34 inline bool modifiedByCall(int Reg) const {
35 return Reg==(int)ModifiedByCall;
38 enum { // colors possible for a LR (in preferred order)
39 // --- following colors are volatile across function calls
40 // %g0 can't be used for coloring - always 0
41 o0, o1, o2, o3, o4, o5, o7, // %o0-%o5,
44 // all %0's can get modified by a call
46 // --- following colors are NON-volatile across function calls
47 l0, l1, l2, l3, l4, l5, l6, l7, // %l0-%l7
48 i0, i1, i2, i3, i4, i5, // %i0-%i5: i's need not be preserved
50 // %i6 is the fp - so not allocated
51 // %i7 is the ret address by convention - can be used for others
53 // max # of colors reg coloring can allocate (NumOfAvailRegs)
55 // --- following colors are not available for allocation within this phase
56 // --- but can appear for pre-colored ranges
58 i6, i7, g0, g1, g2, g3, g4, g5, g6, g7, o6,
60 NumOfAllRegs, // Must be first AFTER registers...
62 //*** NOTE: If we decide to use some %g regs, they are volatile
64 // Move the %g regs from the end of the enumeration to just above the
65 // enumeration of %o0 (change StartOfAllRegs below)
66 // change isRegVloatile method below
67 // Also change IntRegNames above.
69 // max # of colors reg coloring can allocate
72 StartOfNonVolatileRegs = l0,
78 const char * const getRegName(unsigned reg) const;
84 //-----------------------------------------------------------------------------
85 // Float Register Class
86 //-----------------------------------------------------------------------------
88 class SparcFloatRegClass : public TargetRegClassInfo {
89 int findFloatColor(const LiveRange *LR, unsigned Start,
91 const std::vector<bool> &IsColorUsedArr) const;
93 SparcFloatRegClass(unsigned ID)
94 : TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {}
96 // This method marks the registers used for a given register number.
97 // This marks a single register for Float regs, but the R,R+1 pair
98 // for double-precision registers.
100 virtual void markColorsUsed(unsigned RegInClass,
103 std::vector<bool> &IsColorUsedArr) const;
105 // This method finds unused registers of the specified register type,
106 // using the given "used" flag array IsColorUsedArr. It checks a single
107 // entry in the array directly for float regs, and checks the pair [R,R+1]
108 // for double-precision registers
109 // It returns -1 if no unused color is found.
111 virtual int findUnusedColor(int RegTypeWanted,
112 const std::vector<bool> &IsColorUsedArr) const;
114 void colorIGNode(IGNode *Node,
115 const std::vector<bool> &IsColorUsedArr) const;
117 // according to Sparc 64 ABI, all %fp regs are volatile
118 inline bool isRegVolatile(int Reg) const { return true; }
121 f0, f1, f2, f3, f4, f5, f6, f7, f8, f9,
122 f10, f11, f12, f13, f14, f15, f16, f17, f18, f19,
123 f20, f21, f22, f23, f24, f25, f26, f27, f28, f29,
124 f30, f31, f32, f33, f34, f35, f36, f37, f38, f39,
125 f40, f41, f42, f43, f44, f45, f46, f47, f48, f49,
126 f50, f51, f52, f53, f54, f55, f56, f57, f58, f59,
129 // there are 64 regs alltogether but only 32 regs can be allocated at
135 StartOfNonVolatileRegs = f32,
139 const char * const getRegName(unsigned reg) const;
145 //-----------------------------------------------------------------------------
146 // Int CC Register Class
147 // Only one integer cc register is available. However, this register is
148 // referred to as %xcc or %icc when instructions like subcc are executed but
149 // referred to as %ccr (i.e., %xcc . %icc") when this register is moved
150 // into an integer register using RD or WR instrcutions. So, three ids are
151 // allocated for the three names.
152 //-----------------------------------------------------------------------------
154 struct SparcIntCCRegClass : public TargetRegClassInfo {
155 SparcIntCCRegClass(unsigned ID)
156 : TargetRegClassInfo(ID, 1, 3) { }
158 void colorIGNode(IGNode *Node,
159 const std::vector<bool> &IsColorUsedArr) const;
161 // according to Sparc 64 ABI, %ccr is volatile
163 inline bool isRegVolatile(int Reg) const { return true; }
166 xcc, icc, ccr // only one is available - see the note above
169 const char * const getRegName(unsigned reg) const;
173 //-----------------------------------------------------------------------------
174 // Float CC Register Class
175 // Only 4 Float CC registers are available for allocation.
176 //-----------------------------------------------------------------------------
178 struct SparcFloatCCRegClass : public TargetRegClassInfo {
179 SparcFloatCCRegClass(unsigned ID)
180 : TargetRegClassInfo(ID, 4, 5) { }
182 void colorIGNode(IGNode *Node,
183 const std::vector<bool> &IsColorUsedArr) const;
185 // according to Sparc 64 ABI, all %fp CC regs are volatile
187 inline bool isRegVolatile(int Reg) const { return true; }
190 fcc0, fcc1, fcc2, fcc3, fsr // fsr is not used in allocation
191 }; // but has a name in getRegName()
193 const char * const getRegName(unsigned reg) const;
196 //-----------------------------------------------------------------------------
197 // Sparc special register class. These registers are not used for allocation
198 // but are used as arguments of some instructions.
199 //-----------------------------------------------------------------------------
201 struct SparcSpecialRegClass : public TargetRegClassInfo {
202 SparcSpecialRegClass(unsigned ID)
203 : TargetRegClassInfo(ID, 0, 1) { }
205 void colorIGNode(IGNode *Node,
206 const std::vector<bool> &IsColorUsedArr) const {
207 assert(0 && "SparcSpecialRegClass should never be used for allocation");
210 // all currently included special regs are volatile
211 inline bool isRegVolatile(int Reg) const { return true; }
214 fsr // floating point state register
217 const char * const getRegName(unsigned reg) const;