1 //===-- SparcV9RegClassInfo.h - Register class def'ns for SparcV9 -*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the register classes used by the SparcV9 target. It
11 // implicitly defines (using enums) the "class register numbers" used in
12 // the SparcV9 target, which are converted using a formula in the SparcV9RegInfo
13 // class to "unified register numbers".
15 //===----------------------------------------------------------------------===//
17 #ifndef SPARCV9REGCLASSINFO_H
18 #define SPARCV9REGCLASSINFO_H
20 #include "SparcV9RegInfo.h"
24 //-----------------------------------------------------------------------------
25 // Integer Register Class
26 //-----------------------------------------------------------------------------
28 struct SparcV9IntRegClass : public TargetRegClassInfo {
29 SparcV9IntRegClass(unsigned ID)
30 : TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) { }
32 void colorIGNode(IGNode *Node,
33 const std::vector<bool> &IsColorUsedArr) const;
35 inline bool isRegVolatile(int Reg) const {
36 return (Reg < (int)StartOfNonVolatileRegs);
39 inline bool modifiedByCall(int Reg) const {
40 return Reg==(int)ModifiedByCall;
43 enum { // colors possible for a LR (in preferred order)
44 // --- following colors are volatile across function calls
45 // %g0 can't be used for coloring - always 0
46 o0, o1, o2, o3, o4, o5, o7, // %o0-%o5,
49 // all %0's can get modified by a call
51 // --- following colors are NON-volatile across function calls
52 l0, l1, l2, l3, l4, l5, l6, l7, // %l0-%l7
53 i0, i1, i2, i3, i4, i5, // %i0-%i5: i's need not be preserved
55 // %i6 is the fp - so not allocated
56 // %i7 is the ret address by convention - can be used for others
58 // max # of colors reg coloring can allocate (NumOfAvailRegs)
60 // --- following colors are not available for allocation within this phase
61 // --- but can appear for pre-colored ranges
63 i6, i7, g0, g1, g2, g3, g4, g5, g6, g7, o6,
65 NumOfAllRegs, // Must be first AFTER registers...
67 //*** NOTE: If we decide to use some %g regs, they are volatile
69 // Move the %g regs from the end of the enumeration to just above the
70 // enumeration of %o0 (change StartOfAllRegs below)
71 // change isRegVloatile method below
72 // Also change IntRegNames above.
74 // max # of colors reg coloring can allocate
77 StartOfNonVolatileRegs = l0,
83 const char * const getRegName(unsigned reg) const;
87 //-----------------------------------------------------------------------------
88 // Float Register Class
89 //-----------------------------------------------------------------------------
91 class SparcV9FloatRegClass : public TargetRegClassInfo {
92 int findFloatColor(const LiveRange *LR, unsigned Start,
94 const std::vector<bool> &IsColorUsedArr) const;
96 SparcV9FloatRegClass(unsigned ID)
97 : TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {}
99 // This method marks the registers used for a given register number.
100 // This marks a single register for Float regs, but the R,R+1 pair
101 // for double-precision registers.
103 virtual void markColorsUsed(unsigned RegInClass,
106 std::vector<bool> &IsColorUsedArr) const;
108 // This method finds unused registers of the specified register type,
109 // using the given "used" flag array IsColorUsedArr. It checks a single
110 // entry in the array directly for float regs, and checks the pair [R,R+1]
111 // for double-precision registers
112 // It returns -1 if no unused color is found.
114 virtual int findUnusedColor(int RegTypeWanted,
115 const std::vector<bool> &IsColorUsedArr) const;
117 void colorIGNode(IGNode *Node,
118 const std::vector<bool> &IsColorUsedArr) const;
120 // according to SparcV9 64 ABI, all %fp regs are volatile
121 inline bool isRegVolatile(int Reg) const { return true; }
124 f0, f1, f2, f3, f4, f5, f6, f7, f8, f9,
125 f10, f11, f12, f13, f14, f15, f16, f17, f18, f19,
126 f20, f21, f22, f23, f24, f25, f26, f27, f28, f29,
127 f30, f31, f32, f33, f34, f35, f36, f37, f38, f39,
128 f40, f41, f42, f43, f44, f45, f46, f47, f48, f49,
129 f50, f51, f52, f53, f54, f55, f56, f57, f58, f59,
132 // there are 64 regs alltogether but only 32 regs can be allocated at
138 StartOfNonVolatileRegs = f32,
142 const char * const getRegName(unsigned reg) const;
146 //-----------------------------------------------------------------------------
147 // Int CC Register Class
148 // Only one integer cc register is available. However, this register is
149 // referred to as %xcc or %icc when instructions like subcc are executed but
150 // referred to as %ccr (i.e., %xcc . %icc") when this register is moved
151 // into an integer register using RD or WR instrcutions. So, three ids are
152 // allocated for the three names.
153 //-----------------------------------------------------------------------------
155 struct SparcV9IntCCRegClass : public TargetRegClassInfo {
156 SparcV9IntCCRegClass(unsigned ID)
157 : TargetRegClassInfo(ID, 1, 3) { }
159 void colorIGNode(IGNode *Node,
160 const std::vector<bool> &IsColorUsedArr) const;
162 // according to the 64-bit SparcV9 ABI, all integer CC regs are
164 inline bool isRegVolatile(int Reg) const { return true; }
167 xcc, icc, ccr // only one is available - see the note above
170 const char * const getRegName(unsigned reg) const;
174 //-----------------------------------------------------------------------------
175 // Float CC Register Class
176 // Only 4 Float CC registers are available for allocation.
177 //-----------------------------------------------------------------------------
179 struct SparcV9FloatCCRegClass : public TargetRegClassInfo {
180 SparcV9FloatCCRegClass(unsigned ID)
181 : TargetRegClassInfo(ID, 4, 4) { }
183 void colorIGNode(IGNode *Node,
184 const std::vector<bool> &IsColorUsedArr) const;
186 // according to the 64-bit SparcV9 ABI, all floating-point CC regs are
188 inline bool isRegVolatile(int Reg) const { return true; }
191 fcc0, fcc1, fcc2, fcc3
194 const char * const getRegName(unsigned reg) const;
198 //-----------------------------------------------------------------------------
199 // SparcV9 special register class. These registers are not used for allocation
200 // but are used as arguments of some instructions.
201 //-----------------------------------------------------------------------------
203 struct SparcV9SpecialRegClass : public TargetRegClassInfo {
204 SparcV9SpecialRegClass(unsigned ID)
205 : TargetRegClassInfo(ID, 0, 1) { }
207 void colorIGNode(IGNode *Node,
208 const std::vector<bool> &IsColorUsedArr) const {
209 assert(0 && "SparcV9SpecialRegClass should never be used for allocation");
212 // all currently included special regs are volatile
213 inline bool isRegVolatile(int Reg) const { return true; }
216 fsr // floating point state register
219 const char * const getRegName(unsigned reg) const;
222 } // End llvm namespace