1 /* Title: SparcRegClassInfo.h -*- C++ -*-
2 Author: Ruchira Sasanka
4 Purpose: Contains the description of integer register class of Sparc
8 #ifndef SPARC_REG_INFO_CLASS_H
9 #define SPARC_REG_INFO_CLASS_H
11 #include "llvm/Target/MachineRegInfo.h"
12 #include "llvm/CodeGen/IGNode.h"
14 //-----------------------------------------------------------------------------
15 // Integer Register Class
16 //-----------------------------------------------------------------------------
18 // Int register names in same order as enum in class SparcIntRegOrder
20 static const std::string IntRegNames[] = {
21 "o0", "o1", "o2", "o3", "o4", "o5", "o7",
22 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
23 "i0", "i1", "i2", "i3", "i4", "i5",
25 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
31 struct SparcIntRegOrder {
32 enum RegsInPrefOrder { // colors possible for a LR (in preferred order)
33 // --- following colors are volatile across function calls
34 // %g0 can't be used for coloring - always 0
35 o0, o1, o2, o3, o4, o5, o7, // %o0-%o5,
38 // all %0's can get modified by a call
40 // --- following colors are NON-volatile across function calls
41 l0, l1, l2, l3, l4, l5, l6, l7, // %l0-%l7
42 i0, i1, i2, i3, i4, i5, // %i0-%i5: i's need not be preserved
44 // %i6 is the fp - so not allocated
45 // %i7 is the ret address by convention - can be used for others
47 // max # of colors reg coloring can allocate (NumOfAvailRegs)
49 // --- following colors are not available for allocation within this phase
50 // --- but can appear for pre-colored ranges
52 i6, i7, g0, g1, g2, g3, g4, g5, g6, g7, o6
54 //*** NOTE: If we decide to use some %g regs, they are volatile
56 // Move the %g regs from the end of the enumeration to just above the
57 // enumeration of %o0 (change StartOfAllRegs below)
58 // change isRegVloatile method below
59 // Also change IntRegNames above.
62 // max # of colors reg coloring can allocate
63 static unsigned int const NumOfAvailRegs = i6;
65 static unsigned int const StartOfNonVolatileRegs = l0;
66 static unsigned int const StartOfAllRegs = o0;
67 static unsigned int const NumOfAllRegs = o6 + 1;
70 static const std::string getRegName(unsigned reg) {
71 assert( reg < NumOfAllRegs );
72 return IntRegNames[reg];
79 struct SparcIntRegClass : public MachineRegClassInfo {
80 SparcIntRegClass(unsigned ID)
81 : MachineRegClassInfo(ID,
82 SparcIntRegOrder::NumOfAvailRegs,
83 SparcIntRegOrder::NumOfAllRegs) { }
85 void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const;
87 inline bool isRegVolatile(int Reg) const {
88 return (Reg < (int) SparcIntRegOrder::StartOfNonVolatileRegs);
95 //-----------------------------------------------------------------------------
96 // Float Register Class
97 //-----------------------------------------------------------------------------
99 static const std::string FloatRegNames[] =
101 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
102 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
103 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
104 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
105 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
106 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
107 "f60", "f61", "f62", "f63"
111 class SparcFloatRegOrder{
115 enum RegsInPrefOrder {
117 f0, f1, f2, f3, f4, f5, f6, f7, f8, f9,
118 f10, f11, f12, f13, f14, f15, f16, f17, f18, f19,
119 f20, f21, f22, f23, f24, f25, f26, f27, f28, f29,
120 f30, f31, f32, f33, f34, f35, f36, f37, f38, f39,
121 f40, f41, f42, f43, f44, f45, f46, f47, f48, f49,
122 f50, f51, f52, f53, f54, f55, f56, f57, f58, f59,
127 // there are 64 regs alltogether but only 32 regs can be allocated at
130 static unsigned int const NumOfAvailRegs = 32;
131 static unsigned int const NumOfAllRegs = 64;
133 static unsigned int const StartOfNonVolatileRegs = f32;
134 static unsigned int const StartOfAllRegs = f0;
137 static const std::string getRegName(unsigned reg) {
138 assert (reg < NumOfAllRegs);
139 return FloatRegNames[reg];
145 class SparcFloatRegClass : public MachineRegClassInfo {
146 int findFloatColor(const LiveRange *LR, unsigned Start,
147 unsigned End, std::vector<bool> &IsColorUsedArr) const;
149 SparcFloatRegClass(unsigned ID)
150 : MachineRegClassInfo(ID,
151 SparcFloatRegOrder::NumOfAvailRegs,
152 SparcFloatRegOrder::NumOfAllRegs) {}
154 void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const;
156 // according to Sparc 64 ABI, all %fp regs are volatile
157 inline bool isRegVolatile(int Reg) const { return true; }
163 //-----------------------------------------------------------------------------
164 // Int CC Register Class
165 // Only one integer cc register is available. However, this register is
166 // referred to as %xcc when instructions like subcc are executed but
167 // referred to as %ccr (i.e., %xcc + %icc") when this register is moved
168 // into an integer register using RD or WR instrcutions. So, two ids are
169 // allocated for two names.
170 //-----------------------------------------------------------------------------
173 static const std::string IntCCRegNames[] = {
178 struct SparcIntCCRegOrder {
179 enum RegsInPrefOrder {
180 xcc, ccr // only one is available - see the note above
183 static const std::string getRegName(unsigned reg) {
185 return IntCCRegNames[reg];
191 struct SparcIntCCRegClass : public MachineRegClassInfo {
192 SparcIntCCRegClass(unsigned ID)
193 : MachineRegClassInfo(ID, 1, 2) { }
195 void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const {
196 if (IsColorUsedArr[0])
197 Node->getParentLR()->markForSpill();
199 Node->setColor(0); // only one int cc reg is available
202 // according to Sparc 64 ABI, %ccr is volatile
204 inline bool isRegVolatile(int Reg) const { return true; }
210 //-----------------------------------------------------------------------------
211 // Float CC Register Class
212 // Only 4 Float CC registers are available
213 //-----------------------------------------------------------------------------
215 static const std::string FloatCCRegNames[] = {
216 "fcc0", "fcc1", "fcc2", "fcc3"
219 struct SparcFloatCCRegOrder{
220 enum RegsInPrefOrder {
221 fcc0, fcc1, fcc2, fcc3
224 static const std::string getRegName(unsigned reg) {
226 return FloatCCRegNames[reg];
230 struct SparcFloatCCRegClass : public MachineRegClassInfo {
231 SparcFloatCCRegClass(unsigned ID)
232 : MachineRegClassInfo(ID, 4, 4) { }
234 void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const {
235 for(unsigned c = 0; c != 4; ++c)
236 if (!IsColorUsedArr[c]) { // find unused color
241 Node->getParentLR()->markForSpill();
244 // according to Sparc 64 ABI, all %fp CC regs are volatile
246 inline bool isRegVolatile(int Reg) const { return true; }