1 //===-- SparcV9RegClassInfo.h - Register class def'ns for SparcV9 ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the register classes used by the SparcV9 target description.
12 //===----------------------------------------------------------------------===//
14 #ifndef SPARCV9REGCLASSINFO_H
15 #define SPARCV9REGCLASSINFO_H
17 #include "SparcV9RegInfo.h"
21 //-----------------------------------------------------------------------------
22 // Integer Register Class
23 //-----------------------------------------------------------------------------
25 struct SparcV9IntRegClass : public TargetRegClassInfo {
26 SparcV9IntRegClass(unsigned ID)
27 : TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) { }
29 void colorIGNode(IGNode *Node,
30 const std::vector<bool> &IsColorUsedArr) const;
32 inline bool isRegVolatile(int Reg) const {
33 return (Reg < (int)StartOfNonVolatileRegs);
36 inline bool modifiedByCall(int Reg) const {
37 return Reg==(int)ModifiedByCall;
40 enum { // colors possible for a LR (in preferred order)
41 // --- following colors are volatile across function calls
42 // %g0 can't be used for coloring - always 0
43 o0, o1, o2, o3, o4, o5, o7, // %o0-%o5,
46 // all %0's can get modified by a call
48 // --- following colors are NON-volatile across function calls
49 l0, l1, l2, l3, l4, l5, l6, l7, // %l0-%l7
50 i0, i1, i2, i3, i4, i5, // %i0-%i5: i's need not be preserved
52 // %i6 is the fp - so not allocated
53 // %i7 is the ret address by convention - can be used for others
55 // max # of colors reg coloring can allocate (NumOfAvailRegs)
57 // --- following colors are not available for allocation within this phase
58 // --- but can appear for pre-colored ranges
60 i6, i7, g0, g1, g2, g3, g4, g5, g6, g7, o6,
62 NumOfAllRegs, // Must be first AFTER registers...
64 //*** NOTE: If we decide to use some %g regs, they are volatile
66 // Move the %g regs from the end of the enumeration to just above the
67 // enumeration of %o0 (change StartOfAllRegs below)
68 // change isRegVloatile method below
69 // Also change IntRegNames above.
71 // max # of colors reg coloring can allocate
74 StartOfNonVolatileRegs = l0,
80 const char * const getRegName(unsigned reg) const;
84 //-----------------------------------------------------------------------------
85 // Float Register Class
86 //-----------------------------------------------------------------------------
88 class SparcV9FloatRegClass : public TargetRegClassInfo {
89 int findFloatColor(const LiveRange *LR, unsigned Start,
91 const std::vector<bool> &IsColorUsedArr) const;
93 SparcV9FloatRegClass(unsigned ID)
94 : TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {}
96 // This method marks the registers used for a given register number.
97 // This marks a single register for Float regs, but the R,R+1 pair
98 // for double-precision registers.
100 virtual void markColorsUsed(unsigned RegInClass,
103 std::vector<bool> &IsColorUsedArr) const;
105 // This method finds unused registers of the specified register type,
106 // using the given "used" flag array IsColorUsedArr. It checks a single
107 // entry in the array directly for float regs, and checks the pair [R,R+1]
108 // for double-precision registers
109 // It returns -1 if no unused color is found.
111 virtual int findUnusedColor(int RegTypeWanted,
112 const std::vector<bool> &IsColorUsedArr) const;
114 void colorIGNode(IGNode *Node,
115 const std::vector<bool> &IsColorUsedArr) const;
117 // according to SparcV9 64 ABI, all %fp regs are volatile
118 inline bool isRegVolatile(int Reg) const { return true; }
121 f0, f1, f2, f3, f4, f5, f6, f7, f8, f9,
122 f10, f11, f12, f13, f14, f15, f16, f17, f18, f19,
123 f20, f21, f22, f23, f24, f25, f26, f27, f28, f29,
124 f30, f31, f32, f33, f34, f35, f36, f37, f38, f39,
125 f40, f41, f42, f43, f44, f45, f46, f47, f48, f49,
126 f50, f51, f52, f53, f54, f55, f56, f57, f58, f59,
129 // there are 64 regs alltogether but only 32 regs can be allocated at
135 StartOfNonVolatileRegs = f32,
139 const char * const getRegName(unsigned reg) const;
143 //-----------------------------------------------------------------------------
144 // Int CC Register Class
145 // Only one integer cc register is available. However, this register is
146 // referred to as %xcc or %icc when instructions like subcc are executed but
147 // referred to as %ccr (i.e., %xcc . %icc") when this register is moved
148 // into an integer register using RD or WR instrcutions. So, three ids are
149 // allocated for the three names.
150 //-----------------------------------------------------------------------------
152 struct SparcV9IntCCRegClass : public TargetRegClassInfo {
153 SparcV9IntCCRegClass(unsigned ID)
154 : TargetRegClassInfo(ID, 1, 3) { }
156 void colorIGNode(IGNode *Node,
157 const std::vector<bool> &IsColorUsedArr) const;
159 // according to the 64-bit SparcV9 ABI, all integer CC regs are
161 inline bool isRegVolatile(int Reg) const { return true; }
164 xcc, icc, ccr // only one is available - see the note above
167 const char * const getRegName(unsigned reg) const;
171 //-----------------------------------------------------------------------------
172 // Float CC Register Class
173 // Only 4 Float CC registers are available for allocation.
174 //-----------------------------------------------------------------------------
176 struct SparcV9FloatCCRegClass : public TargetRegClassInfo {
177 SparcV9FloatCCRegClass(unsigned ID)
178 : TargetRegClassInfo(ID, 4, 4) { }
180 void colorIGNode(IGNode *Node,
181 const std::vector<bool> &IsColorUsedArr) const;
183 // according to the 64-bit SparcV9 ABI, all floating-point CC regs are
185 inline bool isRegVolatile(int Reg) const { return true; }
188 fcc0, fcc1, fcc2, fcc3
191 const char * const getRegName(unsigned reg) const;
195 //-----------------------------------------------------------------------------
196 // SparcV9 special register class. These registers are not used for allocation
197 // but are used as arguments of some instructions.
198 //-----------------------------------------------------------------------------
200 struct SparcV9SpecialRegClass : public TargetRegClassInfo {
201 SparcV9SpecialRegClass(unsigned ID)
202 : TargetRegClassInfo(ID, 0, 1) { }
204 void colorIGNode(IGNode *Node,
205 const std::vector<bool> &IsColorUsedArr) const {
206 assert(0 && "SparcV9SpecialRegClass should never be used for allocation");
209 // all currently included special regs are volatile
210 inline bool isRegVolatile(int Reg) const { return true; }
213 fsr // floating point state register
216 const char * const getRegName(unsigned reg) const;
219 } // End llvm namespace