1 //===-- SparcRegClassInfo.h - Register class def'ns for Sparc ----*- C++ -*--=//
3 // This file defines the register classes used by the Sparc target description.
5 //===----------------------------------------------------------------------===//
7 #ifndef SPARC_REG_CLASS_INFO_H
8 #define SPARC_REG_CLASS_INFO_H
10 #include "llvm/Target/TargetRegInfo.h"
11 #include "llvm/CodeGen/IGNode.h"
13 //-----------------------------------------------------------------------------
14 // Integer Register Class
15 //-----------------------------------------------------------------------------
18 struct SparcIntRegClass : public TargetRegClassInfo {
19 SparcIntRegClass(unsigned ID)
20 : TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) { }
22 void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const;
24 inline bool isRegVolatile(int Reg) const {
25 return (Reg < (int)StartOfNonVolatileRegs);
28 enum { // colors possible for a LR (in preferred order)
29 // --- following colors are volatile across function calls
30 // %g0 can't be used for coloring - always 0
31 o0, o1, o2, o3, o4, o5, o7, // %o0-%o5,
34 // all %0's can get modified by a call
36 // --- following colors are NON-volatile across function calls
37 l0, l1, l2, l3, l4, l5, l6, l7, // %l0-%l7
38 i0, i1, i2, i3, i4, i5, // %i0-%i5: i's need not be preserved
40 // %i6 is the fp - so not allocated
41 // %i7 is the ret address by convention - can be used for others
43 // max # of colors reg coloring can allocate (NumOfAvailRegs)
45 // --- following colors are not available for allocation within this phase
46 // --- but can appear for pre-colored ranges
48 i6, i7, g0, g1, g2, g3, g4, g5, g6, g7, o6,
50 NumOfAllRegs, // Must be first AFTER registers...
52 //*** NOTE: If we decide to use some %g regs, they are volatile
54 // Move the %g regs from the end of the enumeration to just above the
55 // enumeration of %o0 (change StartOfAllRegs below)
56 // change isRegVloatile method below
57 // Also change IntRegNames above.
59 // max # of colors reg coloring can allocate
62 StartOfNonVolatileRegs = l0,
66 const char * const getRegName(unsigned reg) const;
72 //-----------------------------------------------------------------------------
73 // Float Register Class
74 //-----------------------------------------------------------------------------
76 class SparcFloatRegClass : public TargetRegClassInfo {
77 int findFloatColor(const LiveRange *LR, unsigned Start,
78 unsigned End, std::vector<bool> &IsColorUsedArr) const;
80 SparcFloatRegClass(unsigned ID)
81 : TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {}
83 void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const;
85 // according to Sparc 64 ABI, all %fp regs are volatile
86 inline bool isRegVolatile(int Reg) const { return true; }
89 f0, f1, f2, f3, f4, f5, f6, f7, f8, f9,
90 f10, f11, f12, f13, f14, f15, f16, f17, f18, f19,
91 f20, f21, f22, f23, f24, f25, f26, f27, f28, f29,
92 f30, f31, f32, f33, f34, f35, f36, f37, f38, f39,
93 f40, f41, f42, f43, f44, f45, f46, f47, f48, f49,
94 f50, f51, f52, f53, f54, f55, f56, f57, f58, f59,
97 // there are 64 regs alltogether but only 32 regs can be allocated at
103 StartOfNonVolatileRegs = f32,
107 const char * const getRegName(unsigned reg) const;
113 //-----------------------------------------------------------------------------
114 // Int CC Register Class
115 // Only one integer cc register is available. However, this register is
116 // referred to as %xcc or %icc when instructions like subcc are executed but
117 // referred to as %ccr (i.e., %xcc . %icc") when this register is moved
118 // into an integer register using RD or WR instrcutions. So, three ids are
119 // allocated for the three names.
120 //-----------------------------------------------------------------------------
122 struct SparcIntCCRegClass : public TargetRegClassInfo {
123 SparcIntCCRegClass(unsigned ID)
124 : TargetRegClassInfo(ID, 1, 3) { }
126 void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const;
128 // according to Sparc 64 ABI, %ccr is volatile
130 inline bool isRegVolatile(int Reg) const { return true; }
133 xcc, icc, ccr // only one is available - see the note above
136 const char * const getRegName(unsigned reg) const;
142 //-----------------------------------------------------------------------------
143 // Float CC Register Class
144 // Only 4 Float CC registers are available for allocation.
145 //-----------------------------------------------------------------------------
147 struct SparcFloatCCRegClass : public TargetRegClassInfo {
148 SparcFloatCCRegClass(unsigned ID)
149 : TargetRegClassInfo(ID, 4, 5) { }
151 void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const {
152 for(unsigned c = 0; c != 4; ++c)
153 if (!IsColorUsedArr[c]) { // find unused color
158 Node->getParentLR()->markForSpill();
161 // according to Sparc 64 ABI, all %fp CC regs are volatile
163 inline bool isRegVolatile(int Reg) const { return true; }
166 fcc0, fcc1, fcc2, fcc3, fsr // fsr is not used in allocation
167 }; // but has a name in getRegName()
169 const char * const getRegName(unsigned reg) const;
172 //-----------------------------------------------------------------------------
173 // Sparc special register class. These registers are not used for allocation
174 // but are used as arguments of some instructions.
175 //-----------------------------------------------------------------------------
177 struct SparcSpecialRegClass : public TargetRegClassInfo {
178 SparcSpecialRegClass(unsigned ID)
179 : TargetRegClassInfo(ID, 0, 1) { }
181 void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const {
182 assert(0 && "SparcSpecialRegClass should never be used for allocation");
185 // all currently included special regs are volatile
186 inline bool isRegVolatile(int Reg) const { return true; }
189 fsr // floating point state register
192 const char * const getRegName(unsigned reg) const;