1 //===-- SparcV9RegInfo.cpp - SparcV9 Target Register Information ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains implementations of SparcV9 specific helper methods
11 // used for register allocation.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "MachineFunctionInfo.h"
18 #include "MachineCodeForInstruction.h"
19 #include "MachineInstrAnnot.h"
20 #include "RegAlloc/LiveRangeInfo.h"
21 #include "RegAlloc/LiveRange.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/Instructions.h"
25 #include "SparcV9Internals.h"
26 #include "SparcV9RegClassInfo.h"
27 #include "SparcV9RegInfo.h"
28 #include "SparcV9FrameInfo.h"
29 #include "SparcV9TargetMachine.h"
30 #include "SparcV9TmpInstr.h"
39 SparcV9RegInfo::SparcV9RegInfo(const SparcV9TargetMachine &tgt)
40 : target (tgt), NumOfIntArgRegs (6), NumOfFloatArgRegs (32)
42 MachineRegClassArr.push_back(new SparcV9IntRegClass(IntRegClassID));
43 MachineRegClassArr.push_back(new SparcV9FloatRegClass(FloatRegClassID));
44 MachineRegClassArr.push_back(new SparcV9IntCCRegClass(IntCCRegClassID));
45 MachineRegClassArr.push_back(new SparcV9FloatCCRegClass(FloatCCRegClassID));
46 MachineRegClassArr.push_back(new SparcV9SpecialRegClass(SpecialRegClassID));
48 assert(SparcV9FloatRegClass::StartOfNonVolatileRegs == 32 &&
49 "32 Float regs are used for float arg passing");
53 // getZeroRegNum - returns the register that contains always zero.
54 // this is the unified register number
56 unsigned SparcV9RegInfo::getZeroRegNum() const {
57 return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
58 SparcV9IntRegClass::g0);
61 // getCallAddressReg - returns the reg used for pushing the address when a
62 // method is called. This can be used for other purposes between calls
64 unsigned SparcV9RegInfo::getCallAddressReg() const {
65 return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
66 SparcV9IntRegClass::o7);
69 // Returns the register containing the return address.
70 // It should be made sure that this register contains the return
71 // value when a return instruction is reached.
73 unsigned SparcV9RegInfo::getReturnAddressReg() const {
74 return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
75 SparcV9IntRegClass::i7);
78 // Register get name implementations...
80 // Int register names in same order as enum in class SparcV9IntRegClass
81 static const char * const IntRegNames[] = {
82 "o0", "o1", "o2", "o3", "o4", "o5", "o7",
83 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
84 "i0", "i1", "i2", "i3", "i4", "i5",
86 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
90 const char * const SparcV9IntRegClass::getRegName(unsigned reg) const {
91 assert(reg < NumOfAllRegs);
92 return IntRegNames[reg];
95 static const char * const FloatRegNames[] = {
96 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
97 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
98 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
99 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
100 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
101 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
102 "f60", "f61", "f62", "f63"
105 const char * const SparcV9FloatRegClass::getRegName(unsigned reg) const {
106 assert (reg < NumOfAllRegs);
107 return FloatRegNames[reg];
110 static const char * const IntCCRegNames[] = {
114 const char * const SparcV9IntCCRegClass::getRegName(unsigned reg) const {
116 return IntCCRegNames[reg];
119 static const char * const FloatCCRegNames[] = {
120 "fcc0", "fcc1", "fcc2", "fcc3"
123 const char * const SparcV9FloatCCRegClass::getRegName(unsigned reg) const {
125 return FloatCCRegNames[reg];
128 static const char * const SpecialRegNames[] = {
132 const char * const SparcV9SpecialRegClass::getRegName(unsigned reg) const {
134 return SpecialRegNames[reg];
137 // Get unified reg number for frame pointer
138 unsigned SparcV9RegInfo::getFramePointer() const {
139 return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
140 SparcV9IntRegClass::i6);
143 // Get unified reg number for stack pointer
144 unsigned SparcV9RegInfo::getStackPointer() const {
145 return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
146 SparcV9IntRegClass::o6);
150 //---------------------------------------------------------------------------
151 // Finds whether a call is an indirect call
152 //---------------------------------------------------------------------------
155 isVarArgsFunction(const Type *funcType) {
156 return cast<FunctionType>(cast<PointerType>(funcType)
157 ->getElementType())->isVarArg();
161 isVarArgsCall(const MachineInstr *CallMI) {
162 Value* callee = CallMI->getOperand(0).getVRegValue();
163 // const Type* funcType = isa<Function>(callee)? callee->getType()
164 // : cast<PointerType>(callee->getType())->getElementType();
165 const Type* funcType = callee->getType();
166 return isVarArgsFunction(funcType);
170 // Get the register number for the specified argument #argNo,
173 // getInvalidRegNum(), if there is no int register available for the arg.
174 // regNum, otherwise (this is NOT the unified reg. num).
175 // regClassId is set to the register class ID.
178 SparcV9RegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall,
179 unsigned argNo, unsigned& regClassId) const
181 regClassId = IntRegClassID;
182 if (argNo >= NumOfIntArgRegs)
183 return getInvalidRegNum();
185 return argNo + (inCallee? SparcV9IntRegClass::i0 : SparcV9IntRegClass::o0);
188 // Get the register number for the specified FP argument #argNo,
189 // Use INT regs for FP args if this is a varargs call.
192 // getInvalidRegNum(), if there is no int register available for the arg.
193 // regNum, otherwise (this is NOT the unified reg. num).
194 // regClassId is set to the register class ID.
197 SparcV9RegInfo::regNumForFPArg(unsigned regType,
198 bool inCallee, bool isVarArgsCall,
199 unsigned argNo, unsigned& regClassId) const
202 return regNumForIntArg(inCallee, isVarArgsCall, argNo, regClassId);
205 regClassId = FloatRegClassID;
206 if (regType == FPSingleRegType)
207 return (argNo*2+1 >= NumOfFloatArgRegs)?
208 getInvalidRegNum() : SparcV9FloatRegClass::f0 + (argNo * 2 + 1);
209 else if (regType == FPDoubleRegType)
210 return (argNo*2 >= NumOfFloatArgRegs)?
211 getInvalidRegNum() : SparcV9FloatRegClass::f0 + (argNo * 2);
213 assert(0 && "Illegal FP register type");
219 //---------------------------------------------------------------------------
220 // Finds the return address of a call sparc specific call instruction
221 //---------------------------------------------------------------------------
223 // The following 4 methods are used to find the RegType (SparcV9Internals.h)
224 // of a V9LiveRange, a Value, and for a given register unified reg number.
226 int SparcV9RegInfo::getRegTypeForClassAndType(unsigned regClassID,
227 const Type* type) const
229 switch (regClassID) {
230 case IntRegClassID: return IntRegType;
231 case FloatRegClassID:
232 if (type == Type::FloatTy) return FPSingleRegType;
233 else if (type == Type::DoubleTy) return FPDoubleRegType;
234 assert(0 && "Unknown type in FloatRegClass"); return 0;
235 case IntCCRegClassID: return IntCCRegType;
236 case FloatCCRegClassID: return FloatCCRegType;
237 case SpecialRegClassID: return SpecialRegType;
238 default: assert( 0 && "Unknown reg class ID"); return 0;
242 int SparcV9RegInfo::getRegTypeForDataType(const Type* type) const
244 return getRegTypeForClassAndType(getRegClassIDOfType(type), type);
247 int SparcV9RegInfo::getRegTypeForLR(const V9LiveRange *LR) const
249 return getRegTypeForClassAndType(LR->getRegClassID(), LR->getType());
252 int SparcV9RegInfo::getRegType(int unifiedRegNum) const
254 if (unifiedRegNum < 32)
256 else if (unifiedRegNum < (32 + 32))
257 return FPSingleRegType;
258 else if (unifiedRegNum < (64 + 32))
259 return FPDoubleRegType;
260 else if (unifiedRegNum < (64+32+3))
262 else if (unifiedRegNum < (64+32+3+4))
263 return FloatCCRegType;
264 else if (unifiedRegNum < (64+32+3+4+1))
265 return SpecialRegType;
267 assert(0 && "Invalid unified register number in getRegType");
272 // To find the register class used for a specified Type
274 unsigned SparcV9RegInfo::getRegClassIDOfType(const Type *type,
275 bool isCCReg) const {
276 Type::TypeID ty = type->getTypeID();
279 // FIXME: Comparing types like this isn't very safe...
280 if ((ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
281 (ty == Type::FunctionTyID) || (ty == Type::PointerTyID) )
282 res = IntRegClassID; // sparc int reg (ty=0: void)
283 else if (ty <= Type::DoubleTyID)
284 res = FloatRegClassID; // sparc float reg class
286 //std::cerr << "TypeID: " << ty << "\n";
287 assert(0 && "Cannot resolve register class for type");
292 return res + 2; // corresponding condition code register
297 unsigned SparcV9RegInfo::getRegClassIDOfRegType(int regType) const {
299 case IntRegType: return IntRegClassID;
300 case FPSingleRegType:
301 case FPDoubleRegType: return FloatRegClassID;
302 case IntCCRegType: return IntCCRegClassID;
303 case FloatCCRegType: return FloatCCRegClassID;
304 case SpecialRegType: return SpecialRegClassID;
306 assert(0 && "Invalid register type in getRegClassIDOfRegType");
311 //---------------------------------------------------------------------------
312 // Suggests a register for the ret address in the RET machine instruction.
313 // We always suggest %i7 by convention.
314 //---------------------------------------------------------------------------
315 void SparcV9RegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
316 LiveRangeInfo& LRI) const {
318 assert(target.getInstrInfo()->isReturn(RetMI->getOpcode()));
320 // return address is always mapped to i7 so set it immediately
321 RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID,
322 SparcV9IntRegClass::i7));
324 // Possible Optimization:
325 // Instead of setting the color, we can suggest one. In that case,
326 // we have to test later whether it received the suggested color.
327 // In that case, a LR has to be created at the start of method.
328 // It has to be done as follows (remove the setRegVal above):
330 // MachineOperand & MO = RetMI->getOperand(0);
331 // const Value *RetAddrVal = MO.getVRegValue();
332 // assert( RetAddrVal && "LR for ret address must be created at start");
333 // V9LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
334 // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
335 // SparcV9IntRegOrdr::i7) );
339 //---------------------------------------------------------------------------
340 // Suggests a register for the ret address in the JMPL/CALL machine instr.
341 // SparcV9 ABI dictates that %o7 be used for this purpose.
342 //---------------------------------------------------------------------------
344 SparcV9RegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
345 LiveRangeInfo& LRI) const
347 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
348 const Value *RetAddrVal = argDesc->getReturnAddrReg();
349 assert(RetAddrVal && "INTERNAL ERROR: Return address value is required");
351 // A LR must already exist for the return address.
352 V9LiveRange *RetAddrLR = LRI.getLiveRangeForValue(RetAddrVal);
353 assert(RetAddrLR && "INTERNAL ERROR: No LR for return address of call!");
355 unsigned RegClassID = RetAddrLR->getRegClassID();
356 RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID, SparcV9IntRegClass::o7));
361 //---------------------------------------------------------------------------
362 // This method will suggest colors to incoming args to a method.
363 // According to the SparcV9 ABI, the first 6 incoming args are in
364 // %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float).
365 // If the arg is passed on stack due to the lack of regs, NOTHING will be
366 // done - it will be colored (or spilled) as a normal live range.
367 //---------------------------------------------------------------------------
368 void SparcV9RegInfo::suggestRegs4MethodArgs(const Function *Meth,
369 LiveRangeInfo& LRI) const
371 // Check if this is a varArgs function. needed for choosing regs.
372 bool isVarArgs = isVarArgsFunction(Meth->getType());
374 // Count the arguments, *ignoring* whether they are int or FP args.
375 // Use this common arg numbering to pick the right int or fp register.
377 for(Function::const_arg_iterator I = Meth->arg_begin(), E = Meth->arg_end();
378 I != E; ++I, ++argNo) {
379 V9LiveRange *LR = LRI.getLiveRangeForValue(I);
380 assert(LR && "No live range found for method arg");
382 unsigned regType = getRegTypeForLR(LR);
383 unsigned regClassIDOfArgReg = BadRegClass; // for chosen reg (unused)
385 int regNum = (regType == IntRegType)
386 ? regNumForIntArg(/*inCallee*/ true, isVarArgs, argNo, regClassIDOfArgReg)
387 : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs, argNo,
390 if (regNum != getInvalidRegNum())
391 LR->setSuggestedColor(regNum);
396 //---------------------------------------------------------------------------
397 // This method is called after graph coloring to move incoming args to
398 // the correct hardware registers if they did not receive the correct
399 // (suggested) color through graph coloring.
400 //---------------------------------------------------------------------------
401 void SparcV9RegInfo::colorMethodArgs(const Function *Meth,
403 std::vector<MachineInstr*>& InstrnsBefore,
404 std::vector<MachineInstr*>& InstrnsAfter) const {
406 // check if this is a varArgs function. needed for choosing regs.
407 bool isVarArgs = isVarArgsFunction(Meth->getType());
411 // for each argument. count INT and FP arguments separately.
412 unsigned argNo=0, intArgNo=0, fpArgNo=0;
413 for(Function::const_arg_iterator I = Meth->arg_begin(), E = Meth->arg_end();
414 I != E; ++I, ++argNo) {
416 V9LiveRange *LR = LRI.getLiveRangeForValue(I);
417 assert( LR && "No live range found for method arg");
419 unsigned regType = getRegTypeForLR(LR);
420 unsigned RegClassID = LR->getRegClassID();
422 // Find whether this argument is coming in a register (if not, on stack)
423 // Also find the correct register the argument must use (UniArgReg)
425 bool isArgInReg = false;
426 unsigned UniArgReg = getInvalidRegNum(); // reg that LR MUST be colored with
427 unsigned regClassIDOfArgReg = BadRegClass; // reg class of chosen reg
429 int regNum = (regType == IntRegType)
430 ? regNumForIntArg(/*inCallee*/ true, isVarArgs,
431 argNo, regClassIDOfArgReg)
432 : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs,
433 argNo, regClassIDOfArgReg);
435 if(regNum != getInvalidRegNum()) {
437 UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum);
440 if( ! LR->isMarkedForSpill() ) { // if this arg received a register
442 unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
444 // if LR received the correct color, nothing to do
446 if( UniLRReg == UniArgReg )
449 // We are here because the LR did not receive the suggested
450 // but LR received another register.
451 // Now we have to copy the %i reg (or stack pos of arg)
452 // to the register the LR was colored with.
454 // if the arg is coming in UniArgReg register, it MUST go into
455 // the UniLRReg register
458 if( regClassIDOfArgReg != RegClassID ) {
459 // NOTE: This code has not been well-tested.
461 // It is a variable argument call: the float reg must go in a %o reg.
462 // We have to move an int reg to a float reg via memory.
465 RegClassID == FloatRegClassID &&
466 regClassIDOfArgReg == IntRegClassID &&
467 "This should only be an Int register for an FP argument");
469 int TmpOff = MachineFunction::get(Meth).getInfo<SparcV9FunctionInfo>()->pushTempValue(
470 getSpilledRegSize(regType));
471 cpReg2MemMI(InstrnsBefore,
472 UniArgReg, getFramePointer(), TmpOff, IntRegType);
474 cpMem2RegMI(InstrnsBefore,
475 getFramePointer(), TmpOff, UniLRReg, regType);
478 cpReg2RegMI(InstrnsBefore, UniArgReg, UniLRReg, regType);
483 // Now the arg is coming on stack. Since the LR received a register,
484 // we just have to load the arg on stack into that register
486 const TargetFrameInfo& frameInfo = *target.getFrameInfo();
488 frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
491 // float arguments on stack are right justified so adjust the offset!
492 // int arguments are also right justified but they are always loaded as
493 // a full double-word so the offset does not need to be adjusted.
494 if (regType == FPSingleRegType) {
495 unsigned argSize = target.getTargetData().getTypeSize(LR->getType());
496 unsigned slotSize = SparcV9FrameInfo::SizeOfEachArgOnStack;
497 assert(argSize <= slotSize && "Insufficient slot size!");
498 offsetFromFP += slotSize - argSize;
501 cpMem2RegMI(InstrnsBefore,
502 getFramePointer(), offsetFromFP, UniLRReg, regType);
505 } // if LR received a color
509 // Now, the LR did not receive a color. But it has a stack offset for
511 // So, if the arg is coming in UniArgReg register, we can just move
512 // that on to the stack pos of LR
516 if( regClassIDOfArgReg != RegClassID ) {
518 "FP arguments to a varargs function should be explicitly "
519 "copied to/from int registers by instruction selection!");
521 // It must be a float arg for a variable argument call, which
522 // must come in a %o reg. Move the int reg to the stack.
524 assert(isVarArgs && regClassIDOfArgReg == IntRegClassID &&
525 "This should only be an Int register for an FP argument");
527 cpReg2MemMI(InstrnsBefore, UniArgReg,
528 getFramePointer(), LR->getSpillOffFromFP(), IntRegType);
531 cpReg2MemMI(InstrnsBefore, UniArgReg,
532 getFramePointer(), LR->getSpillOffFromFP(), regType);
538 // Now the arg is coming on stack. Since the LR did NOT
539 // received a register as well, it is allocated a stack position. We
540 // can simply change the stack position of the LR. We can do this,
541 // since this method is called before any other method that makes
542 // uses of the stack pos of the LR (e.g., updateMachineInstr)
544 const TargetFrameInfo& frameInfo = *target.getFrameInfo();
546 frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
549 // FP arguments on stack are right justified so adjust offset!
550 // int arguments are also right justified but they are always loaded as
551 // a full double-word so the offset does not need to be adjusted.
552 if (regType == FPSingleRegType) {
553 unsigned argSize = target.getTargetData().getTypeSize(LR->getType());
554 unsigned slotSize = SparcV9FrameInfo::SizeOfEachArgOnStack;
555 assert(argSize <= slotSize && "Insufficient slot size!");
556 offsetFromFP += slotSize - argSize;
559 LR->modifySpillOffFromFP( offsetFromFP );
564 } // for each incoming argument
570 //---------------------------------------------------------------------------
571 // This method is called before graph coloring to suggest colors to the
572 // outgoing call args and the return value of the call.
573 //---------------------------------------------------------------------------
574 void SparcV9RegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
575 LiveRangeInfo& LRI) const {
576 assert ( (target.getInstrInfo())->isCall(CallMI->getOpcode()) );
578 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
580 suggestReg4CallAddr(CallMI, LRI);
582 // First color the return value of the call instruction, if any.
583 // The return value will be in %o0 if the value is an integer type,
584 // or in %f0 if the value is a float type.
586 if (const Value *RetVal = argDesc->getReturnValue()) {
587 V9LiveRange *RetValLR = LRI.getLiveRangeForValue(RetVal);
588 assert(RetValLR && "No LR for return Value of call!");
590 unsigned RegClassID = RetValLR->getRegClassID();
592 // now suggest a register depending on the register class of ret arg
593 if( RegClassID == IntRegClassID )
594 RetValLR->setSuggestedColor(SparcV9IntRegClass::o0);
595 else if (RegClassID == FloatRegClassID )
596 RetValLR->setSuggestedColor(SparcV9FloatRegClass::f0 );
597 else assert( 0 && "Unknown reg class for return value of call\n");
600 // Now suggest colors for arguments (operands) of the call instruction.
601 // Colors are suggested only if the arg number is smaller than the
602 // the number of registers allocated for argument passing.
603 // Now, go thru call args - implicit operands of the call MI
605 unsigned NumOfCallArgs = argDesc->getNumArgs();
607 for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0;
608 i < NumOfCallArgs; ++i, ++argNo) {
610 const Value *CallArg = argDesc->getArgInfo(i).getArgVal();
612 // get the LR of call operand (parameter)
613 V9LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
615 continue; // no live ranges for constants and labels
617 unsigned regType = getRegTypeForLR(LR);
618 unsigned regClassIDOfArgReg = BadRegClass; // chosen reg class (unused)
620 // Choose a register for this arg depending on whether it is
621 // an INT or FP value. Here we ignore whether or not it is a
622 // varargs calls, because FP arguments will be explicitly copied
623 // to an integer Value and handled under (argCopy != NULL) below.
624 int regNum = (regType == IntRegType)
625 ? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false,
626 argNo, regClassIDOfArgReg)
627 : regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false,
628 argNo, regClassIDOfArgReg);
630 // If a register could be allocated, use it.
631 // If not, do NOTHING as this will be colored as a normal value.
632 if(regNum != getInvalidRegNum())
633 LR->setSuggestedColor(regNum);
634 } // for all call arguments
638 //---------------------------------------------------------------------------
639 // this method is called for an LLVM return instruction to identify which
640 // values will be returned from this method and to suggest colors.
641 //---------------------------------------------------------------------------
642 void SparcV9RegInfo::suggestReg4RetValue(MachineInstr *RetMI,
643 LiveRangeInfo& LRI) const {
645 assert( target.getInstrInfo()->isReturn( RetMI->getOpcode() ) );
647 suggestReg4RetAddr(RetMI, LRI);
649 // To find the return value (if any), we can get the LLVM return instr.
650 // from the return address register, which is the first operand
651 Value* tmpI = RetMI->getOperand(0).getVRegValue();
652 ReturnInst* retI=cast<ReturnInst>(cast<TmpInstruction>(tmpI)->getOperand(0));
653 if (const Value *RetVal = retI->getReturnValue())
654 if (V9LiveRange *const LR = LRI.getLiveRangeForValue(RetVal))
655 LR->setSuggestedColor(LR->getRegClassID() == IntRegClassID
656 ? (unsigned) SparcV9IntRegClass::i0
657 : (unsigned) SparcV9FloatRegClass::f0);
660 //---------------------------------------------------------------------------
661 // Check if a specified register type needs a scratch register to be
662 // copied to/from memory. If it does, the reg. type that must be used
663 // for scratch registers is returned in scratchRegType.
665 // Only the int CC register needs such a scratch register.
666 // The FP CC registers can (and must) be copied directly to/from memory.
667 //---------------------------------------------------------------------------
670 SparcV9RegInfo::regTypeNeedsScratchReg(int RegType,
671 int& scratchRegType) const
673 if (RegType == IntCCRegType)
675 scratchRegType = IntRegType;
681 //---------------------------------------------------------------------------
682 // Copy from a register to register. Register number must be the unified
684 //---------------------------------------------------------------------------
687 SparcV9RegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
691 assert( ((int)SrcReg != getInvalidRegNum()) &&
692 ((int)DestReg != getInvalidRegNum()) &&
695 MachineInstr * MI = NULL;
700 if (getRegType(DestReg) == IntRegType) {
701 // copy intCC reg to int reg
702 MI = (BuildMI(V9::RDCCR, 2)
703 .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
704 SparcV9IntCCRegClass::ccr))
705 .addMReg(DestReg,MachineOperand::Def));
707 // copy int reg to intCC reg
708 assert(getRegType(SrcReg) == IntRegType
709 && "Can only copy CC reg to/from integer reg");
710 MI = (BuildMI(V9::WRCCRr, 3)
712 .addMReg(SparcV9IntRegClass::g0)
713 .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
714 SparcV9IntCCRegClass::ccr),
715 MachineOperand::Def));
720 assert(0 && "Cannot copy FPCC register to any other register");
724 MI = BuildMI(V9::ADDr, 3).addMReg(SrcReg).addMReg(getZeroRegNum())
725 .addMReg(DestReg, MachineOperand::Def);
728 case FPSingleRegType:
729 MI = BuildMI(V9::FMOVS, 2).addMReg(SrcReg)
730 .addMReg(DestReg, MachineOperand::Def);
733 case FPDoubleRegType:
734 MI = BuildMI(V9::FMOVD, 2).addMReg(SrcReg)
735 .addMReg(DestReg, MachineOperand::Def);
739 assert(0 && "Unknown RegType");
747 /// cpReg2MemMI - Generate SparcV9 MachineInstrs to store a register
748 /// (SrcReg) to memory, at [PtrReg + Offset]. Register numbers must be the
749 /// unified register numbers. RegType must be the SparcV9 register type
750 /// of SrcReg. When SrcReg is %ccr, scratchReg must be the
751 /// number of a free integer register. The newly-generated MachineInstrs
752 /// are appended to mvec.
754 void SparcV9RegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
755 unsigned SrcReg, unsigned PtrReg, int Offset,
756 int RegType, int scratchReg) const {
757 unsigned OffReg = SparcV9::g4; // Use register g4 for holding large offsets
758 bool useImmediateOffset = true;
760 // If the Offset will not fit in the signed-immediate field, we put it in
761 // register g4. This takes advantage of the fact that all the opcodes
762 // used below have the same size immed. field.
763 if (RegType != IntCCRegType
764 && !target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) {
765 // Put the offset into a register. We could do this in fewer steps,
766 // in some cases (see CreateSETSWConst()) but we're being lazy.
767 MachineInstr *MI = BuildMI(V9::SETHI, 2).addZImm(Offset).addMReg(OffReg,
768 MachineOperand::Def);
769 MI->getOperand(0).markHi32();
771 MI = BuildMI(V9::ORi,3).addMReg(OffReg).addZImm(Offset).addMReg(OffReg,
772 MachineOperand::Def);
773 MI->getOperand(1).markLo32();
775 MI = BuildMI(V9::SRAi5,3).addMReg(OffReg).addZImm(0).addMReg(OffReg,
776 MachineOperand::Def);
778 useImmediateOffset = false;
781 MachineInstr *MI = 0;
784 if (useImmediateOffset)
785 MI = BuildMI(V9::STXi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
787 MI = BuildMI(V9::STXr,3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg);
790 case FPSingleRegType:
791 if (useImmediateOffset)
792 MI = BuildMI(V9::STFi, 3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
794 MI = BuildMI(V9::STFr, 3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg);
797 case FPDoubleRegType:
798 if (useImmediateOffset)
799 MI = BuildMI(V9::STDFi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
801 MI = BuildMI(V9::STDFr,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(OffReg);
805 assert(scratchReg >= 0 && getRegType(scratchReg) == IntRegType
806 && "Need a scratch reg of integer type to load or store %ccr");
807 MI = BuildMI(V9::RDCCR, 2).addMReg(SparcV9::ccr)
808 .addMReg(scratchReg, MachineOperand::Def);
810 cpReg2MemMI(mvec, scratchReg, PtrReg, Offset, IntRegType);
813 case SpecialRegType: // used only for %fsr itself.
814 case FloatCCRegType: {
815 if (useImmediateOffset)
816 MI = BuildMI(V9::STXFSRi,3).addMReg(SparcV9::fsr).addMReg(PtrReg)
819 MI = BuildMI(V9::STXFSRr,3).addMReg(SparcV9::fsr).addMReg(PtrReg)
824 assert(0 && "Unknown RegType in cpReg2MemMI");
829 /// cpMem2RegMI - Generate SparcV9 MachineInstrs to load a register
830 /// (DestReg) from memory, at [PtrReg + Offset]. Register numbers must be the
831 /// unified register numbers. RegType must be the SparcV9 register type
832 /// of DestReg. When DestReg is %ccr, scratchReg must be the
833 /// number of a free integer register. The newly-generated MachineInstrs
834 /// are appended to mvec.
836 void SparcV9RegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
837 unsigned PtrReg, int Offset, unsigned DestReg,
838 int RegType, int scratchReg) const {
839 unsigned OffReg = SparcV9::g4; // Use register g4 for holding large offsets
840 bool useImmediateOffset = true;
842 // If the Offset will not fit in the signed-immediate field, we put it in
843 // register g4. This takes advantage of the fact that all the opcodes
844 // used below have the same size immed. field.
845 if (RegType != IntCCRegType
846 && !target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) {
847 MachineInstr *MI = BuildMI(V9::SETHI, 2).addZImm(Offset).addMReg(OffReg,
848 MachineOperand::Def);
849 MI->getOperand(0).markHi32();
851 MI = BuildMI(V9::ORi,3).addMReg(OffReg).addZImm(Offset).addMReg(OffReg,
852 MachineOperand::Def);
853 MI->getOperand(1).markLo32();
855 MI = BuildMI(V9::SRAi5,3).addMReg(OffReg).addZImm(0).addMReg(OffReg,
856 MachineOperand::Def);
858 useImmediateOffset = false;
861 MachineInstr *MI = 0;
864 if (useImmediateOffset)
865 MI = BuildMI(V9::LDXi, 3).addMReg(PtrReg).addSImm(Offset)
866 .addMReg(DestReg, MachineOperand::Def);
868 MI = BuildMI(V9::LDXr, 3).addMReg(PtrReg).addMReg(OffReg)
869 .addMReg(DestReg, MachineOperand::Def);
872 case FPSingleRegType:
873 if (useImmediateOffset)
874 MI = BuildMI(V9::LDFi, 3).addMReg(PtrReg).addSImm(Offset)
875 .addMReg(DestReg, MachineOperand::Def);
877 MI = BuildMI(V9::LDFr, 3).addMReg(PtrReg).addMReg(OffReg)
878 .addMReg(DestReg, MachineOperand::Def);
881 case FPDoubleRegType:
882 if (useImmediateOffset)
883 MI= BuildMI(V9::LDDFi, 3).addMReg(PtrReg).addSImm(Offset)
884 .addMReg(DestReg, MachineOperand::Def);
886 MI= BuildMI(V9::LDDFr, 3).addMReg(PtrReg).addMReg(OffReg)
887 .addMReg(DestReg, MachineOperand::Def);
891 assert(scratchReg >= 0 && getRegType(scratchReg) == IntRegType
892 && "Need a scratch reg of integer type to load or store %ccr");
893 cpMem2RegMI(mvec, PtrReg, Offset, scratchReg, IntRegType);
894 MI = BuildMI(V9::WRCCRr, 3).addMReg(scratchReg).addMReg(SparcV9::g0)
895 .addMReg(SparcV9::ccr, MachineOperand::Def);
898 case SpecialRegType: // used only for %fsr itself
899 case FloatCCRegType: {
900 if (useImmediateOffset)
901 MI = BuildMI(V9::LDXFSRi, 3).addMReg(PtrReg).addSImm(Offset)
902 .addMReg(SparcV9::fsr, MachineOperand::Def);
904 MI = BuildMI(V9::LDXFSRr, 3).addMReg(PtrReg).addMReg(OffReg)
905 .addMReg(SparcV9::fsr, MachineOperand::Def);
909 assert(0 && "Unknown RegType in cpMem2RegMI");
915 //---------------------------------------------------------------------------
916 // Generate a copy instruction to copy a value to another. Temporarily
917 // used by PhiElimination code.
918 //---------------------------------------------------------------------------
922 SparcV9RegInfo::cpValue2Value(Value *Src, Value *Dest,
923 std::vector<MachineInstr*>& mvec) const {
924 int RegType = getRegTypeForDataType(Src->getType());
925 MachineInstr * MI = NULL;
929 MI = BuildMI(V9::ADDr, 3).addReg(Src).addMReg(getZeroRegNum())
932 case FPSingleRegType:
933 MI = BuildMI(V9::FMOVS, 2).addReg(Src).addRegDef(Dest);
935 case FPDoubleRegType:
936 MI = BuildMI(V9::FMOVD, 2).addReg(Src).addRegDef(Dest);
939 assert(0 && "Unknown RegType in cpValue2Value");
947 //---------------------------------------------------------------------------
948 // Print the register assigned to a LR
949 //---------------------------------------------------------------------------
951 void SparcV9RegInfo::printReg(const V9LiveRange *LR) const {
952 unsigned RegClassID = LR->getRegClassID();
953 std::cerr << " Node ";
955 if (!LR->hasColor()) {
956 std::cerr << " - could not find a color\n";
960 // if a color is found
962 std::cerr << " colored with color "<< LR->getColor();
964 unsigned uRegName = getUnifiedRegNum(RegClassID, LR->getColor());
967 std::cerr<< getUnifiedRegName(uRegName);
968 if (RegClassID == FloatRegClassID && LR->getType() == Type::DoubleTy)
969 std::cerr << "+" << getUnifiedRegName(uRegName+1);
973 } // End llvm namespace