1 //===-- SparcRegInfo.cpp - Sparc Target Register Information --------------===//
3 // This file contains implementation of Sparc specific helper methods
4 // used for register allocation.
6 //===----------------------------------------------------------------------===//
8 #include "SparcInternals.h"
9 #include "SparcRegClassInfo.h"
10 #include "llvm/Target/Sparc.h"
11 #include "llvm/CodeGen/MachineCodeForMethod.h"
12 #include "llvm/CodeGen/PhyRegAlloc.h"
13 #include "llvm/CodeGen/InstrSelection.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/CodeGen/MachineInstrAnnot.h"
16 #include "llvm/CodeGen/RegAllocCommon.h"
17 #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h"
18 #include "llvm/iTerminators.h"
19 #include "llvm/iOther.h"
20 #include "llvm/Function.h"
21 #include "llvm/DerivedTypes.h"
26 UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
27 : MachineRegInfo(tgt), UltraSparcInfo(&tgt), NumOfIntArgRegs(6),
28 NumOfFloatArgRegs(32), InvalidRegNum(1000) {
30 MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID));
31 MachineRegClassArr.push_back(new SparcFloatRegClass(FloatRegClassID));
32 MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID));
33 MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID));
35 assert(SparcFloatRegOrder::StartOfNonVolatileRegs == 32 &&
36 "32 Float regs are used for float arg passing");
40 // getZeroRegNum - returns the register that contains always zero.
41 // this is the unified register number
43 int UltraSparcRegInfo::getZeroRegNum() const {
44 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
45 SparcIntRegOrder::g0);
48 // getCallAddressReg - returns the reg used for pushing the address when a
49 // method is called. This can be used for other purposes between calls
51 unsigned UltraSparcRegInfo::getCallAddressReg() const {
52 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
53 SparcIntRegOrder::o7);
56 // Returns the register containing the return address.
57 // It should be made sure that this register contains the return
58 // value when a return instruction is reached.
60 unsigned UltraSparcRegInfo::getReturnAddressReg() const {
61 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
62 SparcIntRegOrder::i7);
65 // given the unified register number, this gives the name
66 // for generating assembly code or debugging.
68 const std::string UltraSparcRegInfo::getUnifiedRegName(int reg) const {
70 return SparcIntRegOrder::getRegName(reg);
71 else if ( reg < (64 + 32) )
72 return SparcFloatRegOrder::getRegName( reg - 32);
73 else if( reg < (64+32+4) )
74 return SparcFloatCCRegOrder::getRegName( reg -32 - 64);
75 else if( reg < (64+32+4+2) ) // two names: %xcc and %ccr
76 return SparcIntCCRegOrder::getRegName( reg -32 - 64 - 4);
77 else if (reg== InvalidRegNum) //****** TODO: Remove */
80 assert(0 && "Invalid register number");
84 // Get unified reg number for frame pointer
85 unsigned UltraSparcRegInfo::getFramePointer() const {
86 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
87 SparcIntRegOrder::i6);
90 // Get unified reg number for stack pointer
91 unsigned UltraSparcRegInfo::getStackPointer() const {
92 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
93 SparcIntRegOrder::o6);
97 //---------------------------------------------------------------------------
98 // Finds whether a call is an indirect call
99 //---------------------------------------------------------------------------
102 isVarArgsFunction(const Type *funcType) {
103 return cast<FunctionType>(cast<PointerType>(funcType)
104 ->getElementType())->isVarArg();
108 isVarArgsCall(const MachineInstr *CallMI) {
109 Value* callee = CallMI->getOperand(0).getVRegValue();
110 // const Type* funcType = isa<Function>(callee)? callee->getType()
111 // : cast<PointerType>(callee->getType())->getElementType();
112 const Type* funcType = callee->getType();
113 return isVarArgsFunction(funcType);
117 // Get the register number for the specified integer arg#,
118 // assuming there are argNum total args, intArgNum int args,
119 // and fpArgNum FP args preceding (and not including) this one.
120 // Use INT regs for FP args if this is a varargs call.
123 // InvalidRegNum, if there is no int register available for the arg.
124 // regNum, otherwise (this is NOT the unified reg. num).
127 UltraSparcRegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall,
129 unsigned intArgNo, unsigned fpArgNo,
130 unsigned& regClassId) const
132 regClassId = IntRegClassID;
133 if (argNo >= NumOfIntArgRegs)
134 return InvalidRegNum;
136 return argNo + (inCallee? SparcIntRegOrder::i0 : SparcIntRegOrder::o0);
139 // Get the register number for the specified FP arg#,
140 // assuming there are argNum total args, intArgNum int args,
141 // and fpArgNum FP args preceding (and not including) this one.
142 // Use INT regs for FP args if this is a varargs call.
145 // InvalidRegNum, if there is no int register available for the arg.
146 // regNum, otherwise (this is NOT the unified reg. num).
149 UltraSparcRegInfo::regNumForFPArg(unsigned regType,
150 bool inCallee, bool isVarArgsCall,
152 unsigned intArgNo, unsigned fpArgNo,
153 unsigned& regClassId) const
156 return regNumForIntArg(inCallee, isVarArgsCall, argNo, intArgNo, fpArgNo,
160 regClassId = FloatRegClassID;
161 if (regType == FPSingleRegType)
162 return (argNo*2+1 >= NumOfFloatArgRegs)?
163 InvalidRegNum : SparcFloatRegOrder::f0 + (argNo * 2 + 1);
164 else if (regType == FPDoubleRegType)
165 return (argNo*2 >= NumOfFloatArgRegs)?
166 InvalidRegNum : SparcFloatRegOrder::f0 + (argNo * 2);
168 assert(0 && "Illegal FP register type");
173 //---------------------------------------------------------------------------
174 // Finds the return address of a call sparc specific call instruction
175 //---------------------------------------------------------------------------
177 // The following 4 methods are used to find the RegType (see enum above)
178 // of a LiveRange, a Value, and for a given register unified reg number.
180 int UltraSparcRegInfo::getRegType(unsigned regClassID,
181 const Type* type) const {
182 switch (regClassID) {
183 case IntRegClassID: return IntRegType;
184 case FloatRegClassID: {
185 if (type == Type::FloatTy)
186 return FPSingleRegType;
187 else if (type == Type::DoubleTy)
188 return FPDoubleRegType;
189 assert(0 && "Unknown type in FloatRegClass");
191 case IntCCRegClassID: return IntCCRegType;
192 case FloatCCRegClassID: return FloatCCRegType;
193 default: assert( 0 && "Unknown reg class ID"); return 0;
197 int UltraSparcRegInfo::getRegType(const LiveRange *LR) const {
198 return getRegType(LR->getRegClass()->getID(), LR->getType());
201 int UltraSparcRegInfo::getRegType(const Value *Val) const {
202 return getRegType(getRegClassIDOfValue(Val), Val->getType());
205 int UltraSparcRegInfo::getRegType(int reg) const {
208 else if (reg < (32 + 32))
209 return FPSingleRegType;
210 else if (reg < (64 + 32))
211 return FPDoubleRegType;
212 else if (reg < (64+32+4))
213 return FloatCCRegType;
214 else if (reg < (64+32+4+2))
217 assert(0 && "Invalid register number in getRegType");
222 //---------------------------------------------------------------------------
223 // Suggests a register for the ret address in the RET machine instruction.
224 // We always suggest %i7 by convention.
225 //---------------------------------------------------------------------------
226 void UltraSparcRegInfo::suggestReg4RetAddr(const MachineInstr *RetMI,
227 LiveRangeInfo& LRI) const {
229 assert( (RetMI->getNumOperands() >= 2)
230 && "JMPL/RETURN must have 3 and 2 operands respectively");
232 MachineOperand & MO = ( MachineOperand &) RetMI->getOperand(0);
234 // return address is always mapped to i7
236 MO.setRegForValue( getUnifiedRegNum( IntRegClassID, SparcIntRegOrder::i7) );
238 // Possible Optimization:
239 // Instead of setting the color, we can suggest one. In that case,
240 // we have to test later whether it received the suggested color.
241 // In that case, a LR has to be created at the start of method.
242 // It has to be done as follows (remove the setRegVal above):
244 // const Value *RetAddrVal = MO.getVRegValue();
245 // assert( RetAddrVal && "LR for ret address must be created at start");
246 // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
247 // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
248 // SparcIntRegOrdr::i7) );
252 //---------------------------------------------------------------------------
253 // Suggests a register for the ret address in the JMPL/CALL machine instr.
254 // Sparc ABI dictates that %o7 be used for this purpose.
255 //---------------------------------------------------------------------------
256 void UltraSparcRegInfo::suggestReg4CallAddr(const MachineInstr * CallMI,
258 std::vector<RegClass *> RCList) const {
259 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
260 const Value *RetAddrVal = argDesc->getReturnAddrReg();
261 assert(RetAddrVal && "Return address value is required");
263 // create a new LR for the return address and color it
264 LiveRange * RetAddrLR = new LiveRange();
265 RetAddrLR->insert( RetAddrVal );
266 unsigned RegClassID = getRegClassIDOfValue( RetAddrVal );
267 RetAddrLR->setRegClass( RCList[RegClassID] );
268 RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o7));
269 LRI.addLRToMap( RetAddrVal, RetAddrLR);
276 //---------------------------------------------------------------------------
277 // This method will suggest colors to incoming args to a method.
278 // According to the Sparc ABI, the first 6 incoming args are in
279 // %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float).
280 // If the arg is passed on stack due to the lack of regs, NOTHING will be
281 // done - it will be colored (or spilled) as a normal live range.
282 //---------------------------------------------------------------------------
283 void UltraSparcRegInfo::suggestRegs4MethodArgs(const Function *Meth,
284 LiveRangeInfo& LRI) const
286 // check if this is a varArgs function. needed for choosing regs.
287 bool isVarArgs = isVarArgsFunction(Meth->getType());
289 // get the argument list
290 const Function::ArgumentListType& ArgList = Meth->getArgumentList();
292 // for each argument. count INT and FP arguments separately.
293 for( unsigned argNo=0, intArgNo=0, fpArgNo=0;
294 argNo != ArgList.size(); ++argNo)
297 LiveRange *LR = LRI.getLiveRangeForValue((const Value *)ArgList[argNo]);
298 assert( LR && "No live range found for method arg");
300 unsigned regType = getRegType( LR );
301 unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg (unused)
303 int regNum = (regType == IntRegType)
304 ? regNumForIntArg(/*inCallee*/ true, isVarArgs,
305 argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
306 : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs,
307 argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
309 if(regNum != InvalidRegNum)
310 LR->setSuggestedColor(regNum);
315 //---------------------------------------------------------------------------
316 // This method is called after graph coloring to move incoming args to
317 // the correct hardware registers if they did not receive the correct
318 // (suggested) color through graph coloring.
319 //---------------------------------------------------------------------------
320 void UltraSparcRegInfo::colorMethodArgs(const Function *Meth,
322 AddedInstrns *FirstAI) const {
324 // check if this is a varArgs function. needed for choosing regs.
325 bool isVarArgs = isVarArgsFunction(Meth->getType());
326 // get the argument list
327 const Function::ArgumentListType& ArgList = Meth->getArgumentList();
328 // get an iterator to arg list
332 for( unsigned argNo=0, intArgNo=0, fpArgNo=0;
333 argNo != ArgList.size(); ++argNo) {
335 LiveRange *LR = LRI.getLiveRangeForValue((Value*)ArgList[argNo]);
336 assert( LR && "No live range found for method arg");
338 unsigned regType = getRegType( LR );
339 unsigned RegClassID = (LR->getRegClass())->getID();
341 // Find whether this argument is coming in a register (if not, on stack)
342 // Also find the correct register the argument must use (UniArgReg)
344 bool isArgInReg = false;
345 unsigned UniArgReg = InvalidRegNum; // reg that LR MUST be colored with
346 unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg
348 int regNum = (regType == IntRegType)
349 ? regNumForIntArg(/*inCallee*/ true, isVarArgs,
350 argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
351 : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs,
352 argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
354 if(regNum != InvalidRegNum) {
356 UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum);
359 if( LR->hasColor() ) { // if this arg received a register
361 unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
363 // if LR received the correct color, nothing to do
365 if( UniLRReg == UniArgReg )
368 // We are here because the LR did not receive the suggested
369 // but LR received another register.
370 // Now we have to copy the %i reg (or stack pos of arg)
371 // to the register the LR was colored with.
373 // if the arg is coming in UniArgReg register, it MUST go into
374 // the UniLRReg register
377 if( regClassIDOfArgReg != RegClassID ) {
378 assert(0 && "This could should work but it is not tested yet");
380 // It is a variable argument call: the float reg must go in a %o reg.
381 // We have to move an int reg to a float reg via memory.
384 RegClassID == FloatRegClassID &&
385 regClassIDOfArgReg == IntRegClassID &&
386 "This should only be an Int register for an FP argument");
388 int TmpOff = MachineCodeForMethod::get(Meth).pushTempValue(target,
389 getSpilledRegSize(regType));
390 cpReg2MemMI(UniArgReg, getFramePointer(), TmpOff, IntRegType,
391 FirstAI->InstrnsBefore);
393 cpMem2RegMI(getFramePointer(), TmpOff, UniLRReg, regType,
394 FirstAI->InstrnsBefore);
397 cpReg2RegMI(UniArgReg, UniLRReg, regType, FirstAI->InstrnsBefore);
402 // Now the arg is coming on stack. Since the LR recieved a register,
403 // we just have to load the arg on stack into that register
405 const MachineFrameInfo& frameInfo = target.getFrameInfo();
407 frameInfo.getIncomingArgOffset(MachineCodeForMethod::get(Meth),
410 cpMem2RegMI(getFramePointer(), offsetFromFP, UniLRReg, regType,
411 FirstAI->InstrnsBefore);
414 } // if LR received a color
418 // Now, the LR did not receive a color. But it has a stack offset for
420 // So, if the arg is coming in UniArgReg register, we can just move
421 // that on to the stack pos of LR
425 if( regClassIDOfArgReg != RegClassID ) {
427 "FP arguments to a varargs function should be explicitly "
428 "copied to/from int registers by instruction selection!");
430 // It must be a float arg for a variable argument call, which
431 // must come in a %o reg. Move the int reg to the stack.
433 assert(isVarArgs && regClassIDOfArgReg == IntRegClassID &&
434 "This should only be an Int register for an FP argument");
436 cpReg2MemMI(UniArgReg, getFramePointer(), LR->getSpillOffFromFP(),
437 IntRegType, FirstAI->InstrnsBefore);
440 cpReg2MemMI(UniArgReg, getFramePointer(), LR->getSpillOffFromFP(),
441 regType, FirstAI->InstrnsBefore);
447 // Now the arg is coming on stack. Since the LR did NOT
448 // recieved a register as well, it is allocated a stack position. We
449 // can simply change the stack position of the LR. We can do this,
450 // since this method is called before any other method that makes
451 // uses of the stack pos of the LR (e.g., updateMachineInstr)
453 const MachineFrameInfo& frameInfo = target.getFrameInfo();
455 frameInfo.getIncomingArgOffset(MachineCodeForMethod::get(Meth),
458 LR->modifySpillOffFromFP( offsetFromFP );
463 } // for each incoming argument
469 //---------------------------------------------------------------------------
470 // This method is called before graph coloring to suggest colors to the
471 // outgoing call args and the return value of the call.
472 //---------------------------------------------------------------------------
473 void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *CallMI,
475 std::vector<RegClass *> RCList) const {
476 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
478 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
480 suggestReg4CallAddr(CallMI, LRI, RCList);
482 // First color the return value of the call instruction. The return value
483 // will be in %o0 if the value is an integer type, or in %f0 if the
484 // value is a float type.
486 // the return value cannot have a LR in machine instruction since it is
487 // only defined by the call instruction
489 // if type is not void, create a new live range and set its
490 // register class and add to LRI
492 const Value *RetVal = argDesc->getReturnValue();
495 assert ((!LRI.getLiveRangeForValue(RetVal)) &&
496 "LR for ret Value of call already definded!");
498 // create a new LR for the return value
499 LiveRange *RetValLR = new LiveRange();
500 RetValLR->insert(RetVal);
501 unsigned RegClassID = getRegClassIDOfValue(RetVal);
502 RetValLR->setRegClass(RCList[RegClassID]);
503 LRI.addLRToMap(RetVal, RetValLR);
505 // now suggest a register depending on the register class of ret arg
507 if( RegClassID == IntRegClassID )
508 RetValLR->setSuggestedColor(SparcIntRegOrder::o0);
509 else if (RegClassID == FloatRegClassID )
510 RetValLR->setSuggestedColor(SparcFloatRegOrder::f0 );
511 else assert( 0 && "Unknown reg class for return value of call\n");
515 // Now suggest colors for arguments (operands) of the call instruction.
516 // Colors are suggested only if the arg number is smaller than the
517 // the number of registers allocated for argument passing.
518 // Now, go thru call args - implicit operands of the call MI
520 unsigned NumOfCallArgs = argDesc->getNumArgs();
522 for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0;
523 i < NumOfCallArgs; ++i, ++argNo) {
525 const Value *CallArg = argDesc->getArgInfo(i).getArgVal();
527 // get the LR of call operand (parameter)
528 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
530 // not possible to have a null LR since all args (even consts)
531 // must be defined before
533 cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) << "\n";
534 assert(0 && "NO LR for call arg");
537 unsigned regType = getRegType( LR );
538 unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg (unused)
540 // Choose a register for this arg depending on whether it is
541 // an INT or FP value. Here we ignore whether or not it is a
542 // varargs calls, because FP arguments will be explicitly copied
543 // to an integer Value and handled under (argCopy != NULL) below.
544 int regNum = (regType == IntRegType)
545 ? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false,
546 argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
547 : regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false,
548 argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
550 // If a register could be allocated, use it.
551 // If not, do NOTHING as this will be colored as a normal value.
552 if(regNum != InvalidRegNum)
553 LR->setSuggestedColor(regNum);
555 // Repeat for the second copy of the argument, which would be
556 // an FP argument being passed to a function with no prototype
557 const Value *argCopy = argDesc->getArgInfo(i).getArgCopy();
560 assert(regType != IntRegType && argCopy->getType()->isIntegral()
561 && "Must be passing copy of FP argument in int register");
562 int copyRegNum = regNumForIntArg(/*inCallee*/false, /*isVarArgs*/false,
563 argNo, intArgNo, fpArgNo-1,
565 assert(copyRegNum != InvalidRegNum);
566 LiveRange *const copyLR = LRI.getLiveRangeForValue(argCopy);
567 copyLR->setSuggestedColor(copyRegNum);
570 } // for all call arguments
575 //---------------------------------------------------------------------------
576 // Helper method for UltraSparcRegInfo::colorCallArgs().
577 //---------------------------------------------------------------------------
580 UltraSparcRegInfo::InitializeOutgoingArg(const MachineInstr* CallMI,
581 AddedInstrns *CallAI,
582 PhyRegAlloc &PRA, LiveRange* LR,
583 unsigned regType, unsigned RegClassID,
584 int UniArgRegOrNone, unsigned int argNo,
585 std::vector<MachineInstr *>& AddedInstrnsBefore)
589 bool isArgInReg = false;
590 unsigned UniArgReg = MAXINT; // unused unless initialized below
591 if (UniArgRegOrNone != InvalidRegNum)
594 UniArgReg = (unsigned) UniArgRegOrNone;
597 if (LR->hasColor()) {
598 unsigned UniLRReg = getUnifiedRegNum(RegClassID, LR->getColor());
600 // if LR received the correct color, nothing to do
601 if( isArgInReg && UniArgReg == UniLRReg )
604 // The LR is allocated to a register UniLRReg and must be copied
605 // to UniArgReg or to the stack slot.
608 // Copy UniLRReg to UniArgReg
609 cpReg2RegMI(UniLRReg, UniArgReg, regType, AddedInstrnsBefore);
612 // Copy UniLRReg to the stack to pass the arg on stack.
613 const MachineFrameInfo& frameInfo = target.getFrameInfo();
614 int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo);
615 cpReg2MemMI(UniLRReg, getStackPointer(), argOffset, regType,
616 CallAI->InstrnsBefore);
619 } else { // LR is not colored (i.e., spilled)
622 // Insert a load instruction to load the LR to UniArgReg
623 cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
624 UniArgReg, regType, AddedInstrnsBefore);
625 // Now add the instruction
629 // Now, we have to pass the arg on stack. Since LR also did NOT
630 // receive a register we have to move an argument in memory to
631 // outgoing parameter on stack.
632 // Use TReg to load and store the value.
633 // Use TmpOff to save TReg, since that may have a live value.
635 int TReg = PRA.getUniRegNotUsedByThisInst( LR->getRegClass(), CallMI );
636 int TmpOff = PRA.mcInfo.pushTempValue(target,
637 getSpilledRegSize(getRegType(LR)));
638 const MachineFrameInfo& frameInfo = target.getFrameInfo();
639 int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo);
641 MachineInstr *Ad1, *Ad2, *Ad3, *Ad4;
644 // (1) Save TReg on stack
645 // (2) Load LR value into TReg from stack pos of LR
646 // (3) Store Treg on outgoing Arg pos on stack
647 // (4) Load the old value of TReg from stack to TReg (restore it)
650 // When reverse pointers in MahineInstr are introduced:
651 // Call PRA.getUnusedRegAtMI(....) to get an unused reg. Step 1 is
652 // needed only if this fails. Currently, we cannot call the
653 // above method since we cannot find LVSetBefore without the BB
655 // NOTE: We directly add to CallAI->InstrnsBefore instead of adding to
656 // AddedInstrnsBefore since these instructions must not be reordered.
657 cpReg2MemMI(TReg, getFramePointer(), TmpOff, regType,
658 CallAI->InstrnsBefore);
659 cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(), TReg, regType,
660 CallAI->InstrnsBefore);
661 cpReg2MemMI(TReg, getStackPointer(), argOffset, regType,
662 CallAI->InstrnsBefore);
663 cpMem2RegMI(getFramePointer(), TmpOff, TReg, regType,
664 CallAI->InstrnsBefore);
669 //---------------------------------------------------------------------------
670 // After graph coloring, we have call this method to see whehter the return
671 // value and the call args received the correct colors. If not, we have
672 // to instert copy instructions.
673 //---------------------------------------------------------------------------
675 void UltraSparcRegInfo::colorCallArgs(const MachineInstr *CallMI,
677 AddedInstrns *CallAI,
679 const BasicBlock *BB) const {
681 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
683 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
685 // First color the return value of the call.
686 // If there is a LR for the return value, it means this
687 // method returns a value
691 const Value *RetVal = argDesc->getReturnValue();
694 LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal );
697 cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
698 assert(RetValLR && "ERR:No LR for non-void return value");
701 unsigned RegClassID = (RetValLR->getRegClass())->getID();
702 bool recvCorrectColor = false;
704 unsigned CorrectCol; // correct color for ret value
705 if(RegClassID == IntRegClassID)
706 CorrectCol = SparcIntRegOrder::o0;
707 else if(RegClassID == FloatRegClassID)
708 CorrectCol = SparcFloatRegOrder::f0;
710 assert( 0 && "Unknown RegClass");
714 // if the LR received the correct color, NOTHING to do
716 if( RetValLR->hasColor() )
717 if( RetValLR->getColor() == CorrectCol )
718 recvCorrectColor = true;
721 // if we didn't receive the correct color for some reason,
722 // put copy instruction
724 if( !recvCorrectColor ) {
726 unsigned regType = getRegType( RetValLR );
728 // the reg that LR must be colored with
729 unsigned UniRetReg = getUnifiedRegNum( RegClassID, CorrectCol);
731 if( RetValLR->hasColor() ) {
734 UniRetLRReg=getUnifiedRegNum(RegClassID,RetValLR->getColor());
736 // the return value is coming in UniRetReg but has to go into
739 cpReg2RegMI(UniRetReg, UniRetLRReg, regType, CallAI->InstrnsAfter);
744 // if the LR did NOT receive a color, we have to move the return
745 // value coming in UniRetReg to the stack pos of spilled LR
747 cpReg2MemMI(UniRetReg, getFramePointer(),RetValLR->getSpillOffFromFP(),
748 regType, CallAI->InstrnsAfter);
751 } // the LR didn't receive the suggested color
753 } // if there a return value
756 //-------------------------------------------
757 // Now color all args of the call instruction
758 //-------------------------------------------
760 std::vector<MachineInstr *> AddedInstrnsBefore;
762 unsigned NumOfCallArgs = argDesc->getNumArgs();
764 for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0;
765 i < NumOfCallArgs; ++i, ++argNo) {
767 const Value *CallArg = argDesc->getArgInfo(i).getArgVal();
769 // get the LR of call operand (parameter)
770 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
772 unsigned RegClassID = getRegClassIDOfValue( CallArg);
773 unsigned regType = getRegType( RegClassID, CallArg->getType() );
775 // Find whether this argument is coming in a register (if not, on stack)
776 // Also find the correct register the argument must use (UniArgReg)
778 bool isArgInReg = false;
779 unsigned UniArgReg = InvalidRegNum; // reg that LR MUST be colored with
780 unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg
782 // Find the register that must be used for this arg, depending on
783 // whether it is an INT or FP value. Here we ignore whether or not it
784 // is a varargs calls, because FP arguments will be explicitly copied
785 // to an integer Value and handled under (argCopy != NULL) below.
786 int regNum = (regType == IntRegType)
787 ? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false,
788 argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
789 : regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false,
790 argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
792 if(regNum != InvalidRegNum) {
794 UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum);
795 assert(regClassIDOfArgReg == RegClassID &&
796 "Moving values between reg classes must happen during selection");
799 // not possible to have a null LR since all args (even consts)
800 // must be defined before
802 cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) <<"\n";
803 assert(LR && "NO LR for call arg");
806 InitializeOutgoingArg(CallMI, CallAI, PRA, LR, regType, RegClassID,
807 UniArgReg, argNo, AddedInstrnsBefore);
809 // Repeat for the second copy of the argument, which would be
810 // an FP argument being passed to a function with no prototype.
811 const Value *argCopy = argDesc->getArgInfo(i).getArgCopy();
814 assert(regType != IntRegType && argCopy->getType()->isIntegral()
815 && "Must be passing copy of FP argument in int register");
817 unsigned copyRegClassID = getRegClassIDOfValue(argCopy);
818 unsigned copyRegType = getRegType(copyRegClassID, argCopy->getType());
820 int copyRegNum = regNumForIntArg(/*inCallee*/false, /*isVarArgs*/false,
821 argNo, intArgNo, fpArgNo-1,
823 assert(copyRegNum != InvalidRegNum);
824 assert(regClassIDOfArgReg == copyRegClassID &&
825 "Moving values between reg classes must happen during selection");
827 InitializeOutgoingArg(CallMI, CallAI, PRA,
828 LRI.getLiveRangeForValue(argCopy), copyRegType,
829 copyRegClassID, copyRegNum, argNo,
832 } // for each parameter in call instruction
834 // If we added any instruction before the call instruction, verify
835 // that they are in the proper order and if not, reorder them
837 if (!AddedInstrnsBefore.empty()) {
840 cerr << "\nCalling reorder with instrns: \n";
841 for(unsigned i=0; i < AddedInstrnsBefore.size(); i++)
842 cerr << *(AddedInstrnsBefore[i]);
845 std::vector<MachineInstr *> TmpVec;
846 OrderAddedInstrns(AddedInstrnsBefore, TmpVec, PRA);
849 cerr << "\nAfter reordering instrns: \n";
850 for(unsigned i = 0; i < TmpVec.size(); i++)
854 // copy the results back from TmpVec to InstrnsBefore
855 for(unsigned i=0; i < TmpVec.size(); i++)
856 CallAI->InstrnsBefore.push_back( TmpVec[i] );
859 // now insert caller saving code for this call instruction
861 insertCallerSavingCode(CallMI, BB, PRA);
864 //---------------------------------------------------------------------------
865 // This method is called for an LLVM return instruction to identify which
866 // values will be returned from this method and to suggest colors.
867 //---------------------------------------------------------------------------
868 void UltraSparcRegInfo::suggestReg4RetValue(const MachineInstr *RetMI,
869 LiveRangeInfo &LRI) const {
871 assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) );
873 suggestReg4RetAddr(RetMI, LRI);
875 // if there is an implicit ref, that has to be the ret value
876 if( RetMI->getNumImplicitRefs() > 0 ) {
878 // The first implicit operand is the return value of a return instr
879 const Value *RetVal = RetMI->getImplicitRef(0);
881 LiveRange *const LR = LRI.getLiveRangeForValue( RetVal );
884 cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
885 assert(0 && "No LR for return value of non-void method");
888 unsigned RegClassID = (LR->getRegClass())->getID();
890 if (RegClassID == IntRegClassID)
891 LR->setSuggestedColor(SparcIntRegOrder::i0);
892 else if (RegClassID == FloatRegClassID)
893 LR->setSuggestedColor(SparcFloatRegOrder::f0);
899 //---------------------------------------------------------------------------
900 // Colors the return value of a method to %i0 or %f0, if possible. If it is
901 // not possilbe to directly color the LR, insert a copy instruction to move
902 // the LR to %i0 or %f0. When the LR is spilled, instead of the copy, we
903 // have to put a load instruction.
904 //---------------------------------------------------------------------------
905 void UltraSparcRegInfo::colorRetValue(const MachineInstr *RetMI,
907 AddedInstrns *RetAI) const {
909 assert((UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode()));
911 // if there is an implicit ref, that has to be the ret value
912 if(RetMI->getNumImplicitRefs() > 0) {
914 // The first implicit operand is the return value of a return instr
915 const Value *RetVal = RetMI->getImplicitRef(0);
917 LiveRange *LR = LRI.getLiveRangeForValue(RetVal);
920 cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
921 // assert( LR && "No LR for return value of non-void method");
925 unsigned RegClassID = getRegClassIDOfValue(RetVal);
926 unsigned regType = getRegType( RetVal );
929 if(RegClassID == IntRegClassID)
930 CorrectCol = SparcIntRegOrder::i0;
931 else if(RegClassID == FloatRegClassID)
932 CorrectCol = SparcFloatRegOrder::f0;
934 assert (0 && "Unknown RegClass");
938 // if the LR received the correct color, NOTHING to do
940 if (LR->hasColor() && LR->getColor() == CorrectCol)
943 unsigned UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
945 if (LR->hasColor()) {
947 // We are here because the LR was allocted a regiter
948 // It may be the suggested register or not
950 // copy the LR of retun value to i0 or f0
952 unsigned UniLRReg =getUnifiedRegNum( RegClassID, LR->getColor());
954 // the LR received UniLRReg but must be colored with UniRetReg
955 // to pass as the return value
956 cpReg2RegMI(UniLRReg, UniRetReg, regType, RetAI->InstrnsBefore);
958 else { // if the LR is spilled
959 cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
960 UniRetReg, regType, RetAI->InstrnsBefore);
961 cerr << "\nCopied the return value from stack\n";
964 } // if there is a return value
969 //---------------------------------------------------------------------------
970 // Copy from a register to register. Register number must be the unified
972 //---------------------------------------------------------------------------
975 UltraSparcRegInfo::cpReg2RegMI(unsigned SrcReg,
978 vector<MachineInstr*>& mvec) const {
979 assert( ((int)SrcReg != InvalidRegNum) && ((int)DestReg != InvalidRegNum) &&
982 MachineInstr * MI = NULL;
988 assert(0 && "This code was bogus and needs to be fixed!");
992 MI = new MachineInstr(ADD, 3);
993 MI->SetMachineOperandReg(0, SrcReg, false);
994 MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
995 MI->SetMachineOperandReg(2, DestReg, true);
998 case FPSingleRegType:
999 MI = new MachineInstr(FMOVS, 2);
1000 MI->SetMachineOperandReg(0, SrcReg, false);
1001 MI->SetMachineOperandReg(1, DestReg, true);
1004 case FPDoubleRegType:
1005 MI = new MachineInstr(FMOVD, 2);
1006 MI->SetMachineOperandReg(0, SrcReg, false);
1007 MI->SetMachineOperandReg(1, DestReg, true);
1011 assert(0 && "Unknown RegType");
1018 //---------------------------------------------------------------------------
1019 // Copy from a register to memory (i.e., Store). Register number must
1020 // be the unified register number
1021 //---------------------------------------------------------------------------
1025 UltraSparcRegInfo::cpReg2MemMI(unsigned SrcReg,
1026 unsigned DestPtrReg,
1027 int Offset, int RegType,
1028 vector<MachineInstr*>& mvec) const {
1029 MachineInstr * MI = NULL;
1032 case FloatCCRegType:
1033 MI = new MachineInstr(STX, 3);
1034 MI->SetMachineOperandReg(0, SrcReg, false);
1035 MI->SetMachineOperandReg(1, DestPtrReg, false);
1036 MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
1040 case FPSingleRegType:
1041 MI = new MachineInstr(ST, 3);
1042 MI->SetMachineOperandReg(0, SrcReg, false);
1043 MI->SetMachineOperandReg(1, DestPtrReg, false);
1044 MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
1048 case FPDoubleRegType:
1049 MI = new MachineInstr(STD, 3);
1050 MI->SetMachineOperandReg(0, SrcReg, false);
1051 MI->SetMachineOperandReg(1, DestPtrReg, false);
1052 MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
1057 assert( 0 && "Cannot directly store %ccr to memory");
1060 assert(0 && "Unknown RegType in cpReg2MemMI");
1068 //---------------------------------------------------------------------------
1069 // Copy from memory to a reg (i.e., Load) Register number must be the unified
1071 //---------------------------------------------------------------------------
1075 UltraSparcRegInfo::cpMem2RegMI(unsigned SrcPtrReg,
1079 vector<MachineInstr*>& mvec) const {
1080 MachineInstr * MI = NULL;
1083 case FloatCCRegType:
1084 MI = new MachineInstr(LDX, 3);
1085 MI->SetMachineOperandReg(0, SrcPtrReg, false);
1086 MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
1088 MI->SetMachineOperandReg(2, DestReg, true);
1091 case FPSingleRegType:
1092 MI = new MachineInstr(LD, 3);
1093 MI->SetMachineOperandReg(0, SrcPtrReg, false);
1094 MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
1096 MI->SetMachineOperandReg(2, DestReg, true);
1100 case FPDoubleRegType:
1101 MI = new MachineInstr(LDD, 3);
1102 MI->SetMachineOperandReg(0, SrcPtrReg, false);
1103 MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
1105 MI->SetMachineOperandReg(2, DestReg, true);
1109 assert( 0 && "Cannot directly load into %ccr from memory");
1112 assert(0 && "Unknown RegType in cpMem2RegMI");
1120 //---------------------------------------------------------------------------
1121 // Generate a copy instruction to copy a value to another. Temporarily
1122 // used by PhiElimination code.
1123 //---------------------------------------------------------------------------
1127 UltraSparcRegInfo::cpValue2Value(Value *Src,
1129 vector<MachineInstr*>& mvec) const {
1130 int RegType = getRegType( Src );
1132 assert( (RegType==getRegType(Src)) && "Src & Dest are diff types");
1134 MachineInstr * MI = NULL;
1138 MI = new MachineInstr(ADD, 3);
1139 MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
1140 MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
1141 MI->SetMachineOperandVal(2, MachineOperand:: MO_VirtualRegister, Dest, true);
1144 case FPSingleRegType:
1145 MI = new MachineInstr(FMOVS, 2);
1146 MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
1147 MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true);
1151 case FPDoubleRegType:
1152 MI = new MachineInstr(FMOVD, 2);
1153 MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
1154 MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true);
1158 assert(0 && "Unknow RegType in CpValu2Value");
1170 //----------------------------------------------------------------------------
1171 // This method inserts caller saving/restoring instructons before/after
1172 // a call machine instruction. The caller saving/restoring instructions are
1175 // ** caller saving instructions
1176 // other instructions inserted for the call by ColorCallArg
1178 // other instructions inserted for the call ColorCallArg
1179 // ** caller restoring instructions
1181 //----------------------------------------------------------------------------
1184 void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *CallMI,
1185 const BasicBlock *BB,
1186 PhyRegAlloc &PRA) const {
1188 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
1190 // has set to record which registers were saved/restored
1192 std::hash_set<unsigned> PushedRegSet;
1194 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
1196 // Now find the LR of the return value of the call
1197 // The last *implicit operand* is the return value of a call
1198 // Insert it to to he PushedRegSet since we must not save that register
1199 // and restore it after the call.
1200 // We do this because, we look at the LV set *after* the instruction
1201 // to determine, which LRs must be saved across calls. The return value
1202 // of the call is live in this set - but we must not save/restore it.
1204 const Value *RetVal = argDesc->getReturnValue();
1207 LiveRange *RetValLR = PRA.LRI.getLiveRangeForValue( RetVal );
1208 assert(RetValLR && "No LR for RetValue of call");
1210 if (RetValLR->hasColor())
1211 PushedRegSet.insert(
1212 getUnifiedRegNum((RetValLR->getRegClass())->getID(),
1213 RetValLR->getColor() ) );
1217 const ValueSet &LVSetAft = PRA.LVI->getLiveVarSetAfterMInst(CallMI, BB);
1218 ValueSet::const_iterator LIt = LVSetAft.begin();
1220 // for each live var in live variable set after machine inst
1221 for( ; LIt != LVSetAft.end(); ++LIt) {
1223 // get the live range corresponding to live var
1224 LiveRange *const LR = PRA.LRI.getLiveRangeForValue(*LIt );
1226 // LR can be null if it is a const since a const
1227 // doesn't have a dominating def - see Assumptions above
1230 if( LR->hasColor() ) {
1232 unsigned RCID = (LR->getRegClass())->getID();
1233 unsigned Color = LR->getColor();
1235 if ( isRegVolatile(RCID, Color) ) {
1237 // if the value is in both LV sets (i.e., live before and after
1238 // the call machine instruction)
1240 unsigned Reg = getUnifiedRegNum(RCID, Color);
1242 if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
1244 // if we haven't already pushed that register
1246 unsigned RegType = getRegType( LR );
1248 // Now get two instructions - to push on stack and pop from stack
1249 // and add them to InstrnsBefore and InstrnsAfter of the
1253 int StackOff = PRA.mcInfo.pushTempValue(target,
1254 getSpilledRegSize(RegType));
1257 MachineInstr *AdIBefCC=NULL, *AdIAftCC=NULL, *AdICpCC;
1258 MachineInstr *AdIBef=NULL, *AdIAft=NULL;
1260 //---- Insert code for pushing the reg on stack ----------
1262 if( RegType == IntCCRegType ) {
1264 // Handle IntCCRegType specially since we cannot directly
1265 // push %ccr on to the stack
1267 const ValueSet &LVSetBef =
1268 PRA.LVI->getLiveVarSetBeforeMInst(CallMI, BB);
1270 // get a free INTEGER register
1272 PRA.getUsableUniRegAtMI(PRA.getRegClassByID(IntRegClassID) /*LR->getRegClass()*/,
1273 IntRegType, CallMI, &LVSetBef, AdIBefCC, AdIAftCC);
1275 // insert the instructions in reverse order since we are
1276 // adding them to the front of InstrnsBefore
1277 AddedInstrns& addedI = PRA.AddedInstrMap[CallMI];
1279 addedI.InstrnsBefore.insert(addedI.InstrnsBefore.begin(),
1282 AdICpCC = cpCCR2IntMI(FreeIntReg);
1283 addedI.InstrnsBefore.insert(addedI.InstrnsBefore.begin(),
1287 addedI.InstrnsBefore.insert(addedI.InstrnsBefore.begin(),
1291 cerr << "\n!! Inserted caller saving (push) inst for %ccr:";
1292 if(AdIBefCC) cerr << "\t" << *(AdIBefCC);
1293 cerr << "\t" << *AdICpCC;
1294 if(AdIAftCC) cerr << "\t" << *(AdIAftCC);
1298 // for any other register type, just add the push inst
1299 cpReg2MemMI(Reg, getFramePointer(), StackOff, RegType,
1300 PRA.AddedInstrMap[CallMI].InstrnsBefore);
1304 //---- Insert code for popping the reg from the stack ----------
1306 if (RegType == IntCCRegType) {
1308 // Handle IntCCRegType specially since we cannot directly
1309 // pop %ccr on from the stack
1311 // get a free INT register
1313 PRA.getUsableUniRegAtMI(PRA.getRegClassByID(IntRegClassID) /* LR->getRegClass()*/,
1314 IntRegType, CallMI, &LVSetAft, AdIBefCC, AdIAftCC);
1317 PRA.AddedInstrMap[CallMI].InstrnsAfter.push_back(AdIBefCC);
1319 AdICpCC = cpInt2CCRMI(FreeIntReg);
1320 PRA.AddedInstrMap[CallMI].InstrnsAfter.push_back(AdICpCC);
1323 PRA.AddedInstrMap[CallMI].InstrnsAfter.push_back(AdIAftCC);
1327 cerr << "\n!! Inserted caller saving (pop) inst for %ccr:";
1328 if(AdIBefCC) cerr << "\t" << *(AdIBefCC);
1329 cerr << "\t" << *AdICpCC;
1330 if(AdIAftCC) cerr << "\t" << *(AdIAftCC);
1334 // for any other register type, just add the pop inst
1335 cpMem2RegMI(getFramePointer(), StackOff, Reg, RegType,
1336 PRA.AddedInstrMap[CallMI].InstrnsAfter);
1339 PushedRegSet.insert(Reg);
1342 cerr << "\nFor call inst:" << *CallMI;
1343 cerr << " -inserted caller saving instrs:\n\t ";
1344 if( RegType == IntCCRegType ) {
1345 if(AdIBefCC) cerr << *AdIBefCC << "\t";
1346 if(AdIAftCC) cerr << *AdIAftCC;
1349 if(AdIBef) cerr << *AdIBef << "\t";
1350 if(AdIAft) cerr << *AdIAft;
1353 } // if not already pushed
1355 } // if LR has a volatile color
1357 } // if LR has color
1359 } // if there is a LR for Var
1361 } // for each value in the LV set after instruction
1365 //---------------------------------------------------------------------------
1366 // Copies %ccr into an integer register. IntReg is the UNIFIED register
1368 //---------------------------------------------------------------------------
1370 MachineInstr * UltraSparcRegInfo::cpCCR2IntMI(unsigned IntReg) const {
1371 MachineInstr * MI = new MachineInstr(RDCCR, 2);
1372 MI->SetMachineOperandReg(0, this->getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID,
1373 SparcIntCCRegOrder::ccr),
1375 MI->SetMachineOperandReg(1, IntReg, true);
1379 //---------------------------------------------------------------------------
1380 // Copies an integer register into %ccr. IntReg is the UNIFIED register
1382 //---------------------------------------------------------------------------
1384 MachineInstr *UltraSparcRegInfo::cpInt2CCRMI(unsigned IntReg) const {
1385 MachineInstr *MI = new MachineInstr(WRCCR, 3);
1386 MI->SetMachineOperandReg(0, IntReg, false);
1387 MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
1388 MI->SetMachineOperandReg(2, this->getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID, SparcIntCCRegOrder::ccr),
1396 //---------------------------------------------------------------------------
1397 // Print the register assigned to a LR
1398 //---------------------------------------------------------------------------
1400 void UltraSparcRegInfo::printReg(const LiveRange *LR) {
1401 unsigned RegClassID = (LR->getRegClass())->getID();
1402 cerr << " *Node " << (LR->getUserIGNode())->getIndex();
1404 if (!LR->hasColor()) {
1405 cerr << " - could not find a color\n";
1409 // if a color is found
1411 cerr << " colored with color "<< LR->getColor();
1413 if (RegClassID == IntRegClassID) {
1414 cerr<< " [" << SparcIntRegOrder::getRegName(LR->getColor()) << "]\n";
1416 } else if (RegClassID == FloatRegClassID) {
1417 cerr << "[" << SparcFloatRegOrder::getRegName(LR->getColor());
1418 if( LR->getType() == Type::DoubleTy)
1419 cerr << "+" << SparcFloatRegOrder::getRegName(LR->getColor()+1);
1424 //---------------------------------------------------------------------------
1425 // This method examines instructions inserted by RegAlloc code before a
1426 // machine instruction to detect invalid orders that destroy values before
1427 // they are used. If it detects such conditions, it reorders the instructions.
1429 // The unordered instructions come in the UnordVec. These instructions are
1430 // instructions inserted by RegAlloc. All such instruction MUST have
1431 // their USES BEFORE THE DEFS after reordering.
1433 // The UnordVec & OrdVec must be DISTINCT. The OrdVec must be empty when
1434 // this method is called.
1436 // This method uses two vectors for efficiency in accessing
1438 // Since instructions are inserted in RegAlloc, this assumes that the
1439 // first operand is the source reg and the last operand is the dest reg.
1441 // All the uses are before THE def to a register
1442 //---------------------------------------------------------------------------
1444 void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr*> &UnordVec,
1445 std::vector<MachineInstr*> &OrdVec,
1446 PhyRegAlloc &PRA) const{
1449 Problem: We can have instructions inserted by RegAlloc like
1451 2. add %oy %g0 %oz, where z!=x or z==x
1453 This is wrong since %oy used by 2 is overwritten by 1
1456 We re-order the instructions so that the uses are before the defs
1461 for each instruction 'DefInst' in the UnOrdVec
1462 for each instruction 'UseInst' that follows the DefInst
1463 if the reg defined by DefInst is used by UseInst
1464 mark DefInst as not movable in this iteration
1465 If DefInst is not marked as not-movable, move DefInst to OrdVec
1466 while all instructions in DefInst are moved to OrdVec
1468 For moving, we call the move2OrdVec(). It checks whether there is a def
1469 in it for the uses in the instruction to be added to OrdVec. If there
1470 are no preceding defs, it just appends the instruction. If there is a
1471 preceding def, it puts two instructions to save the reg on stack before
1472 the load and puts a restore at use.
1477 bool DebugPrint = false;
1480 CouldMoveAll = true;
1481 std::vector<MachineInstr *>::iterator DefIt = UnordVec.begin();
1483 for( ; DefIt != UnordVec.end(); ++DefIt ) {
1485 // for each instruction in the UnordVec do ...
1487 MachineInstr *DefInst = *DefIt;
1489 if( DefInst == NULL) continue;
1491 //cerr << "\nInst in UnordVec = " << *DefInst;
1493 // last operand is the def (unless for a store which has no def reg)
1494 MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
1496 if( DefOp.opIsDef() &&
1497 DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1499 // If the operand in DefInst is a def ...
1501 bool DefEqUse = false;
1503 std::vector<MachineInstr *>::iterator UseIt = DefIt;
1506 for( ; UseIt != UnordVec.end(); ++UseIt ) {
1508 MachineInstr *UseInst = *UseIt;
1509 if( UseInst == NULL) continue;
1511 // for each inst (UseInst) that is below the DefInst do ...
1512 MachineOperand& UseOp = UseInst->getOperand(0);
1514 if( ! UseOp.opIsDef() &&
1515 UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1517 // if use is a register ...
1519 if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
1521 // if Def and this use are the same, it means that this use
1522 // is destroyed by a def before it is used
1524 // cerr << "\nCouldn't move " << *DefInst;
1527 CouldMoveAll = false;
1530 } // if two registers are equal
1532 } // if use is a register
1534 }// for all use instructions
1538 // after examining all the instructions that follow the DefInst
1539 // if there are no dependencies, we can move it to the OrdVec
1541 // cerr << "Moved to Ord: " << *DefInst;
1543 moveInst2OrdVec(OrdVec, DefInst, PRA);
1545 //OrdVec.push_back(DefInst);
1547 // mark the pos of DefInst with NULL to indicate that it is
1552 } // if Def is a machine register
1554 } // for all instructions in the UnordVec
1557 } while(!CouldMoveAll);
1560 cerr << "\nAdded instructions were reordered to:\n";
1561 for(unsigned int i=0; i < OrdVec.size(); i++)
1562 cerr << *(OrdVec[i]);
1570 void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
1571 MachineInstr *UnordInst,
1572 PhyRegAlloc &PRA) const {
1573 MachineOperand& UseOp = UnordInst->getOperand(0);
1575 if( ! UseOp.opIsDef() &&
1576 UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1578 // for the use of UnordInst, see whether there is a defining instr
1579 // before in the OrdVec
1580 bool DefEqUse = false;
1582 std::vector<MachineInstr *>::iterator OrdIt = OrdVec.begin();
1584 for( ; OrdIt != OrdVec.end(); ++OrdIt ) {
1586 MachineInstr *OrdInst = *OrdIt ;
1588 MachineOperand& DefOp =
1589 OrdInst->getOperand(OrdInst->getNumOperands()-1);
1591 if( DefOp.opIsDef() &&
1592 DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1594 //cerr << "\nDefining Ord Inst: " << *OrdInst;
1596 if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
1598 // we are here because there is a preceding def in the OrdVec
1599 // for the use in this intr we are going to insert. This
1600 // happened because the original code was like:
1601 // 1. add %ox %g0 %oy
1602 // 2. add %oy %g0 %ox
1603 // In Round1, we added 2 to OrdVec but 1 remained in UnordVec
1604 // Now we are processing %ox of 1.
1607 const int UReg = DefOp.getMachineRegNum();
1608 const int RegType = getRegType(UReg);
1609 MachineInstr *AdIBef, *AdIAft;
1611 const int StackOff = PRA.mcInfo.pushTempValue(target,
1612 getSpilledRegSize(RegType));
1614 // Save the UReg (%ox) on stack before it's destroyed
1615 vector<MachineInstr*> mvec;
1616 cpReg2MemMI(UReg, getFramePointer(), StackOff, RegType, mvec);
1617 for (vector<MachineInstr*>::iterator MI=mvec.begin(); MI != mvec.end(); ++MI) {
1618 OrdIt = OrdVec.insert(OrdIt, *MI);
1619 ++OrdIt; // OrdIt must still point to current instr we processed
1622 // Load directly into DReg (%oy)
1623 MachineOperand& DOp=
1624 (UnordInst->getOperand(UnordInst->getNumOperands()-1));
1625 assert(DOp.opIsDef() && "Last operand is not the def");
1626 const int DReg = DOp.getMachineRegNum();
1628 cpMem2RegMI(getFramePointer(), StackOff, DReg, RegType, OrdVec);
1630 cerr << "\nFixed CIRCULAR references by reordering";
1633 cerr << "\nBefore CIRCULAR Reordering:\n";
1637 cerr << "\nAfter CIRCULAR Reordering - All Inst so far:\n";
1638 for(unsigned i=0; i < OrdVec.size(); i++)
1639 cerr << *(OrdVec[i]);
1642 // Do not copy the UseInst to OrdVec
1646 }// if two registers are equal
1648 } // if Def is a register
1650 } // for each instr in OrdVec
1654 // We didn't find a def in the OrdVec, so just append this inst
1655 OrdVec.push_back( UnordInst );
1656 //cerr << "Reordered Inst (Moved Dn): " << *UnordInst;
1659 }// if the operand in UnordInst is a use