1 //===-- SparcRegInfo.cpp - Sparc Target Register Information --------------===//
3 // This file contains implementation of Sparc specific helper methods
4 // used for register allocation.
6 //===----------------------------------------------------------------------===//
8 #include "llvm/Target/Sparc.h"
9 #include "SparcInternals.h"
10 #include "llvm/Method.h"
11 #include "llvm/iTerminators.h"
12 #include "llvm/iOther.h"
13 #include "llvm/CodeGen/InstrSelection.h"
14 #include "llvm/CodeGen/MachineCodeForMethod.h"
15 #include "llvm/CodeGen/PhyRegAlloc.h"
16 #include "llvm/DerivedTypes.h"
20 //---------------------------------------------------------------------------
21 // Finds the return value of a sparc specific call instruction
22 //---------------------------------------------------------------------------
24 UltraSparcRegInfo::getCallInstRetVal(const MachineInstr *CallMI) const {
25 unsigned OpCode = CallMI->getOpCode();
26 unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
30 // The one before the last implicit operand is the return value of
33 if( NumOfImpRefs > 1 )
34 if( CallMI->implicitRefIsDefined(NumOfImpRefs-2) )
35 return CallMI->getImplicitRef(NumOfImpRefs-2);
37 } else if (OpCode == JMPLCALL) {
39 // The last implicit operand is the return value of a JMPL
42 if (CallMI->implicitRefIsDefined(NumOfImpRefs-1))
43 return CallMI->getImplicitRef(NumOfImpRefs-1);
46 assert(0 && "OpCode must be CALL/JMPL for a call instr");
53 //---------------------------------------------------------------------------
54 // Finds the return address of a call sparc specific call instruction
55 //---------------------------------------------------------------------------
57 UltraSparcRegInfo::getCallInstRetAddr(const MachineInstr *CallMI)const {
59 unsigned OpCode = CallMI->getOpCode();
63 unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
65 assert( NumOfImpRefs && "CALL instr must have at least on ImpRef");
67 // The last implicit operand is the return address of a CALL instr
69 return CallMI->getImplicitRef(NumOfImpRefs-1);
72 else if( OpCode == JMPLCALL ) {
74 MachineOperand & MO = ( MachineOperand &) CallMI->getOperand(2);
75 return MO.getVRegValue();
79 assert(0 && "OpCode must be CALL/JMPL for a call instr");
81 assert(0 && "There must be a return addr for a call instr");
88 //---------------------------------------------------------------------------
89 // Finds the # of actual arguments of the call instruction
90 //---------------------------------------------------------------------------
92 UltraSparcRegInfo::getCallInstNumArgs(const MachineInstr *CallMI) const {
94 unsigned OpCode = CallMI->getOpCode();
95 unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
98 if( OpCode == CALL ) {
100 switch( NumOfImpRefs ) {
102 case 0: assert(0 && "A CALL inst must have at least one ImpRef (RetAddr)");
107 default: // two or more implicit refs
108 if( CallMI->implicitRefIsDefined(NumOfImpRefs-2) )
109 NumArgs = NumOfImpRefs - 2; // i.e., NumOfImpRef-2 is the ret val
111 NumArgs = NumOfImpRefs - 1;
115 else if( OpCode == JMPLCALL ) {
117 // The last implicit operand is the return value of a JMPL instr
118 if( NumOfImpRefs > 0 ) {
119 if( CallMI->implicitRefIsDefined(NumOfImpRefs-1) )
120 NumArgs = NumOfImpRefs - 1; // i.e., NumOfImpRef-1 is the ret val
122 NumArgs = NumOfImpRefs;
125 NumArgs = NumOfImpRefs;
128 assert(0 && "OpCode must be CALL/JMPL for a call instr");
130 assert( (NumArgs != -1) && "Internal error in getCallInstNumArgs" );
131 return (unsigned) NumArgs;
136 //---------------------------------------------------------------------------
137 // Finds whether a call is an indirect call
138 //---------------------------------------------------------------------------
139 bool UltraSparcRegInfo::isVarArgCall(const MachineInstr *CallMI) const {
141 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
143 const MachineOperand & calleeOp = CallMI->getOperand(0);
144 Value *calleeVal = calleeOp.getVRegValue();
146 PointerType *PT = cast<PointerType> (calleeVal->getType());
147 MethodType *MT = cast<MethodType>(PT->getElementType());
149 return MT->isVarArg();
155 //---------------------------------------------------------------------------
156 // Suggests a register for the ret address in the RET machine instruction.
157 // We always suggest %i7 by convention.
158 //---------------------------------------------------------------------------
159 void UltraSparcRegInfo::suggestReg4RetAddr(const MachineInstr * RetMI,
160 LiveRangeInfo& LRI) const {
162 assert( (RetMI->getNumOperands() >= 2)
163 && "JMPL/RETURN must have 3 and 2 operands respectively");
165 MachineOperand & MO = ( MachineOperand &) RetMI->getOperand(0);
167 // return address is always mapped to i7
169 MO.setRegForValue( getUnifiedRegNum( IntRegClassID, SparcIntRegOrder::i7) );
171 // Possible Optimization:
172 // Instead of setting the color, we can suggest one. In that case,
173 // we have to test later whether it received the suggested color.
174 // In that case, a LR has to be created at the start of method.
175 // It has to be done as follows (remove the setRegVal above):
177 // const Value *RetAddrVal = MO.getVRegValue();
178 // assert( RetAddrVal && "LR for ret address must be created at start");
179 // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
180 // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
181 // SparcIntRegOrdr::i7) );
185 //---------------------------------------------------------------------------
186 // Suggests a register for the ret address in the JMPL/CALL machine instr.
187 // Sparc ABI dictates that %o7 be used for this purpose.
188 //---------------------------------------------------------------------------
189 void UltraSparcRegInfo::suggestReg4CallAddr(const MachineInstr * CallMI,
191 std::vector<RegClass *> RCList) const {
194 const Value *RetAddrVal = getCallInstRetAddr( CallMI );
196 // RetAddrVal cannot be NULL (asserted in getCallInstRetAddr)
197 // create a new LR for the return address and color it
199 LiveRange * RetAddrLR = new LiveRange();
200 RetAddrLR->add( RetAddrVal );
201 unsigned RegClassID = getRegClassIDOfValue( RetAddrVal );
202 RetAddrLR->setRegClass( RCList[RegClassID] );
203 RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o7));
204 LRI.addLRToMap( RetAddrVal, RetAddrLR);
211 //---------------------------------------------------------------------------
212 // This method will suggest colors to incoming args to a method.
213 // According to the Sparc ABI, the first 6 incoming args are in
214 // %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float).
215 // If the arg is passed on stack due to the lack of regs, NOTHING will be
216 // done - it will be colored (or spilled) as a normal live range.
217 //---------------------------------------------------------------------------
218 void UltraSparcRegInfo::suggestRegs4MethodArgs(const Method *const Meth,
219 LiveRangeInfo& LRI) const
222 // get the argument list
223 const Method::ArgumentListType& ArgList = Meth->getArgumentList();
224 // get an iterator to arg list
225 Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
228 for( unsigned argNo=0; ArgIt != ArgList.end() ; ++ArgIt, ++argNo) {
231 LiveRange *const LR = LRI.getLiveRangeForValue((const Value *) *ArgIt);
232 assert( LR && "No live range found for method arg");
234 unsigned RegType = getRegType( LR );
237 // if the arg is in int class - allocate a reg for an int arg
239 if( RegType == IntRegType ) {
241 if( argNo < NumOfIntArgRegs) {
242 LR->setSuggestedColor( SparcIntRegOrder::i0 + argNo );
245 // Do NOTHING as this will be colored as a normal value.
246 if (DEBUG_RA) cerr << " Int Regr not suggested for method arg\n";
250 else if( RegType==FPSingleRegType && (argNo*2+1) < NumOfFloatArgRegs)
251 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2 + 1) );
254 else if( RegType == FPDoubleRegType && (argNo*2) < NumOfFloatArgRegs)
255 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2) );
262 //---------------------------------------------------------------------------
263 // This method is called after graph coloring to move incoming args to
264 // the correct hardware registers if they did not receive the correct
265 // (suggested) color through graph coloring.
266 //---------------------------------------------------------------------------
267 void UltraSparcRegInfo::colorMethodArgs(const Method *const Meth,
269 AddedInstrns *const FirstAI) const {
271 // get the argument list
272 const Method::ArgumentListType& ArgList = Meth->getArgumentList();
273 // get an iterator to arg list
274 Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
280 for( unsigned argNo=0; ArgIt != ArgList.end() ; ++ArgIt, ++argNo) {
283 LiveRange *const LR = LRI.getLiveRangeForValue((const Value *) *ArgIt);
284 assert( LR && "No live range found for method arg");
287 unsigned RegType = getRegType( LR );
288 unsigned RegClassID = (LR->getRegClass())->getID();
290 // Find whether this argument is coming in a register (if not, on stack)
291 // Also find the correct register that the argument must go (UniArgReg)
293 bool isArgInReg = false;
294 unsigned UniArgReg = InvalidRegNum; // reg that LR MUST be colored with
296 if( (RegType== IntRegType && argNo < NumOfIntArgRegs)) {
298 UniArgReg = getUnifiedRegNum( RegClassID, SparcIntRegOrder::i0 + argNo );
300 else if(RegType == FPSingleRegType && argNo < NumOfFloatArgRegs) {
302 UniArgReg = getUnifiedRegNum( RegClassID,
303 SparcFloatRegOrder::f0 + argNo*2 + 1 ) ;
305 else if(RegType == FPDoubleRegType && argNo < NumOfFloatArgRegs) {
307 UniArgReg = getUnifiedRegNum(RegClassID, SparcFloatRegOrder::f0+argNo*2);
311 if( LR->hasColor() ) { // if this arg received a register
313 unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
315 // if LR received the correct color, nothing to do
317 if( UniLRReg == UniArgReg )
320 // We are here because the LR did not receive the suggested
321 // but LR received another register.
322 // Now we have to copy the %i reg (or stack pos of arg)
323 // to the register the LR was colored with.
325 // if the arg is coming in UniArgReg register, it MUST go into
326 // the UniLRReg register
329 AdMI = cpReg2RegMI( UniArgReg, UniLRReg, RegType );
333 // Now the arg is coming on stack. Since the LR recieved a register,
334 // we just have to load the arg on stack into that register
336 const MachineFrameInfo& frameInfo = target.getFrameInfo();
337 assert(frameInfo.argsOnStackHaveFixedSize());
339 bool growUp; // find the offset of arg in stack frame
341 frameInfo.getFirstIncomingArgOffset(MachineCodeForMethod::get(Meth),
344 growUp? firstArg + argNo * frameInfo.getSizeOfEachArgOnStack()
345 : firstArg - argNo * frameInfo.getSizeOfEachArgOnStack();
347 AdMI = cpMem2RegMI(getFramePointer(), offsetFromFP,
351 FirstAI->InstrnsBefore.push_back( AdMI );
353 } // if LR received a color
357 // Now, the LR did not receive a color. But it has a stack offset for
359 // So, if the arg is coming in UniArgReg register, we can just move
360 // that on to the stack pos of LR
363 cpReg2MemMI(UniArgReg, getFramePointer(),
364 LR->getSpillOffFromFP(), RegType );
366 FirstAI->InstrnsBefore.push_back( AdMI );
371 // Now the arg is coming on stack. Since the LR did NOT
372 // recieved a register as well, it is allocated a stack position. We
373 // can simply change the stack poistion of the LR. We can do this,
374 // since this method is called before any other method that makes
375 // uses of the stack pos of the LR (e.g., updateMachineInstr)
377 const MachineFrameInfo& frameInfo = target.getFrameInfo();
378 assert(frameInfo.argsOnStackHaveFixedSize());
381 int firstArg = frameInfo.getFirstIncomingArgOffset(MachineCodeForMethod::get(Meth), growUp);
383 growUp? firstArg + argNo * frameInfo.getSizeOfEachArgOnStack()
384 : firstArg - argNo * frameInfo.getSizeOfEachArgOnStack();
386 LR->modifySpillOffFromFP( offsetFromFP );
391 } // for each incoming argument
398 //---------------------------------------------------------------------------
399 // This method is called before graph coloring to suggest colors to the
400 // outgoing call args and the return value of the call.
401 //---------------------------------------------------------------------------
402 void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *const CallMI,
404 std::vector<RegClass *> RCList) const {
406 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
408 suggestReg4CallAddr(CallMI, LRI, RCList);
411 // First color the return value of the call instruction. The return value
412 // will be in %o0 if the value is an integer type, or in %f0 if the
413 // value is a float type.
415 // the return value cannot have a LR in machine instruction since it is
416 // only defined by the call instruction
418 // if type is not void, create a new live range and set its
419 // register class and add to LRI
422 const Value *RetVal = getCallInstRetVal( CallMI );
427 assert( (! LRI.getLiveRangeForValue( RetVal ) ) &&
428 "LR for ret Value of call already definded!");
431 // create a new LR for the return value
433 LiveRange * RetValLR = new LiveRange();
434 RetValLR->add( RetVal );
435 unsigned RegClassID = getRegClassIDOfValue( RetVal );
436 RetValLR->setRegClass( RCList[RegClassID] );
437 LRI.addLRToMap( RetVal, RetValLR);
439 // now suggest a register depending on the register class of ret arg
441 if( RegClassID == IntRegClassID )
442 RetValLR->setSuggestedColor(SparcIntRegOrder::o0);
443 else if (RegClassID == FloatRegClassID )
444 RetValLR->setSuggestedColor(SparcFloatRegOrder::f0 );
445 else assert( 0 && "Unknown reg class for return value of call\n");
450 // Now suggest colors for arguments (operands) of the call instruction.
451 // Colors are suggested only if the arg number is smaller than the
452 // the number of registers allocated for argument passing.
453 // Now, go thru call args - implicit operands of the call MI
455 unsigned NumOfCallArgs = getCallInstNumArgs( CallMI );
457 for(unsigned argNo=0, i=0; i < NumOfCallArgs; ++i, ++argNo ) {
459 const Value *CallArg = CallMI->getImplicitRef(i);
461 // get the LR of call operand (parameter)
462 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
464 // not possible to have a null LR since all args (even consts)
465 // must be defined before
468 cerr << " ERROR: In call instr, no LR for arg: " ;
469 printValue(CallArg); cerr << "\n";
471 assert(0 && "NO LR for call arg");
475 unsigned RegType = getRegType( LR );
477 // if the arg is in int class - allocate a reg for an int arg
478 if( RegType == IntRegType ) {
480 if( argNo < NumOfIntArgRegs)
481 LR->setSuggestedColor( SparcIntRegOrder::o0 + argNo );
484 // Do NOTHING as this will be colored as a normal value.
485 cerr << " Regr not suggested for int call arg\n";
488 else if( RegType == FPSingleRegType && (argNo*2 +1)< NumOfFloatArgRegs)
489 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2 + 1) );
492 else if( RegType == FPDoubleRegType && (argNo*2) < NumOfFloatArgRegs)
493 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2) );
496 } // for all call arguments
501 //---------------------------------------------------------------------------
502 // After graph coloring, we have call this method to see whehter the return
503 // value and the call args received the correct colors. If not, we have
504 // to instert copy instructions.
505 //---------------------------------------------------------------------------
507 void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
509 AddedInstrns *const CallAI,
511 const BasicBlock *BB) const {
513 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
515 // Reset the optional args area in the stack frame
516 // since that is reused for each call
518 PRA.mcInfo.resetOptionalArgs(target);
520 // First color the return value of the call.
521 // If there is a LR for the return value, it means this
522 // method returns a value
526 const Value *RetVal = getCallInstRetVal( CallMI );
530 LiveRange * RetValLR = LRI.getLiveRangeForValue( RetVal );
533 cerr << "\nNo LR for:";
534 printValue( RetVal );
536 assert( RetValLR && "ERR:No LR for non-void return value");
540 unsigned RegClassID = (RetValLR->getRegClass())->getID();
541 bool recvCorrectColor = false;
543 unsigned CorrectCol; // correct color for ret value
544 if(RegClassID == IntRegClassID)
545 CorrectCol = SparcIntRegOrder::o0;
546 else if(RegClassID == FloatRegClassID)
547 CorrectCol = SparcFloatRegOrder::f0;
549 assert( 0 && "Unknown RegClass");
553 // if the LR received the correct color, NOTHING to do
555 if( RetValLR->hasColor() )
556 if( RetValLR->getColor() == CorrectCol )
557 recvCorrectColor = true;
560 // if we didn't receive the correct color for some reason,
561 // put copy instruction
563 if( !recvCorrectColor ) {
565 unsigned RegType = getRegType( RetValLR );
567 // the reg that LR must be colored with
568 unsigned UniRetReg = getUnifiedRegNum( RegClassID, CorrectCol);
570 if( RetValLR->hasColor() ) {
573 UniRetLRReg=getUnifiedRegNum(RegClassID,RetValLR->getColor());
575 // the return value is coming in UniRetReg but has to go into
578 AdMI = cpReg2RegMI( UniRetReg, UniRetLRReg, RegType );
583 // if the LR did NOT receive a color, we have to move the return
584 // value coming in UniRetReg to the stack pos of spilled LR
586 AdMI = cpReg2MemMI(UniRetReg, getFramePointer(),
587 RetValLR->getSpillOffFromFP(), RegType );
590 CallAI->InstrnsAfter.push_back( AdMI );
592 } // the LR didn't receive the suggested color
594 } // if there a return value
597 //-------------------------------------------
598 // Now color all args of the call instruction
599 //-------------------------------------------
601 std::vector<MachineInstr *> AddedInstrnsBefore;
603 unsigned NumOfCallArgs = getCallInstNumArgs( CallMI );
605 bool VarArgCall = isVarArgCall( CallMI );
607 if(VarArgCall) cerr << "\nVar arg call found!!\n";
609 for(unsigned argNo=0, i=0; i < NumOfCallArgs; ++i, ++argNo ) {
611 const Value *CallArg = CallMI->getImplicitRef(i);
613 // get the LR of call operand (parameter)
614 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
616 unsigned RegType = getRegType( CallArg );
617 unsigned RegClassID = getRegClassIDOfValue( CallArg);
619 // find whether this argument is coming in a register (if not, on stack)
621 bool isArgInReg = false;
622 unsigned UniArgReg = InvalidRegNum; // reg that LR must be colored with
624 if( (RegType== IntRegType && argNo < NumOfIntArgRegs)) {
626 UniArgReg = getUnifiedRegNum(RegClassID, SparcIntRegOrder::o0 + argNo );
628 else if(RegType == FPSingleRegType && argNo < NumOfFloatArgRegs) {
632 UniArgReg = getUnifiedRegNum(RegClassID,
633 SparcFloatRegOrder::f0 + (argNo*2 + 1) );
635 // a variable argument call - must pass float arg in %o's
636 if( argNo < NumOfIntArgRegs)
637 UniArgReg=getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o0+argNo);
643 else if(RegType == FPDoubleRegType && argNo < NumOfFloatArgRegs) {
647 UniArgReg =getUnifiedRegNum(RegClassID,SparcFloatRegOrder::f0+argNo*2);
649 // a variable argument call - must pass float arg in %o's
650 if( argNo < NumOfIntArgRegs)
651 UniArgReg=getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o0+argNo);
657 // not possible to have a null LR since all args (even consts)
658 // must be defined before
661 cerr << " ERROR: In call instr, no LR for arg: " ;
662 printValue(CallArg); cerr << "\n";
664 assert(0 && "NO LR for call arg");
669 if( LR->hasColor() ) {
672 unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
674 // if LR received the correct color, nothing to do
675 if( UniLRReg == UniArgReg )
678 // We are here because though the LR is allocated a register, it
679 // was not allocated the suggested register. So, we have to copy %ix reg
680 // (or stack pos of arg) to the register it was colored with
682 // the LR is colored with UniLRReg but has to go into UniArgReg
683 // to pass it as an argument
687 if( VarArgCall && RegClassID == FloatRegClassID ) {
690 // for a variable argument call, the float reg must go in a %o reg.
691 // We have to move a float reg to an int reg via memory.
692 // The store instruction will be directly added to
693 // CallAI->InstrnsBefore since it does not need reordering
695 int TmpOff = PRA.mcInfo.pushTempValue(target,
696 getSpilledRegSize(RegType));
698 AdMI = cpReg2MemMI(UniLRReg, getFramePointer(), TmpOff, RegType );
699 CallAI->InstrnsBefore.push_back( AdMI );
701 AdMI = cpMem2RegMI(getFramePointer(), TmpOff, UniArgReg, IntRegType);
702 AddedInstrnsBefore.push_back( AdMI );
706 AdMI = cpReg2RegMI(UniLRReg, UniArgReg, RegType );
707 AddedInstrnsBefore.push_back( AdMI );
713 // Now, we have to pass the arg on stack. Since LR received a register
714 // we just have to move that register to the stack position where
715 // the argument must be passed
717 int argOffset = PRA.mcInfo.allocateOptionalArg(target, LR->getType());
719 AdMI = cpReg2MemMI(UniLRReg, getStackPointer(), argOffset, RegType );
721 // Now add the instruction. We can directly add to
722 // CallAI->InstrnsBefore since we are just saving a reg on stack
724 CallAI->InstrnsBefore.push_back( AdMI );
726 //cerr << "\nCaution: Passing a reg on stack";
732 else { // LR is not colored (i.e., spilled)
736 // Now the LR did NOT recieve a register but has a stack poistion.
737 // Since, the outgoing arg goes in a register we just have to insert
738 // a load instruction to load the LR to outgoing register
740 if( VarArgCall && RegClassID == FloatRegClassID )
741 AdMI = cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
742 UniArgReg, IntRegType );
744 AdMI = cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
745 UniArgReg, RegType );
747 cerr << "\nCaution: Loading a spilled val to a reg as a call arg";
748 AddedInstrnsBefore.push_back( AdMI ); // Now add the instruction
752 // Now, we have to pass the arg on stack. Since LR also did NOT
753 // receive a register we have to move an argument in memory to
754 // outgoing parameter on stack.
756 // Optoimize: Optimize when reverse pointers in MahineInstr are
758 // call PRA.getUnusedRegAtMI(....) to get an unused reg. Only if this
759 // fails, then use the following code. Currently, we cannot call the
760 // above method since we cannot find LVSetBefore without the BB
762 int TReg = PRA.getUniRegNotUsedByThisInst( LR->getRegClass(), CallMI );
764 int TmpOff = PRA.mcInfo.pushTempValue(target,
765 getSpilledRegSize(getRegType(LR)) );
768 int argOffset = PRA.mcInfo.allocateOptionalArg(target, LR->getType());
770 MachineInstr *Ad1, *Ad2, *Ad3, *Ad4;
773 // (1) Save TReg on stack
774 // (2) Load LR value into TReg from stack pos of LR
775 // (3) Store Treg on outgoing Arg pos on stack
776 // (4) Load the old value of TReg from stack to TReg (restore it)
778 Ad1 = cpReg2MemMI(TReg, getFramePointer(), TmpOff, RegType );
779 Ad2 = cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
781 Ad3 = cpReg2MemMI(TReg, getStackPointer(), argOffset, RegType );
782 Ad4 = cpMem2RegMI(getFramePointer(), TmpOff, TReg, RegType );
784 // We directly add to CallAI->InstrnsBefore instead of adding to
785 // AddedInstrnsBefore since these instructions must not be
788 CallAI->InstrnsBefore.push_back( Ad1 );
789 CallAI->InstrnsBefore.push_back( Ad2 );
790 CallAI->InstrnsBefore.push_back( Ad3 );
791 CallAI->InstrnsBefore.push_back( Ad4 );
793 cerr << "\nCaution: Call arg moved from stack2stack for: " << *CallMI ;
798 } // for each parameter in call instruction
801 // if we added any instruction before the call instruction, verify
802 // that they are in the proper order and if not, reorder them
804 if( ! AddedInstrnsBefore.empty() ) {
807 cerr << "\nCalling reorder with instrns: \n";
808 for(unsigned i=0; i < AddedInstrnsBefore.size(); i++)
809 cerr << *(AddedInstrnsBefore[i]);
812 std::vector<MachineInstr *> TmpVec;
813 OrderAddedInstrns(AddedInstrnsBefore, TmpVec, PRA);
816 cerr << "\nAfter reordering instrns: \n";
817 for(unsigned i=0; i < TmpVec.size(); i++)
818 cerr << *(TmpVec[i]);
821 // copy the results back from TmpVec to InstrnsBefore
822 for(unsigned i=0; i < TmpVec.size(); i++)
823 CallAI->InstrnsBefore.push_back( TmpVec[i] );
827 // now insert caller saving code for this call instruction
829 insertCallerSavingCode(CallMI, BB, PRA);
832 // Reset optional args area again to be safe
833 PRA.mcInfo.resetOptionalArgs(target);
838 //---------------------------------------------------------------------------
839 // This method is called for an LLVM return instruction to identify which
840 // values will be returned from this method and to suggest colors.
841 //---------------------------------------------------------------------------
842 void UltraSparcRegInfo::suggestReg4RetValue(const MachineInstr *const RetMI,
843 LiveRangeInfo& LRI) const {
845 assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) );
847 suggestReg4RetAddr(RetMI, LRI);
849 // if there is an implicit ref, that has to be the ret value
850 if( RetMI->getNumImplicitRefs() > 0 ) {
852 // The first implicit operand is the return value of a return instr
853 const Value *RetVal = RetMI->getImplicitRef(0);
855 LiveRange *const LR = LRI.getLiveRangeForValue( RetVal );
858 cerr << "\nNo LR for:";
859 printValue( RetVal );
861 assert( LR && "No LR for return value of non-void method");
865 unsigned RegClassID = (LR->getRegClass())->getID();
867 if( RegClassID == IntRegClassID )
868 LR->setSuggestedColor(SparcIntRegOrder::i0);
870 else if ( RegClassID == FloatRegClassID )
871 LR->setSuggestedColor(SparcFloatRegOrder::f0);
879 //---------------------------------------------------------------------------
880 // Colors the return value of a method to %i0 or %f0, if possible. If it is
881 // not possilbe to directly color the LR, insert a copy instruction to move
882 // the LR to %i0 or %f0. When the LR is spilled, instead of the copy, we
883 // have to put a load instruction.
884 //---------------------------------------------------------------------------
885 void UltraSparcRegInfo::colorRetValue(const MachineInstr *const RetMI,
887 AddedInstrns *const RetAI) const {
889 assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) );
891 // if there is an implicit ref, that has to be the ret value
892 if( RetMI->getNumImplicitRefs() > 0 ) {
894 // The first implicit operand is the return value of a return instr
895 const Value *RetVal = RetMI->getImplicitRef(0);
897 LiveRange *const LR = LRI.getLiveRangeForValue( RetVal );
900 cerr << "\nNo LR for:";
901 printValue( RetVal );
903 // assert( LR && "No LR for return value of non-void method");
907 unsigned RegClassID = getRegClassIDOfValue(RetVal);
908 unsigned RegType = getRegType( RetVal );
911 if(RegClassID == IntRegClassID)
912 CorrectCol = SparcIntRegOrder::i0;
913 else if(RegClassID == FloatRegClassID)
914 CorrectCol = SparcFloatRegOrder::f0;
916 assert( 0 && "Unknown RegClass");
920 // if the LR received the correct color, NOTHING to do
923 if( LR->getColor() == CorrectCol )
926 unsigned UniRetReg = getUnifiedRegNum( RegClassID, CorrectCol );
928 if( LR->hasColor() ) {
930 // We are here because the LR was allocted a regiter
931 // It may be the suggested register or not
933 // copy the LR of retun value to i0 or f0
935 unsigned UniLRReg =getUnifiedRegNum( RegClassID, LR->getColor());
937 // the LR received UniLRReg but must be colored with UniRetReg
938 // to pass as the return value
939 RetAI->InstrnsBefore.push_back(cpReg2RegMI(UniLRReg, UniRetReg, RegType));
941 else { // if the LR is spilled
942 MachineInstr *AdMI = cpMem2RegMI(getFramePointer(),
943 LR->getSpillOffFromFP(),
945 RetAI->InstrnsBefore.push_back(AdMI);
946 cerr << "\nCopied the return value from stack\n";
949 } // if there is a return value
954 //---------------------------------------------------------------------------
955 // Copy from a register to register. Register number must be the unified
957 //---------------------------------------------------------------------------
959 MachineInstr * UltraSparcRegInfo::cpReg2RegMI(const unsigned SrcReg,
960 const unsigned DestReg,
961 const int RegType) const {
963 assert( ((int)SrcReg != InvalidRegNum) && ((int)DestReg != InvalidRegNum) &&
966 MachineInstr * MI = NULL;
973 MI = new MachineInstr(ADD, 3);
974 MI->SetMachineOperand(0, SrcReg, false);
975 MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
976 MI->SetMachineOperand(2, DestReg, true);
979 case FPSingleRegType:
980 MI = new MachineInstr(FMOVS, 2);
981 MI->SetMachineOperand(0, SrcReg, false);
982 MI->SetMachineOperand(1, DestReg, true);
985 case FPDoubleRegType:
986 MI = new MachineInstr(FMOVD, 2);
987 MI->SetMachineOperand(0, SrcReg, false);
988 MI->SetMachineOperand(1, DestReg, true);
992 assert(0 && "Unknow RegType");
999 //---------------------------------------------------------------------------
1000 // Copy from a register to memory (i.e., Store). Register number must
1001 // be the unified register number
1002 //---------------------------------------------------------------------------
1005 MachineInstr * UltraSparcRegInfo::cpReg2MemMI(const unsigned SrcReg,
1006 const unsigned DestPtrReg,
1008 const int RegType) const {
1011 MachineInstr * MI = NULL;
1016 case FloatCCRegType:
1017 MI = new MachineInstr(STX, 3);
1018 MI->SetMachineOperand(0, SrcReg, false);
1019 MI->SetMachineOperand(1, DestPtrReg, false);
1020 MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
1021 (int64_t) Offset, false);
1024 case FPSingleRegType:
1025 MI = new MachineInstr(ST, 3);
1026 MI->SetMachineOperand(0, SrcReg, false);
1027 MI->SetMachineOperand(1, DestPtrReg, false);
1028 MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
1029 (int64_t) Offset, false);
1032 case FPDoubleRegType:
1033 MI = new MachineInstr(STD, 3);
1034 MI->SetMachineOperand(0, SrcReg, false);
1035 MI->SetMachineOperand(1, DestPtrReg, false);
1036 MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
1037 (int64_t) Offset, false);
1041 assert( 0 && "Cannot directly store %ccr to memory");
1044 assert(0 && "Unknow RegType in cpReg2MemMI");
1051 //---------------------------------------------------------------------------
1052 // Copy from memory to a reg (i.e., Load) Register number must be the unified
1054 //---------------------------------------------------------------------------
1057 MachineInstr * UltraSparcRegInfo::cpMem2RegMI(const unsigned SrcPtrReg,
1059 const unsigned DestReg,
1060 const int RegType) const {
1062 MachineInstr * MI = NULL;
1067 case FloatCCRegType:
1068 MI = new MachineInstr(LDX, 3);
1069 MI->SetMachineOperand(0, SrcPtrReg, false);
1070 MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,
1071 (int64_t) Offset, false);
1072 MI->SetMachineOperand(2, DestReg, true);
1075 case FPSingleRegType:
1076 MI = new MachineInstr(LD, 3);
1077 MI->SetMachineOperand(0, SrcPtrReg, false);
1078 MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,
1079 (int64_t) Offset, false);
1080 MI->SetMachineOperand(2, DestReg, true);
1084 case FPDoubleRegType:
1085 MI = new MachineInstr(LDD, 3);
1086 MI->SetMachineOperand(0, SrcPtrReg, false);
1087 MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,
1088 (int64_t) Offset, false);
1089 MI->SetMachineOperand(2, DestReg, true);
1093 assert( 0 && "Cannot directly load into %ccr from memory");
1096 assert(0 && "Unknown RegType in cpMem2RegMI");
1106 //---------------------------------------------------------------------------
1107 // Generate a copy instruction to copy a value to another. Temporarily
1108 // used by PhiElimination code.
1109 //---------------------------------------------------------------------------
1112 MachineInstr * UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest) const{
1114 int RegType = getRegType( Src );
1116 assert( (RegType==getRegType(Src)) && "Src & Dest are diff types");
1118 MachineInstr * MI = NULL;
1124 MI = new MachineInstr(ADD, 3);
1125 MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
1126 MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
1127 MI->SetMachineOperand(2, MachineOperand:: MO_VirtualRegister, Dest, true);
1130 case FPSingleRegType:
1131 MI = new MachineInstr(FMOVS, 2);
1132 MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
1133 MI->SetMachineOperand(1, MachineOperand:: MO_VirtualRegister, Dest, true);
1137 case FPDoubleRegType:
1138 MI = new MachineInstr(FMOVD, 2);
1139 MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
1140 MI->SetMachineOperand(1, MachineOperand:: MO_VirtualRegister, Dest, true);
1144 assert(0 && "Unknow RegType in CpValu2Value");
1155 //----------------------------------------------------------------------------
1156 // This method inserts caller saving/restoring instructons before/after
1157 // a call machine instruction. The caller saving/restoring instructions are
1160 // ** caller saving instructions
1161 // other instructions inserted for the call by ColorCallArg
1163 // other instructions inserted for the call ColorCallArg
1164 // ** caller restoring instructions
1166 //----------------------------------------------------------------------------
1169 void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *MInst,
1170 const BasicBlock *BB,
1171 PhyRegAlloc &PRA) const {
1173 // has set to record which registers were saved/restored
1175 std::hash_set<unsigned> PushedRegSet;
1177 // Now find the LR of the return value of the call
1178 // The last *implicit operand* is the return value of a call
1179 // Insert it to to he PushedRegSet since we must not save that register
1180 // and restore it after the call.
1181 // We do this because, we look at the LV set *after* the instruction
1182 // to determine, which LRs must be saved across calls. The return value
1183 // of the call is live in this set - but we must not save/restore it.
1186 const Value *RetVal = getCallInstRetVal( MInst );
1190 LiveRange *RetValLR = PRA.LRI.getLiveRangeForValue( RetVal );
1191 assert( RetValLR && "No LR for RetValue of call");
1193 if( RetValLR->hasColor())
1194 PushedRegSet.insert(
1195 getUnifiedRegNum((RetValLR->getRegClass())->getID(),
1196 RetValLR->getColor() ) );
1200 const LiveVarSet *LVSetAft = PRA.LVI->getLiveVarSetAfterMInst(MInst, BB);
1202 LiveVarSet::const_iterator LIt = LVSetAft->begin();
1204 // for each live var in live variable set after machine inst
1205 for( ; LIt != LVSetAft->end(); ++LIt) {
1207 // get the live range corresponding to live var
1208 LiveRange *const LR = PRA.LRI.getLiveRangeForValue(*LIt );
1210 // LR can be null if it is a const since a const
1211 // doesn't have a dominating def - see Assumptions above
1214 if( LR->hasColor() ) {
1216 unsigned RCID = (LR->getRegClass())->getID();
1217 unsigned Color = LR->getColor();
1219 if ( isRegVolatile(RCID, Color) ) {
1221 // if the value is in both LV sets (i.e., live before and after
1222 // the call machine instruction)
1224 unsigned Reg = getUnifiedRegNum(RCID, Color);
1226 if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
1228 // if we haven't already pushed that register
1230 unsigned RegType = getRegType( LR );
1232 // Now get two instructions - to push on stack and pop from stack
1233 // and add them to InstrnsBefore and InstrnsAfter of the
1237 int StackOff = PRA.mcInfo.pushTempValue(target,
1238 getSpilledRegSize(RegType));
1241 MachineInstr *AdIBefCC, *AdIAftCC, *AdICpCC;
1242 MachineInstr *AdIBef, *AdIAft;
1245 //---- Insert code for pushing the reg on stack ----------
1247 if( RegType == IntCCRegType ) {
1249 // Handle IntCCRegType specially since we cannot directly
1250 // push %ccr on to the stack
1252 const LiveVarSet *LVSetBef =
1253 PRA.LVI->getLiveVarSetBeforeMInst(MInst, BB);
1255 // get a free INTEGER register
1257 PRA.getUsableUniRegAtMI(LR->getRegClass(), IntRegType, MInst,
1258 LVSetBef, AdIBefCC, AdIAftCC);
1260 // insert the instructions in reverse order since we are
1261 // adding them to the front of InstrnsBefore
1264 (PRA.AddedInstrMap[MInst]->InstrnsBefore).push_front(AdIAftCC);
1266 AdICpCC = cpCCR2IntMI(FreeIntReg);
1267 (PRA.AddedInstrMap[MInst]->InstrnsBefore).push_front(AdICpCC);
1270 (PRA.AddedInstrMap[MInst]->InstrnsBefore).push_front(AdIBefCC);
1273 cerr << "\n!! Inserted caller saving (push) inst for %ccr:";
1274 if(AdIBefCC) cerr << "\t" << *(AdIBefCC);
1275 cerr << "\t" << *AdICpCC;
1276 if(AdIAftCC) cerr << "\t" << *(AdIAftCC);
1280 // for any other register type, just add the push inst
1281 AdIBef = cpReg2MemMI(Reg, getFramePointer(), StackOff, RegType );
1282 ((PRA.AddedInstrMap[MInst])->InstrnsBefore).push_front(AdIBef);
1286 //---- Insert code for popping the reg from the stack ----------
1288 if( RegType == IntCCRegType ) {
1290 // Handle IntCCRegType specially since we cannot directly
1291 // pop %ccr on from the stack
1293 // get a free INT register
1295 PRA.getUsableUniRegAtMI(LR->getRegClass(), IntRegType, MInst,
1296 LVSetAft, AdIBefCC, AdIAftCC);
1299 (PRA.AddedInstrMap[MInst]->InstrnsAfter).push_back(AdIBefCC);
1301 AdICpCC = cpInt2CCRMI(FreeIntReg);
1302 (PRA.AddedInstrMap[MInst]->InstrnsAfter).push_back(AdICpCC);
1305 (PRA.AddedInstrMap[MInst]->InstrnsAfter).push_back(AdIAftCC);
1309 cerr << "\n!! Inserted caller saving (pop) inst for %ccr:";
1310 if(AdIBefCC) cerr << "\t" << *(AdIBefCC);
1311 cerr << "\t" << *AdICpCC;
1312 if(AdIAftCC) cerr << "\t" << *(AdIAftCC);
1316 // for any other register type, just add the pop inst
1317 AdIAft = cpMem2RegMI(getFramePointer(), StackOff, Reg, RegType );
1318 ((PRA.AddedInstrMap[MInst])->InstrnsAfter).push_back(AdIAft);
1321 PushedRegSet.insert( Reg );
1324 cerr << "\nFor call inst:" << *MInst;
1325 cerr << " -inserted caller saving instrs:\n\t ";
1326 if( RegType == IntCCRegType )
1327 cerr << *AdIBefCC << "\t" << *AdIAftCC ;
1329 cerr << *AdIBef << "\t" << *AdIAft ;
1331 } // if not already pushed
1333 } // if LR has a volatile color
1335 } // if LR has color
1337 } // if there is a LR for Var
1339 } // for each value in the LV set after instruction
1343 //---------------------------------------------------------------------------
1344 // Copies %ccr into an integer register. IntReg is the UNIFIED register
1346 //---------------------------------------------------------------------------
1348 MachineInstr * UltraSparcRegInfo::cpCCR2IntMI(const unsigned IntReg) const {
1349 MachineInstr * MI = NULL;
1351 MI = new MachineInstr(RDCCR, 2);
1352 MI->SetMachineOperand(0, SparcIntCCRegOrder::ccr, false);
1353 MI->SetMachineOperand(1, IntReg, true);
1358 //---------------------------------------------------------------------------
1359 // Copies an integer register into %ccr. IntReg is the UNIFIED register
1361 //---------------------------------------------------------------------------
1363 MachineInstr * UltraSparcRegInfo::cpInt2CCRMI(const unsigned IntReg) const {
1364 MachineInstr * MI = NULL;
1366 MI = new MachineInstr(WRCCR, 3);
1367 MI->SetMachineOperand(0, IntReg, false);
1368 MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
1369 MI->SetMachineOperand(2, SparcIntCCRegOrder::ccr, true);
1377 //---------------------------------------------------------------------------
1378 // Print the register assigned to a LR
1379 //---------------------------------------------------------------------------
1381 void UltraSparcRegInfo::printReg(const LiveRange *const LR) {
1383 unsigned RegClassID = (LR->getRegClass())->getID();
1385 cerr << " *Node " << (LR->getUserIGNode())->getIndex();
1387 if( ! LR->hasColor() ) {
1388 cerr << " - could not find a color\n";
1392 // if a color is found
1394 cerr << " colored with color "<< LR->getColor();
1396 if( RegClassID == IntRegClassID ) {
1397 cerr<< " [" << SparcIntRegOrder::getRegName(LR->getColor()) << "]\n";
1399 } else if ( RegClassID == FloatRegClassID) {
1400 cerr << "[" << SparcFloatRegOrder::getRegName(LR->getColor());
1401 if( LR->getTypeID() == Type::DoubleTyID )
1402 cerr << "+" << SparcFloatRegOrder::getRegName(LR->getColor()+1);
1407 //---------------------------------------------------------------------------
1408 // This method examines instructions inserted by RegAlloc code before a
1409 // machine instruction to detect invalid orders that destroy values before
1410 // they are used. If it detects such conditions, it reorders the instructions.
1412 // The unordered instructions come in the UnordVec. These instructions are
1413 // instructions inserted by RegAlloc. All such instruction MUST have
1414 // their USES BEFORE THE DEFS after reordering.
1416 // The UnordVec & OrdVec must be DISTINCT. The OrdVec must be empty when
1417 // this method is called.
1419 // This method uses two vectors for efficiency in accessing
1421 // Since instructions are inserted in RegAlloc, this assumes that the
1422 // first operand is the source reg and the last operand is the dest reg.
1424 // All the uses are before THE def to a register
1427 //---------------------------------------------------------------------------
1428 void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
1429 std::vector<MachineInstr *> &OrdVec,
1430 PhyRegAlloc &PRA) const{
1433 Problem: We can have instructions inserted by RegAlloc like
1435 2. add %oy %g0 %oz, where z!=x or z==x
1437 This is wrong since %oy used by 2 is overwritten by 1
1440 We re-order the instructions so that the uses are before the defs
1445 for each instruction 'DefInst' in the UnOrdVec
1446 for each instruction 'UseInst' that follows the DefInst
1447 if the reg defined by DefInst is used by UseInst
1448 mark DefInst as not movable in this iteration
1449 If DefInst is not marked as not-movable, move DefInst to OrdVec
1450 while all instructions in DefInst are moved to OrdVec
1452 For moving, we call the move2OrdVec(). It checks whether there is a def
1453 in it for the uses in the instruction to be added to OrdVec. If there
1454 are no preceding defs, it just appends the instruction. If there is a
1455 preceding def, it puts two instructions to save the reg on stack before
1456 the load and puts a restore at use.
1462 bool DebugPrint = false;
1466 CouldMoveAll = true;
1468 std::vector<MachineInstr *>::iterator DefIt = UnordVec.begin();
1470 for( ; DefIt != UnordVec.end(); ++DefIt ) {
1472 // for each instruction in the UnordVec do ...
1474 MachineInstr *DefInst = *DefIt;
1476 if( DefInst == NULL) continue;
1478 //cerr << "\nInst in UnordVec = " << *DefInst;
1480 // last operand is the def (unless for a store which has no def reg)
1481 MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
1483 if( DefOp.opIsDef() &&
1484 DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1486 // If the operand in DefInst is a def ...
1488 bool DefEqUse = false;
1490 std::vector<MachineInstr *>::iterator UseIt = DefIt;
1493 for( ; UseIt != UnordVec.end(); ++UseIt ) {
1495 MachineInstr *UseInst = *UseIt;
1496 if( UseInst == NULL) continue;
1498 // for each inst (UseInst) that is below the DefInst do ...
1501 MachineOperand& UseOp = UseInst->getOperand(0);
1503 if( ! UseOp.opIsDef() &&
1504 UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1506 // if use is a register ...
1508 if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
1510 // if Def and this use are the same, it means that this use
1511 // is destroyed by a def before it is used
1513 // cerr << "\nCouldn't move " << *DefInst;
1516 CouldMoveAll = false;
1519 } // if two registers are equal
1521 } // if use is a register
1523 }// for all use instructions
1527 // after examining all the instructions that follow the DefInst
1528 // if there are no dependencies, we can move it to the OrdVec
1530 // cerr << "Moved to Ord: " << *DefInst;
1532 moveInst2OrdVec(OrdVec, DefInst, PRA);
1534 //OrdVec.push_back(DefInst);
1536 // mark the pos of DefInst with NULL to indicate that it is
1541 } // if Def is a machine register
1543 } // for all instructions in the UnordVec
1546 } while( !CouldMoveAll);
1550 cerr << "\nAdded instructions were reordered to:\n";
1551 for(unsigned int i=0; i < OrdVec.size(); i++)
1552 cerr << *(OrdVec[i]);
1564 void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
1565 MachineInstr *UnordInst,
1566 PhyRegAlloc &PRA ) const {
1568 MachineOperand& UseOp = UnordInst->getOperand(0);
1570 if( ! UseOp.opIsDef() &&
1571 UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1573 // for the use of UnordInst, see whether there is a defining instr
1574 // before in the OrdVec
1575 bool DefEqUse = false;
1577 std::vector<MachineInstr *>::iterator OrdIt = OrdVec.begin();
1579 for( ; OrdIt != OrdVec.end(); ++OrdIt ) {
1581 MachineInstr *OrdInst = *OrdIt ;
1583 MachineOperand& DefOp =
1584 OrdInst->getOperand(OrdInst->getNumOperands()-1);
1586 if( DefOp.opIsDef() &&
1587 DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1589 //cerr << "\nDefining Ord Inst: " << *OrdInst;
1591 if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
1593 // we are here because there is a preceding def in the OrdVec
1594 // for the use in this intr we are going to insert. This
1595 // happened because the original code was like:
1596 // 1. add %ox %g0 %oy
1597 // 2. add %oy %g0 %ox
1598 // In Round1, we added 2 to OrdVec but 1 remained in UnordVec
1599 // Now we are processing %ox of 1.
1602 const int UReg = DefOp.getMachineRegNum();
1603 const int RegType = getRegType(UReg);
1604 MachineInstr *AdIBef, *AdIAft;
1606 const int StackOff = PRA.mcInfo.pushTempValue(target,
1607 getSpilledRegSize(RegType));
1609 // Save the UReg (%ox) on stack before it's destroyed
1610 AdIBef=cpReg2MemMI(UReg, getFramePointer(), StackOff, RegType);
1611 OrdIt = OrdVec.insert( OrdIt, AdIBef);
1612 OrdIt++; // points to current instr we processed
1614 // Load directly into DReg (%oy)
1615 MachineOperand& DOp=
1616 (UnordInst->getOperand(UnordInst->getNumOperands()-1));
1617 assert(DOp.opIsDef() && "Last operand is not the def");
1618 const int DReg = DOp.getMachineRegNum();
1620 AdIAft=cpMem2RegMI(getFramePointer(), StackOff, DReg, RegType);
1621 OrdVec.push_back(AdIAft);
1623 cerr << "\nFixed CIRCULAR references by reordering";
1626 cerr << "\nBefore CIRCULAR Reordering:\n";
1630 cerr << "\nAfter CIRCULAR Reordering - All Inst so far:\n";
1631 for(unsigned i=0; i < OrdVec.size(); i++)
1632 cerr << *(OrdVec[i]);
1635 // Do not copy the UseInst to OrdVec
1639 }// if two registers are equal
1641 } // if Def is a register
1643 } // for each instr in OrdVec
1647 // We didn't find a def in the OrdVec, so just append this inst
1648 OrdVec.push_back( UnordInst );
1649 //cerr << "Reordered Inst (Moved Dn): " << *UnordInst;
1652 }// if the operand in UnordInst is a use