1 //===-- SparcRegInfo.cpp - Sparc Target Register Information --------------===//
3 // This file contains implementation of Sparc specific helper methods
4 // used for register allocation.
6 //===----------------------------------------------------------------------===//
8 #include "SparcInternals.h"
9 #include "SparcRegClassInfo.h"
10 #include "llvm/Target/Sparc.h"
11 #include "llvm/CodeGen/MachineCodeForMethod.h"
12 #include "llvm/CodeGen/PhyRegAlloc.h"
13 #include "llvm/CodeGen/InstrSelection.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/CodeGen/MachineInstrAnnot.h"
16 #include "llvm/CodeGen/RegAllocCommon.h"
17 #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h"
18 #include "llvm/iTerminators.h"
19 #include "llvm/iOther.h"
20 #include "llvm/Function.h"
21 #include "llvm/DerivedTypes.h"
27 UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
28 : MachineRegInfo(tgt), UltraSparcInfo(&tgt), NumOfIntArgRegs(6),
29 NumOfFloatArgRegs(32), InvalidRegNum(1000) {
31 MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID));
32 MachineRegClassArr.push_back(new SparcFloatRegClass(FloatRegClassID));
33 MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID));
34 MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID));
36 assert(SparcFloatRegOrder::StartOfNonVolatileRegs == 32 &&
37 "32 Float regs are used for float arg passing");
41 // getZeroRegNum - returns the register that contains always zero.
42 // this is the unified register number
44 int UltraSparcRegInfo::getZeroRegNum() const {
45 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
46 SparcIntRegOrder::g0);
49 // getCallAddressReg - returns the reg used for pushing the address when a
50 // method is called. This can be used for other purposes between calls
52 unsigned UltraSparcRegInfo::getCallAddressReg() const {
53 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
54 SparcIntRegOrder::o7);
57 // Returns the register containing the return address.
58 // It should be made sure that this register contains the return
59 // value when a return instruction is reached.
61 unsigned UltraSparcRegInfo::getReturnAddressReg() const {
62 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
63 SparcIntRegOrder::i7);
66 // given the unified register number, this gives the name
67 // for generating assembly code or debugging.
69 const std::string UltraSparcRegInfo::getUnifiedRegName(int reg) const {
71 return SparcIntRegOrder::getRegName(reg);
72 else if ( reg < (64 + 32) )
73 return SparcFloatRegOrder::getRegName( reg - 32);
74 else if( reg < (64+32+4) )
75 return SparcFloatCCRegOrder::getRegName( reg -32 - 64);
76 else if( reg < (64+32+4+2) ) // two names: %xcc and %ccr
77 return SparcIntCCRegOrder::getRegName( reg -32 - 64 - 4);
78 else if (reg== InvalidRegNum) //****** TODO: Remove */
81 assert(0 && "Invalid register number");
85 // Get unified reg number for frame pointer
86 unsigned UltraSparcRegInfo::getFramePointer() const {
87 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
88 SparcIntRegOrder::i6);
91 // Get unified reg number for stack pointer
92 unsigned UltraSparcRegInfo::getStackPointer() const {
93 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
94 SparcIntRegOrder::o6);
98 //---------------------------------------------------------------------------
99 // Finds whether a call is an indirect call
100 //---------------------------------------------------------------------------
103 isVarArgsFunction(const Type *funcType) {
104 return cast<FunctionType>(cast<PointerType>(funcType)
105 ->getElementType())->isVarArg();
109 isVarArgsCall(const MachineInstr *CallMI) {
110 Value* callee = CallMI->getOperand(0).getVRegValue();
111 // const Type* funcType = isa<Function>(callee)? callee->getType()
112 // : cast<PointerType>(callee->getType())->getElementType();
113 const Type* funcType = callee->getType();
114 return isVarArgsFunction(funcType);
118 // Get the register number for the specified integer arg#,
119 // assuming there are argNum total args, intArgNum int args,
120 // and fpArgNum FP args preceding (and not including) this one.
121 // Use INT regs for FP args if this is a varargs call.
124 // InvalidRegNum, if there is no int register available for the arg.
125 // regNum, otherwise (this is NOT the unified reg. num).
128 UltraSparcRegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall,
130 unsigned intArgNo, unsigned fpArgNo,
131 unsigned& regClassId) const
133 regClassId = IntRegClassID;
134 if (argNo >= NumOfIntArgRegs)
135 return InvalidRegNum;
137 return argNo + (inCallee? SparcIntRegOrder::i0 : SparcIntRegOrder::o0);
140 // Get the register number for the specified FP arg#,
141 // assuming there are argNum total args, intArgNum int args,
142 // and fpArgNum FP args preceding (and not including) this one.
143 // Use INT regs for FP args if this is a varargs call.
146 // InvalidRegNum, if there is no int register available for the arg.
147 // regNum, otherwise (this is NOT the unified reg. num).
150 UltraSparcRegInfo::regNumForFPArg(unsigned regType,
151 bool inCallee, bool isVarArgsCall,
153 unsigned intArgNo, unsigned fpArgNo,
154 unsigned& regClassId) const
157 return regNumForIntArg(inCallee, isVarArgsCall, argNo, intArgNo, fpArgNo,
161 regClassId = FloatRegClassID;
162 if (regType == FPSingleRegType)
163 return (argNo*2+1 >= NumOfFloatArgRegs)?
164 InvalidRegNum : SparcFloatRegOrder::f0 + (argNo * 2 + 1);
165 else if (regType == FPDoubleRegType)
166 return (argNo*2 >= NumOfFloatArgRegs)?
167 InvalidRegNum : SparcFloatRegOrder::f0 + (argNo * 2);
169 assert(0 && "Illegal FP register type");
174 //---------------------------------------------------------------------------
175 // Finds the return address of a call sparc specific call instruction
176 //---------------------------------------------------------------------------
178 // The following 4 methods are used to find the RegType (see enum above)
179 // of a LiveRange, a Value, and for a given register unified reg number.
181 int UltraSparcRegInfo::getRegType(unsigned regClassID,
182 const Type* type) const {
183 switch (regClassID) {
184 case IntRegClassID: return IntRegType;
185 case FloatRegClassID: {
186 if (type == Type::FloatTy)
187 return FPSingleRegType;
188 else if (type == Type::DoubleTy)
189 return FPDoubleRegType;
190 assert(0 && "Unknown type in FloatRegClass");
192 case IntCCRegClassID: return IntCCRegType;
193 case FloatCCRegClassID: return FloatCCRegType;
194 default: assert( 0 && "Unknown reg class ID"); return 0;
198 int UltraSparcRegInfo::getRegType(const LiveRange *LR) const {
199 return getRegType(LR->getRegClass()->getID(), LR->getType());
202 int UltraSparcRegInfo::getRegType(const Value *Val) const {
203 return getRegType(getRegClassIDOfValue(Val), Val->getType());
206 int UltraSparcRegInfo::getRegType(int reg) const {
209 else if (reg < (32 + 32))
210 return FPSingleRegType;
211 else if (reg < (64 + 32))
212 return FPDoubleRegType;
213 else if (reg < (64+32+4))
214 return FloatCCRegType;
215 else if (reg < (64+32+4+2))
218 assert(0 && "Invalid register number in getRegType");
223 //---------------------------------------------------------------------------
224 // Suggests a register for the ret address in the RET machine instruction.
225 // We always suggest %i7 by convention.
226 //---------------------------------------------------------------------------
227 void UltraSparcRegInfo::suggestReg4RetAddr(const MachineInstr *RetMI,
228 LiveRangeInfo& LRI) const {
230 assert( (RetMI->getNumOperands() >= 2)
231 && "JMPL/RETURN must have 3 and 2 operands respectively");
233 MachineOperand & MO = ( MachineOperand &) RetMI->getOperand(0);
235 // return address is always mapped to i7
237 MO.setRegForValue( getUnifiedRegNum( IntRegClassID, SparcIntRegOrder::i7) );
239 // Possible Optimization:
240 // Instead of setting the color, we can suggest one. In that case,
241 // we have to test later whether it received the suggested color.
242 // In that case, a LR has to be created at the start of method.
243 // It has to be done as follows (remove the setRegVal above):
245 // const Value *RetAddrVal = MO.getVRegValue();
246 // assert( RetAddrVal && "LR for ret address must be created at start");
247 // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
248 // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
249 // SparcIntRegOrdr::i7) );
253 //---------------------------------------------------------------------------
254 // Suggests a register for the ret address in the JMPL/CALL machine instr.
255 // Sparc ABI dictates that %o7 be used for this purpose.
256 //---------------------------------------------------------------------------
257 void UltraSparcRegInfo::suggestReg4CallAddr(const MachineInstr * CallMI,
259 std::vector<RegClass *> RCList) const {
260 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
261 const Value *RetAddrVal = argDesc->getReturnAddrReg();
262 assert(RetAddrVal && "Return address value is required");
264 // create a new LR for the return address and color it
265 LiveRange * RetAddrLR = new LiveRange();
266 RetAddrLR->insert( RetAddrVal );
267 unsigned RegClassID = getRegClassIDOfValue( RetAddrVal );
268 RetAddrLR->setRegClass( RCList[RegClassID] );
269 RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o7));
270 LRI.addLRToMap( RetAddrVal, RetAddrLR);
277 //---------------------------------------------------------------------------
278 // This method will suggest colors to incoming args to a method.
279 // According to the Sparc ABI, the first 6 incoming args are in
280 // %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float).
281 // If the arg is passed on stack due to the lack of regs, NOTHING will be
282 // done - it will be colored (or spilled) as a normal live range.
283 //---------------------------------------------------------------------------
284 void UltraSparcRegInfo::suggestRegs4MethodArgs(const Function *Meth,
285 LiveRangeInfo& LRI) const
287 // check if this is a varArgs function. needed for choosing regs.
288 bool isVarArgs = isVarArgsFunction(Meth->getType());
290 // for each argument. count INT and FP arguments separately.
291 unsigned argNo=0, intArgNo=0, fpArgNo=0;
292 for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend();
293 I != E; ++I, ++argNo) {
295 LiveRange *LR = LRI.getLiveRangeForValue(I);
296 assert(LR && "No live range found for method arg");
298 unsigned regType = getRegType(LR);
299 unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg (unused)
301 int regNum = (regType == IntRegType)
302 ? regNumForIntArg(/*inCallee*/ true, isVarArgs,
303 argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
304 : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs,
305 argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
307 if(regNum != InvalidRegNum)
308 LR->setSuggestedColor(regNum);
313 //---------------------------------------------------------------------------
314 // This method is called after graph coloring to move incoming args to
315 // the correct hardware registers if they did not receive the correct
316 // (suggested) color through graph coloring.
317 //---------------------------------------------------------------------------
318 void UltraSparcRegInfo::colorMethodArgs(const Function *Meth,
320 AddedInstrns *FirstAI) const {
322 // check if this is a varArgs function. needed for choosing regs.
323 bool isVarArgs = isVarArgsFunction(Meth->getType());
327 // for each argument. count INT and FP arguments separately.
328 unsigned argNo=0, intArgNo=0, fpArgNo=0;
329 for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend();
330 I != E; ++I, ++argNo) {
332 LiveRange *LR = LRI.getLiveRangeForValue(I);
333 assert( LR && "No live range found for method arg");
335 unsigned regType = getRegType( LR );
336 unsigned RegClassID = (LR->getRegClass())->getID();
338 // Find whether this argument is coming in a register (if not, on stack)
339 // Also find the correct register the argument must use (UniArgReg)
341 bool isArgInReg = false;
342 unsigned UniArgReg = InvalidRegNum; // reg that LR MUST be colored with
343 unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg
345 int regNum = (regType == IntRegType)
346 ? regNumForIntArg(/*inCallee*/ true, isVarArgs,
347 argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
348 : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs,
349 argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
351 if(regNum != InvalidRegNum) {
353 UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum);
356 if( LR->hasColor() ) { // if this arg received a register
358 unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
360 // if LR received the correct color, nothing to do
362 if( UniLRReg == UniArgReg )
365 // We are here because the LR did not receive the suggested
366 // but LR received another register.
367 // Now we have to copy the %i reg (or stack pos of arg)
368 // to the register the LR was colored with.
370 // if the arg is coming in UniArgReg register, it MUST go into
371 // the UniLRReg register
374 if( regClassIDOfArgReg != RegClassID ) {
375 assert(0 && "This could should work but it is not tested yet");
377 // It is a variable argument call: the float reg must go in a %o reg.
378 // We have to move an int reg to a float reg via memory.
381 RegClassID == FloatRegClassID &&
382 regClassIDOfArgReg == IntRegClassID &&
383 "This should only be an Int register for an FP argument");
385 int TmpOff = MachineCodeForMethod::get(Meth).pushTempValue(target,
386 getSpilledRegSize(regType));
387 cpReg2MemMI(UniArgReg, getFramePointer(), TmpOff, IntRegType,
388 FirstAI->InstrnsBefore);
390 cpMem2RegMI(getFramePointer(), TmpOff, UniLRReg, regType,
391 FirstAI->InstrnsBefore);
394 cpReg2RegMI(UniArgReg, UniLRReg, regType, FirstAI->InstrnsBefore);
399 // Now the arg is coming on stack. Since the LR recieved a register,
400 // we just have to load the arg on stack into that register
402 const MachineFrameInfo& frameInfo = target.getFrameInfo();
404 frameInfo.getIncomingArgOffset(MachineCodeForMethod::get(Meth),
407 cpMem2RegMI(getFramePointer(), offsetFromFP, UniLRReg, regType,
408 FirstAI->InstrnsBefore);
411 } // if LR received a color
415 // Now, the LR did not receive a color. But it has a stack offset for
417 // So, if the arg is coming in UniArgReg register, we can just move
418 // that on to the stack pos of LR
422 if( regClassIDOfArgReg != RegClassID ) {
424 "FP arguments to a varargs function should be explicitly "
425 "copied to/from int registers by instruction selection!");
427 // It must be a float arg for a variable argument call, which
428 // must come in a %o reg. Move the int reg to the stack.
430 assert(isVarArgs && regClassIDOfArgReg == IntRegClassID &&
431 "This should only be an Int register for an FP argument");
433 cpReg2MemMI(UniArgReg, getFramePointer(), LR->getSpillOffFromFP(),
434 IntRegType, FirstAI->InstrnsBefore);
437 cpReg2MemMI(UniArgReg, getFramePointer(), LR->getSpillOffFromFP(),
438 regType, FirstAI->InstrnsBefore);
444 // Now the arg is coming on stack. Since the LR did NOT
445 // recieved a register as well, it is allocated a stack position. We
446 // can simply change the stack position of the LR. We can do this,
447 // since this method is called before any other method that makes
448 // uses of the stack pos of the LR (e.g., updateMachineInstr)
450 const MachineFrameInfo& frameInfo = target.getFrameInfo();
452 frameInfo.getIncomingArgOffset(MachineCodeForMethod::get(Meth),
455 LR->modifySpillOffFromFP( offsetFromFP );
460 } // for each incoming argument
466 //---------------------------------------------------------------------------
467 // This method is called before graph coloring to suggest colors to the
468 // outgoing call args and the return value of the call.
469 //---------------------------------------------------------------------------
470 void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *CallMI,
472 std::vector<RegClass *> RCList) const {
473 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
475 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
477 suggestReg4CallAddr(CallMI, LRI, RCList);
479 // First color the return value of the call instruction. The return value
480 // will be in %o0 if the value is an integer type, or in %f0 if the
481 // value is a float type.
483 // the return value cannot have a LR in machine instruction since it is
484 // only defined by the call instruction
486 // if type is not void, create a new live range and set its
487 // register class and add to LRI
489 const Value *RetVal = argDesc->getReturnValue();
492 assert ((!LRI.getLiveRangeForValue(RetVal)) &&
493 "LR for ret Value of call already definded!");
495 // create a new LR for the return value
496 LiveRange *RetValLR = new LiveRange();
497 RetValLR->insert(RetVal);
498 unsigned RegClassID = getRegClassIDOfValue(RetVal);
499 RetValLR->setRegClass(RCList[RegClassID]);
500 LRI.addLRToMap(RetVal, RetValLR);
502 // now suggest a register depending on the register class of ret arg
504 if( RegClassID == IntRegClassID )
505 RetValLR->setSuggestedColor(SparcIntRegOrder::o0);
506 else if (RegClassID == FloatRegClassID )
507 RetValLR->setSuggestedColor(SparcFloatRegOrder::f0 );
508 else assert( 0 && "Unknown reg class for return value of call\n");
512 // Now suggest colors for arguments (operands) of the call instruction.
513 // Colors are suggested only if the arg number is smaller than the
514 // the number of registers allocated for argument passing.
515 // Now, go thru call args - implicit operands of the call MI
517 unsigned NumOfCallArgs = argDesc->getNumArgs();
519 for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0;
520 i < NumOfCallArgs; ++i, ++argNo) {
522 const Value *CallArg = argDesc->getArgInfo(i).getArgVal();
524 // get the LR of call operand (parameter)
525 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
527 // not possible to have a null LR since all args (even consts)
528 // must be defined before
530 cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) << "\n";
531 assert(0 && "NO LR for call arg");
534 unsigned regType = getRegType( LR );
535 unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg (unused)
537 // Choose a register for this arg depending on whether it is
538 // an INT or FP value. Here we ignore whether or not it is a
539 // varargs calls, because FP arguments will be explicitly copied
540 // to an integer Value and handled under (argCopy != NULL) below.
541 int regNum = (regType == IntRegType)
542 ? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false,
543 argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
544 : regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false,
545 argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
547 // If a register could be allocated, use it.
548 // If not, do NOTHING as this will be colored as a normal value.
549 if(regNum != InvalidRegNum)
550 LR->setSuggestedColor(regNum);
552 // Repeat for the second copy of the argument, which would be
553 // an FP argument being passed to a function with no prototype
554 const Value *argCopy = argDesc->getArgInfo(i).getArgCopy();
557 assert(regType != IntRegType && argCopy->getType()->isIntegral()
558 && "Must be passing copy of FP argument in int register");
559 int copyRegNum = regNumForIntArg(/*inCallee*/false, /*isVarArgs*/false,
560 argNo, intArgNo, fpArgNo-1,
562 assert(copyRegNum != InvalidRegNum);
563 LiveRange *const copyLR = LRI.getLiveRangeForValue(argCopy);
564 copyLR->setSuggestedColor(copyRegNum);
567 } // for all call arguments
572 //---------------------------------------------------------------------------
573 // Helper method for UltraSparcRegInfo::colorCallArgs().
574 //---------------------------------------------------------------------------
577 UltraSparcRegInfo::InitializeOutgoingArg(const MachineInstr* CallMI,
578 AddedInstrns *CallAI,
579 PhyRegAlloc &PRA, LiveRange* LR,
580 unsigned regType, unsigned RegClassID,
581 int UniArgRegOrNone, unsigned int argNo,
582 std::vector<MachineInstr *>& AddedInstrnsBefore)
586 bool isArgInReg = false;
587 unsigned UniArgReg = MAXINT; // unused unless initialized below
588 if (UniArgRegOrNone != InvalidRegNum)
591 UniArgReg = (unsigned) UniArgRegOrNone;
594 if (LR->hasColor()) {
595 unsigned UniLRReg = getUnifiedRegNum(RegClassID, LR->getColor());
597 // if LR received the correct color, nothing to do
598 if( isArgInReg && UniArgReg == UniLRReg )
601 // The LR is allocated to a register UniLRReg and must be copied
602 // to UniArgReg or to the stack slot.
605 // Copy UniLRReg to UniArgReg
606 cpReg2RegMI(UniLRReg, UniArgReg, regType, AddedInstrnsBefore);
609 // Copy UniLRReg to the stack to pass the arg on stack.
610 const MachineFrameInfo& frameInfo = target.getFrameInfo();
611 int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo);
612 cpReg2MemMI(UniLRReg, getStackPointer(), argOffset, regType,
613 CallAI->InstrnsBefore);
616 } else { // LR is not colored (i.e., spilled)
619 // Insert a load instruction to load the LR to UniArgReg
620 cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
621 UniArgReg, regType, AddedInstrnsBefore);
622 // Now add the instruction
626 // Now, we have to pass the arg on stack. Since LR also did NOT
627 // receive a register we have to move an argument in memory to
628 // outgoing parameter on stack.
629 // Use TReg to load and store the value.
630 // Use TmpOff to save TReg, since that may have a live value.
632 int TReg = PRA.getUniRegNotUsedByThisInst( LR->getRegClass(), CallMI );
633 int TmpOff = PRA.mcInfo.pushTempValue(target,
634 getSpilledRegSize(getRegType(LR)));
635 const MachineFrameInfo& frameInfo = target.getFrameInfo();
636 int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo);
638 MachineInstr *Ad1, *Ad2, *Ad3, *Ad4;
641 // (1) Save TReg on stack
642 // (2) Load LR value into TReg from stack pos of LR
643 // (3) Store Treg on outgoing Arg pos on stack
644 // (4) Load the old value of TReg from stack to TReg (restore it)
647 // When reverse pointers in MahineInstr are introduced:
648 // Call PRA.getUnusedRegAtMI(....) to get an unused reg. Step 1 is
649 // needed only if this fails. Currently, we cannot call the
650 // above method since we cannot find LVSetBefore without the BB
652 // NOTE: We directly add to CallAI->InstrnsBefore instead of adding to
653 // AddedInstrnsBefore since these instructions must not be reordered.
654 cpReg2MemMI(TReg, getFramePointer(), TmpOff, regType,
655 CallAI->InstrnsBefore);
656 cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(), TReg, regType,
657 CallAI->InstrnsBefore);
658 cpReg2MemMI(TReg, getStackPointer(), argOffset, regType,
659 CallAI->InstrnsBefore);
660 cpMem2RegMI(getFramePointer(), TmpOff, TReg, regType,
661 CallAI->InstrnsBefore);
666 //---------------------------------------------------------------------------
667 // After graph coloring, we have call this method to see whehter the return
668 // value and the call args received the correct colors. If not, we have
669 // to instert copy instructions.
670 //---------------------------------------------------------------------------
672 void UltraSparcRegInfo::colorCallArgs(const MachineInstr *CallMI,
674 AddedInstrns *CallAI,
676 const BasicBlock *BB) const {
678 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
680 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
682 // First color the return value of the call.
683 // If there is a LR for the return value, it means this
684 // method returns a value
688 const Value *RetVal = argDesc->getReturnValue();
691 LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal );
694 cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
695 assert(RetValLR && "ERR:No LR for non-void return value");
698 unsigned RegClassID = (RetValLR->getRegClass())->getID();
699 bool recvCorrectColor = false;
701 unsigned CorrectCol; // correct color for ret value
702 if(RegClassID == IntRegClassID)
703 CorrectCol = SparcIntRegOrder::o0;
704 else if(RegClassID == FloatRegClassID)
705 CorrectCol = SparcFloatRegOrder::f0;
707 assert( 0 && "Unknown RegClass");
711 // if the LR received the correct color, NOTHING to do
713 if( RetValLR->hasColor() )
714 if( RetValLR->getColor() == CorrectCol )
715 recvCorrectColor = true;
718 // if we didn't receive the correct color for some reason,
719 // put copy instruction
721 if( !recvCorrectColor ) {
723 unsigned regType = getRegType( RetValLR );
725 // the reg that LR must be colored with
726 unsigned UniRetReg = getUnifiedRegNum( RegClassID, CorrectCol);
728 if( RetValLR->hasColor() ) {
731 UniRetLRReg=getUnifiedRegNum(RegClassID,RetValLR->getColor());
733 // the return value is coming in UniRetReg but has to go into
736 cpReg2RegMI(UniRetReg, UniRetLRReg, regType, CallAI->InstrnsAfter);
741 // if the LR did NOT receive a color, we have to move the return
742 // value coming in UniRetReg to the stack pos of spilled LR
744 cpReg2MemMI(UniRetReg, getFramePointer(),RetValLR->getSpillOffFromFP(),
745 regType, CallAI->InstrnsAfter);
748 } // the LR didn't receive the suggested color
750 } // if there a return value
753 //-------------------------------------------
754 // Now color all args of the call instruction
755 //-------------------------------------------
757 std::vector<MachineInstr *> AddedInstrnsBefore;
759 unsigned NumOfCallArgs = argDesc->getNumArgs();
761 for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0;
762 i < NumOfCallArgs; ++i, ++argNo) {
764 const Value *CallArg = argDesc->getArgInfo(i).getArgVal();
766 // get the LR of call operand (parameter)
767 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
769 unsigned RegClassID = getRegClassIDOfValue( CallArg);
770 unsigned regType = getRegType( RegClassID, CallArg->getType() );
772 // Find whether this argument is coming in a register (if not, on stack)
773 // Also find the correct register the argument must use (UniArgReg)
775 bool isArgInReg = false;
776 unsigned UniArgReg = InvalidRegNum; // reg that LR MUST be colored with
777 unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg
779 // Find the register that must be used for this arg, depending on
780 // whether it is an INT or FP value. Here we ignore whether or not it
781 // is a varargs calls, because FP arguments will be explicitly copied
782 // to an integer Value and handled under (argCopy != NULL) below.
783 int regNum = (regType == IntRegType)
784 ? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false,
785 argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
786 : regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false,
787 argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
789 if(regNum != InvalidRegNum) {
791 UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum);
792 assert(regClassIDOfArgReg == RegClassID &&
793 "Moving values between reg classes must happen during selection");
796 // not possible to have a null LR since all args (even consts)
797 // must be defined before
799 cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) <<"\n";
800 assert(LR && "NO LR for call arg");
803 InitializeOutgoingArg(CallMI, CallAI, PRA, LR, regType, RegClassID,
804 UniArgReg, argNo, AddedInstrnsBefore);
806 // Repeat for the second copy of the argument, which would be
807 // an FP argument being passed to a function with no prototype.
808 const Value *argCopy = argDesc->getArgInfo(i).getArgCopy();
811 assert(regType != IntRegType && argCopy->getType()->isIntegral()
812 && "Must be passing copy of FP argument in int register");
814 unsigned copyRegClassID = getRegClassIDOfValue(argCopy);
815 unsigned copyRegType = getRegType(copyRegClassID, argCopy->getType());
817 int copyRegNum = regNumForIntArg(/*inCallee*/false, /*isVarArgs*/false,
818 argNo, intArgNo, fpArgNo-1,
820 assert(copyRegNum != InvalidRegNum);
821 assert(regClassIDOfArgReg == copyRegClassID &&
822 "Moving values between reg classes must happen during selection");
824 InitializeOutgoingArg(CallMI, CallAI, PRA,
825 LRI.getLiveRangeForValue(argCopy), copyRegType,
826 copyRegClassID, copyRegNum, argNo,
829 } // for each parameter in call instruction
831 // If we added any instruction before the call instruction, verify
832 // that they are in the proper order and if not, reorder them
834 if (!AddedInstrnsBefore.empty()) {
837 cerr << "\nCalling reorder with instrns: \n";
838 for(unsigned i=0; i < AddedInstrnsBefore.size(); i++)
839 cerr << *(AddedInstrnsBefore[i]);
842 std::vector<MachineInstr *> TmpVec;
843 OrderAddedInstrns(AddedInstrnsBefore, TmpVec, PRA);
846 cerr << "\nAfter reordering instrns: \n";
847 for(unsigned i = 0; i < TmpVec.size(); i++)
851 // copy the results back from TmpVec to InstrnsBefore
852 for(unsigned i=0; i < TmpVec.size(); i++)
853 CallAI->InstrnsBefore.push_back( TmpVec[i] );
856 // now insert caller saving code for this call instruction
858 insertCallerSavingCode(CallMI, BB, PRA);
861 //---------------------------------------------------------------------------
862 // This method is called for an LLVM return instruction to identify which
863 // values will be returned from this method and to suggest colors.
864 //---------------------------------------------------------------------------
865 void UltraSparcRegInfo::suggestReg4RetValue(const MachineInstr *RetMI,
866 LiveRangeInfo &LRI) const {
868 assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) );
870 suggestReg4RetAddr(RetMI, LRI);
872 // if there is an implicit ref, that has to be the ret value
873 if( RetMI->getNumImplicitRefs() > 0 ) {
875 // The first implicit operand is the return value of a return instr
876 const Value *RetVal = RetMI->getImplicitRef(0);
878 LiveRange *const LR = LRI.getLiveRangeForValue( RetVal );
881 cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
882 assert(0 && "No LR for return value of non-void method");
885 unsigned RegClassID = (LR->getRegClass())->getID();
887 if (RegClassID == IntRegClassID)
888 LR->setSuggestedColor(SparcIntRegOrder::i0);
889 else if (RegClassID == FloatRegClassID)
890 LR->setSuggestedColor(SparcFloatRegOrder::f0);
896 //---------------------------------------------------------------------------
897 // Colors the return value of a method to %i0 or %f0, if possible. If it is
898 // not possilbe to directly color the LR, insert a copy instruction to move
899 // the LR to %i0 or %f0. When the LR is spilled, instead of the copy, we
900 // have to put a load instruction.
901 //---------------------------------------------------------------------------
902 void UltraSparcRegInfo::colorRetValue(const MachineInstr *RetMI,
904 AddedInstrns *RetAI) const {
906 assert((UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode()));
908 // if there is an implicit ref, that has to be the ret value
909 if(RetMI->getNumImplicitRefs() > 0) {
911 // The first implicit operand is the return value of a return instr
912 const Value *RetVal = RetMI->getImplicitRef(0);
914 LiveRange *LR = LRI.getLiveRangeForValue(RetVal);
917 cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
918 // assert( LR && "No LR for return value of non-void method");
922 unsigned RegClassID = getRegClassIDOfValue(RetVal);
923 unsigned regType = getRegType( RetVal );
926 if(RegClassID == IntRegClassID)
927 CorrectCol = SparcIntRegOrder::i0;
928 else if(RegClassID == FloatRegClassID)
929 CorrectCol = SparcFloatRegOrder::f0;
931 assert (0 && "Unknown RegClass");
935 // if the LR received the correct color, NOTHING to do
937 if (LR->hasColor() && LR->getColor() == CorrectCol)
940 unsigned UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
942 if (LR->hasColor()) {
944 // We are here because the LR was allocted a regiter
945 // It may be the suggested register or not
947 // copy the LR of retun value to i0 or f0
949 unsigned UniLRReg =getUnifiedRegNum( RegClassID, LR->getColor());
951 // the LR received UniLRReg but must be colored with UniRetReg
952 // to pass as the return value
953 cpReg2RegMI(UniLRReg, UniRetReg, regType, RetAI->InstrnsBefore);
955 else { // if the LR is spilled
956 cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
957 UniRetReg, regType, RetAI->InstrnsBefore);
958 cerr << "\nCopied the return value from stack\n";
961 } // if there is a return value
966 //---------------------------------------------------------------------------
967 // Copy from a register to register. Register number must be the unified
969 //---------------------------------------------------------------------------
972 UltraSparcRegInfo::cpReg2RegMI(unsigned SrcReg,
975 vector<MachineInstr*>& mvec) const {
976 assert( ((int)SrcReg != InvalidRegNum) && ((int)DestReg != InvalidRegNum) &&
979 MachineInstr * MI = NULL;
985 assert(0 && "This code was bogus and needs to be fixed!");
989 MI = new MachineInstr(ADD, 3);
990 MI->SetMachineOperandReg(0, SrcReg, false);
991 MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
992 MI->SetMachineOperandReg(2, DestReg, true);
995 case FPSingleRegType:
996 MI = new MachineInstr(FMOVS, 2);
997 MI->SetMachineOperandReg(0, SrcReg, false);
998 MI->SetMachineOperandReg(1, DestReg, true);
1001 case FPDoubleRegType:
1002 MI = new MachineInstr(FMOVD, 2);
1003 MI->SetMachineOperandReg(0, SrcReg, false);
1004 MI->SetMachineOperandReg(1, DestReg, true);
1008 assert(0 && "Unknown RegType");
1015 //---------------------------------------------------------------------------
1016 // Copy from a register to memory (i.e., Store). Register number must
1017 // be the unified register number
1018 //---------------------------------------------------------------------------
1022 UltraSparcRegInfo::cpReg2MemMI(unsigned SrcReg,
1023 unsigned DestPtrReg,
1024 int Offset, int RegType,
1025 vector<MachineInstr*>& mvec) const {
1026 MachineInstr * MI = NULL;
1029 case FloatCCRegType:
1030 MI = new MachineInstr(STX, 3);
1031 MI->SetMachineOperandReg(0, SrcReg, false);
1032 MI->SetMachineOperandReg(1, DestPtrReg, false);
1033 MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
1037 case FPSingleRegType:
1038 MI = new MachineInstr(ST, 3);
1039 MI->SetMachineOperandReg(0, SrcReg, false);
1040 MI->SetMachineOperandReg(1, DestPtrReg, false);
1041 MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
1045 case FPDoubleRegType:
1046 MI = new MachineInstr(STD, 3);
1047 MI->SetMachineOperandReg(0, SrcReg, false);
1048 MI->SetMachineOperandReg(1, DestPtrReg, false);
1049 MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
1054 assert( 0 && "Cannot directly store %ccr to memory");
1057 assert(0 && "Unknown RegType in cpReg2MemMI");
1065 //---------------------------------------------------------------------------
1066 // Copy from memory to a reg (i.e., Load) Register number must be the unified
1068 //---------------------------------------------------------------------------
1072 UltraSparcRegInfo::cpMem2RegMI(unsigned SrcPtrReg,
1076 vector<MachineInstr*>& mvec) const {
1077 MachineInstr * MI = NULL;
1080 case FloatCCRegType:
1081 MI = new MachineInstr(LDX, 3);
1082 MI->SetMachineOperandReg(0, SrcPtrReg, false);
1083 MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
1085 MI->SetMachineOperandReg(2, DestReg, true);
1088 case FPSingleRegType:
1089 MI = new MachineInstr(LD, 3);
1090 MI->SetMachineOperandReg(0, SrcPtrReg, false);
1091 MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
1093 MI->SetMachineOperandReg(2, DestReg, true);
1097 case FPDoubleRegType:
1098 MI = new MachineInstr(LDD, 3);
1099 MI->SetMachineOperandReg(0, SrcPtrReg, false);
1100 MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
1102 MI->SetMachineOperandReg(2, DestReg, true);
1106 assert( 0 && "Cannot directly load into %ccr from memory");
1109 assert(0 && "Unknown RegType in cpMem2RegMI");
1117 //---------------------------------------------------------------------------
1118 // Generate a copy instruction to copy a value to another. Temporarily
1119 // used by PhiElimination code.
1120 //---------------------------------------------------------------------------
1124 UltraSparcRegInfo::cpValue2Value(Value *Src,
1126 vector<MachineInstr*>& mvec) const {
1127 int RegType = getRegType( Src );
1129 assert( (RegType==getRegType(Src)) && "Src & Dest are diff types");
1131 MachineInstr * MI = NULL;
1135 MI = new MachineInstr(ADD, 3);
1136 MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
1137 MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
1138 MI->SetMachineOperandVal(2, MachineOperand:: MO_VirtualRegister, Dest, true);
1141 case FPSingleRegType:
1142 MI = new MachineInstr(FMOVS, 2);
1143 MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
1144 MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true);
1148 case FPDoubleRegType:
1149 MI = new MachineInstr(FMOVD, 2);
1150 MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
1151 MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true);
1155 assert(0 && "Unknow RegType in CpValu2Value");
1167 //----------------------------------------------------------------------------
1168 // This method inserts caller saving/restoring instructons before/after
1169 // a call machine instruction. The caller saving/restoring instructions are
1172 // ** caller saving instructions
1173 // other instructions inserted for the call by ColorCallArg
1175 // other instructions inserted for the call ColorCallArg
1176 // ** caller restoring instructions
1178 //----------------------------------------------------------------------------
1181 void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *CallMI,
1182 const BasicBlock *BB,
1183 PhyRegAlloc &PRA) const {
1185 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
1187 // has set to record which registers were saved/restored
1189 std::hash_set<unsigned> PushedRegSet;
1191 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
1193 // Now find the LR of the return value of the call
1194 // The last *implicit operand* is the return value of a call
1195 // Insert it to to he PushedRegSet since we must not save that register
1196 // and restore it after the call.
1197 // We do this because, we look at the LV set *after* the instruction
1198 // to determine, which LRs must be saved across calls. The return value
1199 // of the call is live in this set - but we must not save/restore it.
1201 const Value *RetVal = argDesc->getReturnValue();
1204 LiveRange *RetValLR = PRA.LRI.getLiveRangeForValue( RetVal );
1205 assert(RetValLR && "No LR for RetValue of call");
1207 if (RetValLR->hasColor())
1208 PushedRegSet.insert(
1209 getUnifiedRegNum((RetValLR->getRegClass())->getID(),
1210 RetValLR->getColor() ) );
1214 const ValueSet &LVSetAft = PRA.LVI->getLiveVarSetAfterMInst(CallMI, BB);
1215 ValueSet::const_iterator LIt = LVSetAft.begin();
1217 // for each live var in live variable set after machine inst
1218 for( ; LIt != LVSetAft.end(); ++LIt) {
1220 // get the live range corresponding to live var
1221 LiveRange *const LR = PRA.LRI.getLiveRangeForValue(*LIt );
1223 // LR can be null if it is a const since a const
1224 // doesn't have a dominating def - see Assumptions above
1227 if( LR->hasColor() ) {
1229 unsigned RCID = (LR->getRegClass())->getID();
1230 unsigned Color = LR->getColor();
1232 if ( isRegVolatile(RCID, Color) ) {
1234 // if the value is in both LV sets (i.e., live before and after
1235 // the call machine instruction)
1237 unsigned Reg = getUnifiedRegNum(RCID, Color);
1239 if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
1241 // if we haven't already pushed that register
1243 unsigned RegType = getRegType( LR );
1245 // Now get two instructions - to push on stack and pop from stack
1246 // and add them to InstrnsBefore and InstrnsAfter of the
1250 int StackOff = PRA.mcInfo.pushTempValue(target,
1251 getSpilledRegSize(RegType));
1254 MachineInstr *AdIBefCC=NULL, *AdIAftCC=NULL, *AdICpCC;
1255 MachineInstr *AdIBef=NULL, *AdIAft=NULL;
1257 //---- Insert code for pushing the reg on stack ----------
1259 if( RegType == IntCCRegType ) {
1261 // Handle IntCCRegType specially since we cannot directly
1262 // push %ccr on to the stack
1264 const ValueSet &LVSetBef =
1265 PRA.LVI->getLiveVarSetBeforeMInst(CallMI, BB);
1267 // get a free INTEGER register
1269 PRA.getUsableUniRegAtMI(PRA.getRegClassByID(IntRegClassID) /*LR->getRegClass()*/,
1270 IntRegType, CallMI, &LVSetBef, AdIBefCC, AdIAftCC);
1272 // insert the instructions in reverse order since we are
1273 // adding them to the front of InstrnsBefore
1274 AddedInstrns& addedI = PRA.AddedInstrMap[CallMI];
1276 addedI.InstrnsBefore.insert(addedI.InstrnsBefore.begin(),
1279 AdICpCC = cpCCR2IntMI(FreeIntReg);
1280 addedI.InstrnsBefore.insert(addedI.InstrnsBefore.begin(),
1284 addedI.InstrnsBefore.insert(addedI.InstrnsBefore.begin(),
1288 cerr << "\n!! Inserted caller saving (push) inst for %ccr:";
1289 if(AdIBefCC) cerr << "\t" << *(AdIBefCC);
1290 cerr << "\t" << *AdICpCC;
1291 if(AdIAftCC) cerr << "\t" << *(AdIAftCC);
1295 // for any other register type, just add the push inst
1296 cpReg2MemMI(Reg, getFramePointer(), StackOff, RegType,
1297 PRA.AddedInstrMap[CallMI].InstrnsBefore);
1301 //---- Insert code for popping the reg from the stack ----------
1303 if (RegType == IntCCRegType) {
1305 // Handle IntCCRegType specially since we cannot directly
1306 // pop %ccr on from the stack
1308 // get a free INT register
1310 PRA.getUsableUniRegAtMI(PRA.getRegClassByID(IntRegClassID) /* LR->getRegClass()*/,
1311 IntRegType, CallMI, &LVSetAft, AdIBefCC, AdIAftCC);
1314 PRA.AddedInstrMap[CallMI].InstrnsAfter.push_back(AdIBefCC);
1316 AdICpCC = cpInt2CCRMI(FreeIntReg);
1317 PRA.AddedInstrMap[CallMI].InstrnsAfter.push_back(AdICpCC);
1320 PRA.AddedInstrMap[CallMI].InstrnsAfter.push_back(AdIAftCC);
1324 cerr << "\n!! Inserted caller saving (pop) inst for %ccr:";
1325 if(AdIBefCC) cerr << "\t" << *(AdIBefCC);
1326 cerr << "\t" << *AdICpCC;
1327 if(AdIAftCC) cerr << "\t" << *(AdIAftCC);
1331 // for any other register type, just add the pop inst
1332 cpMem2RegMI(getFramePointer(), StackOff, Reg, RegType,
1333 PRA.AddedInstrMap[CallMI].InstrnsAfter);
1336 PushedRegSet.insert(Reg);
1339 cerr << "\nFor call inst:" << *CallMI;
1340 cerr << " -inserted caller saving instrs:\n\t ";
1341 if( RegType == IntCCRegType ) {
1342 if(AdIBefCC) cerr << *AdIBefCC << "\t";
1343 if(AdIAftCC) cerr << *AdIAftCC;
1346 if(AdIBef) cerr << *AdIBef << "\t";
1347 if(AdIAft) cerr << *AdIAft;
1350 } // if not already pushed
1352 } // if LR has a volatile color
1354 } // if LR has color
1356 } // if there is a LR for Var
1358 } // for each value in the LV set after instruction
1362 //---------------------------------------------------------------------------
1363 // Copies %ccr into an integer register. IntReg is the UNIFIED register
1365 //---------------------------------------------------------------------------
1367 MachineInstr * UltraSparcRegInfo::cpCCR2IntMI(unsigned IntReg) const {
1368 MachineInstr * MI = new MachineInstr(RDCCR, 2);
1369 MI->SetMachineOperandReg(0, this->getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID,
1370 SparcIntCCRegOrder::ccr),
1372 MI->SetMachineOperandReg(1, IntReg, true);
1376 //---------------------------------------------------------------------------
1377 // Copies an integer register into %ccr. IntReg is the UNIFIED register
1379 //---------------------------------------------------------------------------
1381 MachineInstr *UltraSparcRegInfo::cpInt2CCRMI(unsigned IntReg) const {
1382 MachineInstr *MI = new MachineInstr(WRCCR, 3);
1383 MI->SetMachineOperandReg(0, IntReg, false);
1384 MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
1385 MI->SetMachineOperandReg(2, this->getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID, SparcIntCCRegOrder::ccr),
1393 //---------------------------------------------------------------------------
1394 // Print the register assigned to a LR
1395 //---------------------------------------------------------------------------
1397 void UltraSparcRegInfo::printReg(const LiveRange *LR) {
1398 unsigned RegClassID = (LR->getRegClass())->getID();
1399 cerr << " *Node " << (LR->getUserIGNode())->getIndex();
1401 if (!LR->hasColor()) {
1402 cerr << " - could not find a color\n";
1406 // if a color is found
1408 cerr << " colored with color "<< LR->getColor();
1410 if (RegClassID == IntRegClassID) {
1411 cerr<< " [" << SparcIntRegOrder::getRegName(LR->getColor()) << "]\n";
1413 } else if (RegClassID == FloatRegClassID) {
1414 cerr << "[" << SparcFloatRegOrder::getRegName(LR->getColor());
1415 if( LR->getType() == Type::DoubleTy)
1416 cerr << "+" << SparcFloatRegOrder::getRegName(LR->getColor()+1);
1421 //---------------------------------------------------------------------------
1422 // This method examines instructions inserted by RegAlloc code before a
1423 // machine instruction to detect invalid orders that destroy values before
1424 // they are used. If it detects such conditions, it reorders the instructions.
1426 // The unordered instructions come in the UnordVec. These instructions are
1427 // instructions inserted by RegAlloc. All such instruction MUST have
1428 // their USES BEFORE THE DEFS after reordering.
1430 // The UnordVec & OrdVec must be DISTINCT. The OrdVec must be empty when
1431 // this method is called.
1433 // This method uses two vectors for efficiency in accessing
1435 // Since instructions are inserted in RegAlloc, this assumes that the
1436 // first operand is the source reg and the last operand is the dest reg.
1438 // All the uses are before THE def to a register
1439 //---------------------------------------------------------------------------
1441 void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr*> &UnordVec,
1442 std::vector<MachineInstr*> &OrdVec,
1443 PhyRegAlloc &PRA) const{
1446 Problem: We can have instructions inserted by RegAlloc like
1448 2. add %oy %g0 %oz, where z!=x or z==x
1450 This is wrong since %oy used by 2 is overwritten by 1
1453 We re-order the instructions so that the uses are before the defs
1458 for each instruction 'DefInst' in the UnOrdVec
1459 for each instruction 'UseInst' that follows the DefInst
1460 if the reg defined by DefInst is used by UseInst
1461 mark DefInst as not movable in this iteration
1462 If DefInst is not marked as not-movable, move DefInst to OrdVec
1463 while all instructions in DefInst are moved to OrdVec
1465 For moving, we call the move2OrdVec(). It checks whether there is a def
1466 in it for the uses in the instruction to be added to OrdVec. If there
1467 are no preceding defs, it just appends the instruction. If there is a
1468 preceding def, it puts two instructions to save the reg on stack before
1469 the load and puts a restore at use.
1474 bool DebugPrint = false;
1477 CouldMoveAll = true;
1478 std::vector<MachineInstr *>::iterator DefIt = UnordVec.begin();
1480 for( ; DefIt != UnordVec.end(); ++DefIt ) {
1482 // for each instruction in the UnordVec do ...
1484 MachineInstr *DefInst = *DefIt;
1486 if( DefInst == NULL) continue;
1488 //cerr << "\nInst in UnordVec = " << *DefInst;
1490 // last operand is the def (unless for a store which has no def reg)
1491 MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
1493 if( DefOp.opIsDef() &&
1494 DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1496 // If the operand in DefInst is a def ...
1498 bool DefEqUse = false;
1500 std::vector<MachineInstr *>::iterator UseIt = DefIt;
1503 for( ; UseIt != UnordVec.end(); ++UseIt ) {
1505 MachineInstr *UseInst = *UseIt;
1506 if( UseInst == NULL) continue;
1508 // for each inst (UseInst) that is below the DefInst do ...
1509 MachineOperand& UseOp = UseInst->getOperand(0);
1511 if( ! UseOp.opIsDef() &&
1512 UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1514 // if use is a register ...
1516 if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
1518 // if Def and this use are the same, it means that this use
1519 // is destroyed by a def before it is used
1521 // cerr << "\nCouldn't move " << *DefInst;
1524 CouldMoveAll = false;
1527 } // if two registers are equal
1529 } // if use is a register
1531 }// for all use instructions
1535 // after examining all the instructions that follow the DefInst
1536 // if there are no dependencies, we can move it to the OrdVec
1538 // cerr << "Moved to Ord: " << *DefInst;
1540 moveInst2OrdVec(OrdVec, DefInst, PRA);
1542 //OrdVec.push_back(DefInst);
1544 // mark the pos of DefInst with NULL to indicate that it is
1549 } // if Def is a machine register
1551 } // for all instructions in the UnordVec
1554 } while(!CouldMoveAll);
1556 if (DebugPrint && DEBUG_RA) {
1557 cerr << "\nAdded instructions were reordered to:\n";
1558 for(unsigned int i=0; i < OrdVec.size(); i++)
1559 cerr << *(OrdVec[i]);
1567 void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
1568 MachineInstr *UnordInst,
1569 PhyRegAlloc &PRA) const {
1570 MachineOperand& UseOp = UnordInst->getOperand(0);
1572 if( ! UseOp.opIsDef() &&
1573 UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1575 // for the use of UnordInst, see whether there is a defining instr
1576 // before in the OrdVec
1577 bool DefEqUse = false;
1579 std::vector<MachineInstr *>::iterator OrdIt = OrdVec.begin();
1581 for( ; OrdIt != OrdVec.end(); ++OrdIt ) {
1583 MachineInstr *OrdInst = *OrdIt ;
1585 MachineOperand& DefOp =
1586 OrdInst->getOperand(OrdInst->getNumOperands()-1);
1588 if( DefOp.opIsDef() &&
1589 DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1591 //cerr << "\nDefining Ord Inst: " << *OrdInst;
1593 if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
1595 // we are here because there is a preceding def in the OrdVec
1596 // for the use in this intr we are going to insert. This
1597 // happened because the original code was like:
1598 // 1. add %ox %g0 %oy
1599 // 2. add %oy %g0 %ox
1600 // In Round1, we added 2 to OrdVec but 1 remained in UnordVec
1601 // Now we are processing %ox of 1.
1604 const int UReg = DefOp.getMachineRegNum();
1605 const int RegType = getRegType(UReg);
1606 MachineInstr *AdIBef, *AdIAft;
1608 const int StackOff = PRA.mcInfo.pushTempValue(target,
1609 getSpilledRegSize(RegType));
1611 // Save the UReg (%ox) on stack before it's destroyed
1612 vector<MachineInstr*> mvec;
1613 cpReg2MemMI(UReg, getFramePointer(), StackOff, RegType, mvec);
1614 for (vector<MachineInstr*>::iterator MI=mvec.begin(); MI != mvec.end(); ++MI) {
1615 OrdIt = OrdVec.insert(OrdIt, *MI);
1616 ++OrdIt; // OrdIt must still point to current instr we processed
1619 // Load directly into DReg (%oy)
1620 MachineOperand& DOp=
1621 (UnordInst->getOperand(UnordInst->getNumOperands()-1));
1622 assert(DOp.opIsDef() && "Last operand is not the def");
1623 const int DReg = DOp.getMachineRegNum();
1625 cpMem2RegMI(getFramePointer(), StackOff, DReg, RegType, OrdVec);
1627 cerr << "\nFixed CIRCULAR references by reordering";
1630 cerr << "\nBefore CIRCULAR Reordering:\n";
1634 cerr << "\nAfter CIRCULAR Reordering - All Inst so far:\n";
1635 for(unsigned i=0; i < OrdVec.size(); i++)
1636 cerr << *(OrdVec[i]);
1639 // Do not copy the UseInst to OrdVec
1643 }// if two registers are equal
1645 } // if Def is a register
1647 } // for each instr in OrdVec
1651 // We didn't find a def in the OrdVec, so just append this inst
1652 OrdVec.push_back( UnordInst );
1653 //cerr << "Reordered Inst (Moved Dn): " << *UnordInst;
1656 }// if the operand in UnordInst is a use