1 //===-- SparcRegInfo.cpp - Sparc Target Register Information --------------===//
3 // This file contains implementation of Sparc specific helper methods
4 // used for register allocation.
6 //===----------------------------------------------------------------------===//
8 #include "SparcInternals.h"
9 #include "SparcRegClassInfo.h"
10 #include "llvm/Target/Sparc.h"
11 #include "llvm/CodeGen/MachineCodeForMethod.h"
12 #include "llvm/CodeGen/PhyRegAlloc.h"
13 #include "llvm/CodeGen/MachineInstr.h"
14 #include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h"
15 #include "llvm/iTerminators.h"
16 #include "llvm/iOther.h"
17 #include "llvm/DerivedTypes.h"
21 UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
22 : MachineRegInfo(tgt), UltraSparcInfo(&tgt), NumOfIntArgRegs(6),
23 NumOfFloatArgRegs(32), InvalidRegNum(1000) {
25 MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID));
26 MachineRegClassArr.push_back(new SparcFloatRegClass(FloatRegClassID));
27 MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID));
28 MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID));
30 assert(SparcFloatRegOrder::StartOfNonVolatileRegs == 32 &&
31 "32 Float regs are used for float arg passing");
35 // getZeroRegNum - returns the register that contains always zero.
36 // this is the unified register number
38 int UltraSparcRegInfo::getZeroRegNum() const {
39 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
40 SparcIntRegOrder::g0);
43 // getCallAddressReg - returns the reg used for pushing the address when a
44 // method is called. This can be used for other purposes between calls
46 unsigned UltraSparcRegInfo::getCallAddressReg() const {
47 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
48 SparcIntRegOrder::o7);
51 // Returns the register containing the return address.
52 // It should be made sure that this register contains the return
53 // value when a return instruction is reached.
55 unsigned UltraSparcRegInfo::getReturnAddressReg() const {
56 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
57 SparcIntRegOrder::i7);
60 // given the unified register number, this gives the name
61 // for generating assembly code or debugging.
63 const std::string UltraSparcRegInfo::getUnifiedRegName(int reg) const {
65 return SparcIntRegOrder::getRegName(reg);
66 else if ( reg < (64 + 32) )
67 return SparcFloatRegOrder::getRegName( reg - 32);
68 else if( reg < (64+32+4) )
69 return SparcFloatCCRegOrder::getRegName( reg -32 - 64);
70 else if( reg < (64+32+4+2) ) // two names: %xcc and %ccr
71 return SparcIntCCRegOrder::getRegName( reg -32 - 64 - 4);
72 else if (reg== InvalidRegNum) //****** TODO: Remove */
75 assert(0 && "Invalid register number");
79 // Get unified reg number for frame pointer
80 unsigned UltraSparcRegInfo::getFramePointer() const {
81 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
82 SparcIntRegOrder::i6);
85 // Get unified reg number for stack pointer
86 unsigned UltraSparcRegInfo::getStackPointer() const {
87 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
88 SparcIntRegOrder::o6);
93 //---------------------------------------------------------------------------
94 // Finds the return value of a sparc specific call instruction
95 //---------------------------------------------------------------------------
97 UltraSparcRegInfo::getCallInstRetVal(const MachineInstr *CallMI) const {
98 unsigned OpCode = CallMI->getOpCode();
99 unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
101 if (OpCode == CALL) {
103 // The one before the last implicit operand is the return value of
106 if( NumOfImpRefs > 1 )
107 if (CallMI->implicitRefIsDefined(NumOfImpRefs-2))
108 return CallMI->getImplicitRef(NumOfImpRefs-2);
110 } else if (OpCode == JMPLCALL) {
112 // The last implicit operand is the return value of a JMPL
115 if (CallMI->implicitRefIsDefined(NumOfImpRefs-1))
116 return CallMI->getImplicitRef(NumOfImpRefs-1);
118 assert(0 && "OpCode must be CALL/JMPL for a call instr");
125 //---------------------------------------------------------------------------
126 // Finds the return address of a call sparc specific call instruction
127 //---------------------------------------------------------------------------
129 UltraSparcRegInfo::getCallInstRetAddr(const MachineInstr *CallMI) const {
130 unsigned OpCode = CallMI->getOpCode();
132 if (OpCode == CALL) {
133 unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
135 assert( NumOfImpRefs && "CALL instr must have at least on ImpRef");
137 // The last implicit operand is the return address of a CALL instr
139 return CallMI->getImplicitRef(NumOfImpRefs-1);
141 } else if(OpCode == JMPLCALL) {
142 MachineOperand &MO = (MachineOperand &)CallMI->getOperand(2);
143 return MO.getVRegValue();
146 assert(0 && "OpCode must be CALL/JMPL for a call instr");
150 // The following 3 methods are used to find the RegType (see enum above)
151 // of a LiveRange, Value and using the unified RegClassID
153 int UltraSparcRegInfo::getRegType(const LiveRange *LR) const {
154 switch (LR->getRegClass()->getID()) {
155 case IntRegClassID: return IntRegType;
156 case FloatRegClassID: {
157 const Type *Typ = LR->getType();
158 if (Typ == Type::FloatTy)
159 return FPSingleRegType;
160 else if (Typ == Type::DoubleTy)
161 return FPDoubleRegType;
162 assert(0 && "Unknown type in FloatRegClass");
164 case IntCCRegClassID: return IntCCRegType;
165 case FloatCCRegClassID: return FloatCCRegType;
166 default: assert( 0 && "Unknown reg class ID");
171 int UltraSparcRegInfo::getRegType(const Value *Val) const {
174 switch (getRegClassIDOfValue(Val)) {
175 case IntRegClassID: return IntRegType;
176 case FloatRegClassID:
177 Typ = Val->getType()->getPrimitiveID();
178 if (Typ == Type::FloatTyID)
179 return FPSingleRegType;
180 else if (Typ == Type::DoubleTyID)
181 return FPDoubleRegType;
182 assert(0 && "Unknown type in FloatRegClass");
184 case IntCCRegClassID: return IntCCRegType;
185 case FloatCCRegClassID: return FloatCCRegType ;
186 default: assert(0 && "Unknown reg class ID");
191 int UltraSparcRegInfo::getRegType(int reg) const {
194 else if (reg < (32 + 32))
195 return FPSingleRegType;
196 else if (reg < (64 + 32))
197 return FPDoubleRegType;
198 else if (reg < (64+32+4))
199 return FloatCCRegType;
200 else if (reg < (64+32+4+2))
203 assert(0 && "Invalid register number in getRegType");
211 //---------------------------------------------------------------------------
212 // Finds the # of actual arguments of the call instruction
213 //---------------------------------------------------------------------------
215 UltraSparcRegInfo::getCallInstNumArgs(const MachineInstr *CallMI) const {
217 unsigned OpCode = CallMI->getOpCode();
218 unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
220 if (OpCode == CALL) {
221 switch (NumOfImpRefs) {
222 case 0: assert(0 && "A CALL inst must have at least one ImpRef (RetAddr)");
224 default: // two or more implicit refs
225 if (CallMI->implicitRefIsDefined(NumOfImpRefs-2))
226 return NumOfImpRefs - 2;
228 return NumOfImpRefs - 1;
230 } else if (OpCode == JMPLCALL) {
232 // The last implicit operand is the return value of a JMPL instr
233 if( NumOfImpRefs > 0 ) {
234 if (CallMI->implicitRefIsDefined(NumOfImpRefs-1))
235 return NumOfImpRefs - 1;
243 assert(0 && "OpCode must be CALL/JMPL for a call instr");
249 //---------------------------------------------------------------------------
250 // Finds whether a call is an indirect call
251 //---------------------------------------------------------------------------
252 bool UltraSparcRegInfo::isVarArgCall(const MachineInstr *CallMI) const {
254 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
256 const MachineOperand & calleeOp = CallMI->getOperand(0);
257 Value *calleeVal = calleeOp.getVRegValue();
259 PointerType *PT = cast<PointerType> (calleeVal->getType());
260 MethodType *MT = cast<MethodType>(PT->getElementType());
262 return MT->isVarArg();
268 //---------------------------------------------------------------------------
269 // Suggests a register for the ret address in the RET machine instruction.
270 // We always suggest %i7 by convention.
271 //---------------------------------------------------------------------------
272 void UltraSparcRegInfo::suggestReg4RetAddr(const MachineInstr *RetMI,
273 LiveRangeInfo& LRI) const {
275 assert( (RetMI->getNumOperands() >= 2)
276 && "JMPL/RETURN must have 3 and 2 operands respectively");
278 MachineOperand & MO = ( MachineOperand &) RetMI->getOperand(0);
280 // return address is always mapped to i7
282 MO.setRegForValue( getUnifiedRegNum( IntRegClassID, SparcIntRegOrder::i7) );
284 // Possible Optimization:
285 // Instead of setting the color, we can suggest one. In that case,
286 // we have to test later whether it received the suggested color.
287 // In that case, a LR has to be created at the start of method.
288 // It has to be done as follows (remove the setRegVal above):
290 // const Value *RetAddrVal = MO.getVRegValue();
291 // assert( RetAddrVal && "LR for ret address must be created at start");
292 // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
293 // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
294 // SparcIntRegOrdr::i7) );
298 //---------------------------------------------------------------------------
299 // Suggests a register for the ret address in the JMPL/CALL machine instr.
300 // Sparc ABI dictates that %o7 be used for this purpose.
301 //---------------------------------------------------------------------------
302 void UltraSparcRegInfo::suggestReg4CallAddr(const MachineInstr * CallMI,
304 std::vector<RegClass *> RCList) const {
307 const Value *RetAddrVal = getCallInstRetAddr( CallMI );
309 // RetAddrVal cannot be NULL (asserted in getCallInstRetAddr)
310 // create a new LR for the return address and color it
312 LiveRange * RetAddrLR = new LiveRange();
313 RetAddrLR->insert( RetAddrVal );
314 unsigned RegClassID = getRegClassIDOfValue( RetAddrVal );
315 RetAddrLR->setRegClass( RCList[RegClassID] );
316 RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o7));
317 LRI.addLRToMap( RetAddrVal, RetAddrLR);
324 //---------------------------------------------------------------------------
325 // This method will suggest colors to incoming args to a method.
326 // According to the Sparc ABI, the first 6 incoming args are in
327 // %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float).
328 // If the arg is passed on stack due to the lack of regs, NOTHING will be
329 // done - it will be colored (or spilled) as a normal live range.
330 //---------------------------------------------------------------------------
331 void UltraSparcRegInfo::suggestRegs4MethodArgs(const Method *Meth,
332 LiveRangeInfo& LRI) const
335 // get the argument list
336 const Method::ArgumentListType& ArgList = Meth->getArgumentList();
337 // get an iterator to arg list
338 Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
341 for( unsigned argNo=0; ArgIt != ArgList.end() ; ++ArgIt, ++argNo) {
344 LiveRange *const LR = LRI.getLiveRangeForValue((const Value *) *ArgIt);
345 assert( LR && "No live range found for method arg");
347 unsigned RegType = getRegType( LR );
350 // if the arg is in int class - allocate a reg for an int arg
352 if( RegType == IntRegType ) {
354 if( argNo < NumOfIntArgRegs) {
355 LR->setSuggestedColor( SparcIntRegOrder::i0 + argNo );
358 // Do NOTHING as this will be colored as a normal value.
359 if (DEBUG_RA) cerr << " Int Regr not suggested for method arg\n";
363 else if( RegType==FPSingleRegType && (argNo*2+1) < NumOfFloatArgRegs)
364 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2 + 1) );
367 else if( RegType == FPDoubleRegType && (argNo*2) < NumOfFloatArgRegs)
368 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2) );
375 //---------------------------------------------------------------------------
376 // This method is called after graph coloring to move incoming args to
377 // the correct hardware registers if they did not receive the correct
378 // (suggested) color through graph coloring.
379 //---------------------------------------------------------------------------
380 void UltraSparcRegInfo::colorMethodArgs(const Method *Meth,
382 AddedInstrns *FirstAI) const {
384 // get the argument list
385 const Method::ArgumentListType& ArgList = Meth->getArgumentList();
386 // get an iterator to arg list
387 Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
393 for( unsigned argNo=0; ArgIt != ArgList.end() ; ++ArgIt, ++argNo) {
396 LiveRange *const LR = LRI.getLiveRangeForValue((const Value *) *ArgIt);
397 assert( LR && "No live range found for method arg");
400 unsigned RegType = getRegType( LR );
401 unsigned RegClassID = (LR->getRegClass())->getID();
403 // Find whether this argument is coming in a register (if not, on stack)
404 // Also find the correct register that the argument must go (UniArgReg)
406 bool isArgInReg = false;
407 unsigned UniArgReg = InvalidRegNum; // reg that LR MUST be colored with
409 if( (RegType== IntRegType && argNo < NumOfIntArgRegs)) {
411 UniArgReg = getUnifiedRegNum( RegClassID, SparcIntRegOrder::i0 + argNo );
413 else if(RegType == FPSingleRegType && argNo < NumOfFloatArgRegs) {
415 UniArgReg = getUnifiedRegNum( RegClassID,
416 SparcFloatRegOrder::f0 + argNo*2 + 1 ) ;
418 else if(RegType == FPDoubleRegType && argNo < NumOfFloatArgRegs) {
420 UniArgReg = getUnifiedRegNum(RegClassID, SparcFloatRegOrder::f0+argNo*2);
424 if( LR->hasColor() ) { // if this arg received a register
426 unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
428 // if LR received the correct color, nothing to do
430 if( UniLRReg == UniArgReg )
433 // We are here because the LR did not receive the suggested
434 // but LR received another register.
435 // Now we have to copy the %i reg (or stack pos of arg)
436 // to the register the LR was colored with.
438 // if the arg is coming in UniArgReg register, it MUST go into
439 // the UniLRReg register
442 AdMI = cpReg2RegMI( UniArgReg, UniLRReg, RegType );
446 // Now the arg is coming on stack. Since the LR recieved a register,
447 // we just have to load the arg on stack into that register
449 const MachineFrameInfo& frameInfo = target.getFrameInfo();
450 assert(frameInfo.argsOnStackHaveFixedSize());
452 bool growUp; // find the offset of arg in stack frame
454 frameInfo.getFirstIncomingArgOffset(MachineCodeForMethod::get(Meth),
457 growUp? firstArg + argNo * frameInfo.getSizeOfEachArgOnStack()
458 : firstArg - argNo * frameInfo.getSizeOfEachArgOnStack();
460 AdMI = cpMem2RegMI(getFramePointer(), offsetFromFP,
464 FirstAI->InstrnsBefore.push_back( AdMI );
466 } // if LR received a color
470 // Now, the LR did not receive a color. But it has a stack offset for
472 // So, if the arg is coming in UniArgReg register, we can just move
473 // that on to the stack pos of LR
476 cpReg2MemMI(UniArgReg, getFramePointer(),
477 LR->getSpillOffFromFP(), RegType );
479 FirstAI->InstrnsBefore.push_back( AdMI );
484 // Now the arg is coming on stack. Since the LR did NOT
485 // recieved a register as well, it is allocated a stack position. We
486 // can simply change the stack poistion of the LR. We can do this,
487 // since this method is called before any other method that makes
488 // uses of the stack pos of the LR (e.g., updateMachineInstr)
490 const MachineFrameInfo& frameInfo = target.getFrameInfo();
491 assert(frameInfo.argsOnStackHaveFixedSize());
494 int firstArg = frameInfo.getFirstIncomingArgOffset(MachineCodeForMethod::get(Meth), growUp);
496 growUp? firstArg + argNo * frameInfo.getSizeOfEachArgOnStack()
497 : firstArg - argNo * frameInfo.getSizeOfEachArgOnStack();
499 LR->modifySpillOffFromFP( offsetFromFP );
504 } // for each incoming argument
510 //---------------------------------------------------------------------------
511 // This method is called before graph coloring to suggest colors to the
512 // outgoing call args and the return value of the call.
513 //---------------------------------------------------------------------------
514 void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *CallMI,
516 std::vector<RegClass *> RCList) const {
518 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
520 suggestReg4CallAddr(CallMI, LRI, RCList);
523 // First color the return value of the call instruction. The return value
524 // will be in %o0 if the value is an integer type, or in %f0 if the
525 // value is a float type.
527 // the return value cannot have a LR in machine instruction since it is
528 // only defined by the call instruction
530 // if type is not void, create a new live range and set its
531 // register class and add to LRI
534 const Value *RetVal = getCallInstRetVal( CallMI );
538 assert ((!LRI.getLiveRangeForValue(RetVal)) &&
539 "LR for ret Value of call already definded!");
541 // create a new LR for the return value
542 LiveRange *RetValLR = new LiveRange();
543 RetValLR->insert(RetVal);
544 unsigned RegClassID = getRegClassIDOfValue(RetVal);
545 RetValLR->setRegClass(RCList[RegClassID]);
546 LRI.addLRToMap(RetVal, RetValLR);
548 // now suggest a register depending on the register class of ret arg
550 if( RegClassID == IntRegClassID )
551 RetValLR->setSuggestedColor(SparcIntRegOrder::o0);
552 else if (RegClassID == FloatRegClassID )
553 RetValLR->setSuggestedColor(SparcFloatRegOrder::f0 );
554 else assert( 0 && "Unknown reg class for return value of call\n");
558 // Now suggest colors for arguments (operands) of the call instruction.
559 // Colors are suggested only if the arg number is smaller than the
560 // the number of registers allocated for argument passing.
561 // Now, go thru call args - implicit operands of the call MI
563 unsigned NumOfCallArgs = getCallInstNumArgs( CallMI );
565 for(unsigned argNo=0, i=0; i < NumOfCallArgs; ++i, ++argNo ) {
567 const Value *CallArg = CallMI->getImplicitRef(i);
569 // get the LR of call operand (parameter)
570 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
572 // not possible to have a null LR since all args (even consts)
573 // must be defined before
575 cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) << "\n";
576 assert(0 && "NO LR for call arg");
579 unsigned RegType = getRegType( LR );
581 // if the arg is in int class - allocate a reg for an int arg
582 if( RegType == IntRegType ) {
584 if( argNo < NumOfIntArgRegs)
585 LR->setSuggestedColor( SparcIntRegOrder::o0 + argNo );
588 // Do NOTHING as this will be colored as a normal value.
589 cerr << " Regr not suggested for int call arg\n";
592 else if( RegType == FPSingleRegType && (argNo*2 +1)< NumOfFloatArgRegs)
593 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2 + 1) );
596 else if( RegType == FPDoubleRegType && (argNo*2) < NumOfFloatArgRegs)
597 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2) );
600 } // for all call arguments
605 //---------------------------------------------------------------------------
606 // After graph coloring, we have call this method to see whehter the return
607 // value and the call args received the correct colors. If not, we have
608 // to instert copy instructions.
609 //---------------------------------------------------------------------------
611 void UltraSparcRegInfo::colorCallArgs(const MachineInstr *CallMI,
613 AddedInstrns *CallAI,
615 const BasicBlock *BB) const {
617 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
619 // Reset the optional args area in the stack frame
620 // since that is reused for each call
622 PRA.mcInfo.resetOptionalArgs(target);
624 // First color the return value of the call.
625 // If there is a LR for the return value, it means this
626 // method returns a value
630 const Value *RetVal = getCallInstRetVal( CallMI );
633 LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal );
636 cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
637 assert(0 && "ERR:No LR for non-void return value");
640 unsigned RegClassID = (RetValLR->getRegClass())->getID();
641 bool recvCorrectColor = false;
643 unsigned CorrectCol; // correct color for ret value
644 if(RegClassID == IntRegClassID)
645 CorrectCol = SparcIntRegOrder::o0;
646 else if(RegClassID == FloatRegClassID)
647 CorrectCol = SparcFloatRegOrder::f0;
649 assert( 0 && "Unknown RegClass");
653 // if the LR received the correct color, NOTHING to do
655 if( RetValLR->hasColor() )
656 if( RetValLR->getColor() == CorrectCol )
657 recvCorrectColor = true;
660 // if we didn't receive the correct color for some reason,
661 // put copy instruction
663 if( !recvCorrectColor ) {
665 unsigned RegType = getRegType( RetValLR );
667 // the reg that LR must be colored with
668 unsigned UniRetReg = getUnifiedRegNum( RegClassID, CorrectCol);
670 if( RetValLR->hasColor() ) {
673 UniRetLRReg=getUnifiedRegNum(RegClassID,RetValLR->getColor());
675 // the return value is coming in UniRetReg but has to go into
678 AdMI = cpReg2RegMI( UniRetReg, UniRetLRReg, RegType );
683 // if the LR did NOT receive a color, we have to move the return
684 // value coming in UniRetReg to the stack pos of spilled LR
686 AdMI = cpReg2MemMI(UniRetReg, getFramePointer(),
687 RetValLR->getSpillOffFromFP(), RegType );
690 CallAI->InstrnsAfter.push_back( AdMI );
692 } // the LR didn't receive the suggested color
694 } // if there a return value
697 //-------------------------------------------
698 // Now color all args of the call instruction
699 //-------------------------------------------
701 std::vector<MachineInstr *> AddedInstrnsBefore;
703 unsigned NumOfCallArgs = getCallInstNumArgs( CallMI );
705 bool VarArgCall = isVarArgCall( CallMI );
707 if(VarArgCall) cerr << "\nVar arg call found!!\n";
709 for(unsigned argNo=0, i=0; i < NumOfCallArgs; ++i, ++argNo ) {
711 const Value *CallArg = CallMI->getImplicitRef(i);
713 // get the LR of call operand (parameter)
714 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
716 unsigned RegType = getRegType( CallArg );
717 unsigned RegClassID = getRegClassIDOfValue( CallArg);
719 // find whether this argument is coming in a register (if not, on stack)
721 bool isArgInReg = false;
722 unsigned UniArgReg = InvalidRegNum; // reg that LR must be colored with
724 if( (RegType== IntRegType && argNo < NumOfIntArgRegs)) {
726 UniArgReg = getUnifiedRegNum(RegClassID, SparcIntRegOrder::o0 + argNo );
728 else if(RegType == FPSingleRegType && argNo < NumOfFloatArgRegs) {
732 UniArgReg = getUnifiedRegNum(RegClassID,
733 SparcFloatRegOrder::f0 + (argNo*2 + 1) );
735 // a variable argument call - must pass float arg in %o's
736 if( argNo < NumOfIntArgRegs)
737 UniArgReg=getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o0+argNo);
743 else if(RegType == FPDoubleRegType && argNo < NumOfFloatArgRegs) {
747 UniArgReg =getUnifiedRegNum(RegClassID,SparcFloatRegOrder::f0+argNo*2);
749 // a variable argument call - must pass float arg in %o's
750 if( argNo < NumOfIntArgRegs)
751 UniArgReg=getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o0+argNo);
757 // not possible to have a null LR since all args (even consts)
758 // must be defined before
760 cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) << "\n";
761 assert(0 && "NO LR for call arg");
765 if (LR->hasColor()) {
766 unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
768 // if LR received the correct color, nothing to do
769 if( UniLRReg == UniArgReg )
772 // We are here because though the LR is allocated a register, it
773 // was not allocated the suggested register. So, we have to copy %ix reg
774 // (or stack pos of arg) to the register it was colored with
776 // the LR is colored with UniLRReg but has to go into UniArgReg
777 // to pass it as an argument
781 if( VarArgCall && RegClassID == FloatRegClassID ) {
784 // for a variable argument call, the float reg must go in a %o reg.
785 // We have to move a float reg to an int reg via memory.
786 // The store instruction will be directly added to
787 // CallAI->InstrnsBefore since it does not need reordering
789 int TmpOff = PRA.mcInfo.pushTempValue(target,
790 getSpilledRegSize(RegType));
792 AdMI = cpReg2MemMI(UniLRReg, getFramePointer(), TmpOff, RegType );
793 CallAI->InstrnsBefore.push_back( AdMI );
795 AdMI = cpMem2RegMI(getFramePointer(), TmpOff, UniArgReg, IntRegType);
796 AddedInstrnsBefore.push_back( AdMI );
800 AdMI = cpReg2RegMI(UniLRReg, UniArgReg, RegType );
801 AddedInstrnsBefore.push_back( AdMI );
805 // Now, we have to pass the arg on stack. Since LR received a register
806 // we just have to move that register to the stack position where
807 // the argument must be passed
809 int argOffset = PRA.mcInfo.allocateOptionalArg(target, LR->getType());
811 AdMI = cpReg2MemMI(UniLRReg, getStackPointer(), argOffset, RegType );
813 // Now add the instruction. We can directly add to
814 // CallAI->InstrnsBefore since we are just saving a reg on stack
816 CallAI->InstrnsBefore.push_back( AdMI );
818 //cerr << "\nCaution: Passing a reg on stack";
822 } else { // LR is not colored (i.e., spilled)
826 // Now the LR did NOT recieve a register but has a stack poistion.
827 // Since, the outgoing arg goes in a register we just have to insert
828 // a load instruction to load the LR to outgoing register
830 if( VarArgCall && RegClassID == FloatRegClassID )
831 AdMI = cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
832 UniArgReg, IntRegType );
834 AdMI = cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
835 UniArgReg, RegType );
837 cerr << "\nCaution: Loading a spilled val to a reg as a call arg";
838 AddedInstrnsBefore.push_back( AdMI ); // Now add the instruction
842 // Now, we have to pass the arg on stack. Since LR also did NOT
843 // receive a register we have to move an argument in memory to
844 // outgoing parameter on stack.
846 // Optoimize: Optimize when reverse pointers in MahineInstr are
848 // call PRA.getUnusedRegAtMI(....) to get an unused reg. Only if this
849 // fails, then use the following code. Currently, we cannot call the
850 // above method since we cannot find LVSetBefore without the BB
852 int TReg = PRA.getUniRegNotUsedByThisInst( LR->getRegClass(), CallMI );
854 int TmpOff = PRA.mcInfo.pushTempValue(target,
855 getSpilledRegSize(getRegType(LR)) );
858 int argOffset = PRA.mcInfo.allocateOptionalArg(target, LR->getType());
860 MachineInstr *Ad1, *Ad2, *Ad3, *Ad4;
863 // (1) Save TReg on stack
864 // (2) Load LR value into TReg from stack pos of LR
865 // (3) Store Treg on outgoing Arg pos on stack
866 // (4) Load the old value of TReg from stack to TReg (restore it)
868 Ad1 = cpReg2MemMI(TReg, getFramePointer(), TmpOff, RegType );
869 Ad2 = cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
871 Ad3 = cpReg2MemMI(TReg, getStackPointer(), argOffset, RegType );
872 Ad4 = cpMem2RegMI(getFramePointer(), TmpOff, TReg, RegType );
874 // We directly add to CallAI->InstrnsBefore instead of adding to
875 // AddedInstrnsBefore since these instructions must not be
878 CallAI->InstrnsBefore.push_back( Ad1 );
879 CallAI->InstrnsBefore.push_back( Ad2 );
880 CallAI->InstrnsBefore.push_back( Ad3 );
881 CallAI->InstrnsBefore.push_back( Ad4 );
883 cerr << "\nCaution: Call arg moved from stack2stack for: " << *CallMI ;
886 } // for each parameter in call instruction
889 // if we added any instruction before the call instruction, verify
890 // that they are in the proper order and if not, reorder them
892 if (!AddedInstrnsBefore.empty()) {
895 cerr << "\nCalling reorder with instrns: \n";
896 for(unsigned i=0; i < AddedInstrnsBefore.size(); i++)
897 cerr << *(AddedInstrnsBefore[i]);
900 std::vector<MachineInstr *> TmpVec;
901 OrderAddedInstrns(AddedInstrnsBefore, TmpVec, PRA);
904 cerr << "\nAfter reordering instrns: \n";
905 for(unsigned i = 0; i < TmpVec.size(); i++)
909 // copy the results back from TmpVec to InstrnsBefore
910 for(unsigned i=0; i < TmpVec.size(); i++)
911 CallAI->InstrnsBefore.push_back( TmpVec[i] );
915 // now insert caller saving code for this call instruction
917 insertCallerSavingCode(CallMI, BB, PRA);
919 // Reset optional args area again to be safe
920 PRA.mcInfo.resetOptionalArgs(target);
923 //---------------------------------------------------------------------------
924 // This method is called for an LLVM return instruction to identify which
925 // values will be returned from this method and to suggest colors.
926 //---------------------------------------------------------------------------
927 void UltraSparcRegInfo::suggestReg4RetValue(const MachineInstr *RetMI,
928 LiveRangeInfo &LRI) const {
930 assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) );
932 suggestReg4RetAddr(RetMI, LRI);
934 // if there is an implicit ref, that has to be the ret value
935 if( RetMI->getNumImplicitRefs() > 0 ) {
937 // The first implicit operand is the return value of a return instr
938 const Value *RetVal = RetMI->getImplicitRef(0);
940 LiveRange *const LR = LRI.getLiveRangeForValue( RetVal );
943 cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
944 assert(0 && "No LR for return value of non-void method");
947 unsigned RegClassID = (LR->getRegClass())->getID();
949 if (RegClassID == IntRegClassID)
950 LR->setSuggestedColor(SparcIntRegOrder::i0);
951 else if (RegClassID == FloatRegClassID)
952 LR->setSuggestedColor(SparcFloatRegOrder::f0);
958 //---------------------------------------------------------------------------
959 // Colors the return value of a method to %i0 or %f0, if possible. If it is
960 // not possilbe to directly color the LR, insert a copy instruction to move
961 // the LR to %i0 or %f0. When the LR is spilled, instead of the copy, we
962 // have to put a load instruction.
963 //---------------------------------------------------------------------------
964 void UltraSparcRegInfo::colorRetValue(const MachineInstr *RetMI,
966 AddedInstrns *RetAI) const {
968 assert((UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode()));
970 // if there is an implicit ref, that has to be the ret value
971 if(RetMI->getNumImplicitRefs() > 0) {
973 // The first implicit operand is the return value of a return instr
974 const Value *RetVal = RetMI->getImplicitRef(0);
976 LiveRange *LR = LRI.getLiveRangeForValue(RetVal);
979 cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
980 // assert( LR && "No LR for return value of non-void method");
984 unsigned RegClassID = getRegClassIDOfValue(RetVal);
985 unsigned RegType = getRegType( RetVal );
988 if(RegClassID == IntRegClassID)
989 CorrectCol = SparcIntRegOrder::i0;
990 else if(RegClassID == FloatRegClassID)
991 CorrectCol = SparcFloatRegOrder::f0;
993 assert (0 && "Unknown RegClass");
997 // if the LR received the correct color, NOTHING to do
999 if (LR->hasColor() && LR->getColor() == CorrectCol)
1002 unsigned UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
1004 if (LR->hasColor()) {
1006 // We are here because the LR was allocted a regiter
1007 // It may be the suggested register or not
1009 // copy the LR of retun value to i0 or f0
1011 unsigned UniLRReg =getUnifiedRegNum( RegClassID, LR->getColor());
1013 // the LR received UniLRReg but must be colored with UniRetReg
1014 // to pass as the return value
1015 RetAI->InstrnsBefore.push_back(cpReg2RegMI(UniLRReg, UniRetReg, RegType));
1017 else { // if the LR is spilled
1018 MachineInstr *AdMI = cpMem2RegMI(getFramePointer(),
1019 LR->getSpillOffFromFP(),
1020 UniRetReg, RegType);
1021 RetAI->InstrnsBefore.push_back(AdMI);
1022 cerr << "\nCopied the return value from stack\n";
1025 } // if there is a return value
1030 //---------------------------------------------------------------------------
1031 // Copy from a register to register. Register number must be the unified
1033 //---------------------------------------------------------------------------
1035 MachineInstr * UltraSparcRegInfo::cpReg2RegMI(unsigned SrcReg, unsigned DestReg,
1036 int RegType) const {
1038 assert( ((int)SrcReg != InvalidRegNum) && ((int)DestReg != InvalidRegNum) &&
1039 "Invalid Register");
1041 MachineInstr * MI = NULL;
1047 case FloatCCRegType:
1048 MI = new MachineInstr(ADD, 3);
1049 MI->SetMachineOperandReg(0, SrcReg, false);
1050 MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
1051 MI->SetMachineOperandReg(2, DestReg, true);
1054 case FPSingleRegType:
1055 MI = new MachineInstr(FMOVS, 2);
1056 MI->SetMachineOperandReg(0, SrcReg, false);
1057 MI->SetMachineOperandReg(1, DestReg, true);
1060 case FPDoubleRegType:
1061 MI = new MachineInstr(FMOVD, 2);
1062 MI->SetMachineOperandReg(0, SrcReg, false);
1063 MI->SetMachineOperandReg(1, DestReg, true);
1067 assert(0 && "Unknow RegType");
1074 //---------------------------------------------------------------------------
1075 // Copy from a register to memory (i.e., Store). Register number must
1076 // be the unified register number
1077 //---------------------------------------------------------------------------
1080 MachineInstr * UltraSparcRegInfo::cpReg2MemMI(unsigned SrcReg,
1081 unsigned DestPtrReg,
1082 int Offset, int RegType) const {
1083 MachineInstr * MI = NULL;
1086 case FloatCCRegType:
1087 MI = new MachineInstr(STX, 3);
1088 MI->SetMachineOperandReg(0, SrcReg, false);
1089 MI->SetMachineOperandReg(1, DestPtrReg, false);
1090 MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
1094 case FPSingleRegType:
1095 MI = new MachineInstr(ST, 3);
1096 MI->SetMachineOperandReg(0, SrcReg, false);
1097 MI->SetMachineOperandReg(1, DestPtrReg, false);
1098 MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
1102 case FPDoubleRegType:
1103 MI = new MachineInstr(STD, 3);
1104 MI->SetMachineOperandReg(0, SrcReg, false);
1105 MI->SetMachineOperandReg(1, DestPtrReg, false);
1106 MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
1111 assert( 0 && "Cannot directly store %ccr to memory");
1114 assert(0 && "Unknow RegType in cpReg2MemMI");
1121 //---------------------------------------------------------------------------
1122 // Copy from memory to a reg (i.e., Load) Register number must be the unified
1124 //---------------------------------------------------------------------------
1127 MachineInstr * UltraSparcRegInfo::cpMem2RegMI(unsigned SrcPtrReg,
1130 int RegType) const {
1131 MachineInstr * MI = NULL;
1134 case FloatCCRegType:
1135 MI = new MachineInstr(LDX, 3);
1136 MI->SetMachineOperandReg(0, SrcPtrReg, false);
1137 MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
1139 MI->SetMachineOperandReg(2, DestReg, true);
1142 case FPSingleRegType:
1143 MI = new MachineInstr(LD, 3);
1144 MI->SetMachineOperandReg(0, SrcPtrReg, false);
1145 MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
1147 MI->SetMachineOperandReg(2, DestReg, true);
1151 case FPDoubleRegType:
1152 MI = new MachineInstr(LDD, 3);
1153 MI->SetMachineOperandReg(0, SrcPtrReg, false);
1154 MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
1156 MI->SetMachineOperandReg(2, DestReg, true);
1160 assert( 0 && "Cannot directly load into %ccr from memory");
1163 assert(0 && "Unknown RegType in cpMem2RegMI");
1173 //---------------------------------------------------------------------------
1174 // Generate a copy instruction to copy a value to another. Temporarily
1175 // used by PhiElimination code.
1176 //---------------------------------------------------------------------------
1179 MachineInstr *UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest) const {
1180 int RegType = getRegType( Src );
1182 assert( (RegType==getRegType(Src)) && "Src & Dest are diff types");
1184 MachineInstr * MI = NULL;
1188 MI = new MachineInstr(ADD, 3);
1189 MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
1190 MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
1191 MI->SetMachineOperandVal(2, MachineOperand:: MO_VirtualRegister, Dest, true);
1194 case FPSingleRegType:
1195 MI = new MachineInstr(FMOVS, 2);
1196 MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
1197 MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true);
1201 case FPDoubleRegType:
1202 MI = new MachineInstr(FMOVD, 2);
1203 MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
1204 MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true);
1208 assert(0 && "Unknow RegType in CpValu2Value");
1219 //----------------------------------------------------------------------------
1220 // This method inserts caller saving/restoring instructons before/after
1221 // a call machine instruction. The caller saving/restoring instructions are
1224 // ** caller saving instructions
1225 // other instructions inserted for the call by ColorCallArg
1227 // other instructions inserted for the call ColorCallArg
1228 // ** caller restoring instructions
1230 //----------------------------------------------------------------------------
1233 void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *MInst,
1234 const BasicBlock *BB,
1235 PhyRegAlloc &PRA) const {
1237 // has set to record which registers were saved/restored
1239 std::hash_set<unsigned> PushedRegSet;
1241 // Now find the LR of the return value of the call
1242 // The last *implicit operand* is the return value of a call
1243 // Insert it to to he PushedRegSet since we must not save that register
1244 // and restore it after the call.
1245 // We do this because, we look at the LV set *after* the instruction
1246 // to determine, which LRs must be saved across calls. The return value
1247 // of the call is live in this set - but we must not save/restore it.
1250 const Value *RetVal = getCallInstRetVal( MInst );
1253 LiveRange *RetValLR = PRA.LRI.getLiveRangeForValue( RetVal );
1254 assert(RetValLR && "No LR for RetValue of call");
1256 if (RetValLR->hasColor())
1257 PushedRegSet.insert(
1258 getUnifiedRegNum((RetValLR->getRegClass())->getID(),
1259 RetValLR->getColor() ) );
1263 const ValueSet &LVSetAft = PRA.LVI->getLiveVarSetAfterMInst(MInst, BB);
1264 ValueSet::const_iterator LIt = LVSetAft.begin();
1266 // for each live var in live variable set after machine inst
1267 for( ; LIt != LVSetAft.end(); ++LIt) {
1269 // get the live range corresponding to live var
1270 LiveRange *const LR = PRA.LRI.getLiveRangeForValue(*LIt );
1272 // LR can be null if it is a const since a const
1273 // doesn't have a dominating def - see Assumptions above
1276 if( LR->hasColor() ) {
1278 unsigned RCID = (LR->getRegClass())->getID();
1279 unsigned Color = LR->getColor();
1281 if ( isRegVolatile(RCID, Color) ) {
1283 // if the value is in both LV sets (i.e., live before and after
1284 // the call machine instruction)
1286 unsigned Reg = getUnifiedRegNum(RCID, Color);
1288 if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
1290 // if we haven't already pushed that register
1292 unsigned RegType = getRegType( LR );
1294 // Now get two instructions - to push on stack and pop from stack
1295 // and add them to InstrnsBefore and InstrnsAfter of the
1299 int StackOff = PRA.mcInfo.pushTempValue(target,
1300 getSpilledRegSize(RegType));
1303 MachineInstr *AdIBefCC=NULL, *AdIAftCC=NULL, *AdICpCC;
1304 MachineInstr *AdIBef=NULL, *AdIAft=NULL;
1306 //---- Insert code for pushing the reg on stack ----------
1308 if( RegType == IntCCRegType ) {
1310 // Handle IntCCRegType specially since we cannot directly
1311 // push %ccr on to the stack
1313 const ValueSet &LVSetBef =
1314 PRA.LVI->getLiveVarSetBeforeMInst(MInst, BB);
1316 // get a free INTEGER register
1318 PRA.getUsableUniRegAtMI(PRA.getRegClassByID(IntRegClassID) /*LR->getRegClass()*/,
1319 IntRegType, MInst, &LVSetBef, AdIBefCC, AdIAftCC);
1321 // insert the instructions in reverse order since we are
1322 // adding them to the front of InstrnsBefore
1325 PRA.AddedInstrMap[MInst]->InstrnsBefore.push_front(AdIAftCC);
1327 AdICpCC = cpCCR2IntMI(FreeIntReg);
1328 PRA.AddedInstrMap[MInst]->InstrnsBefore.push_front(AdICpCC);
1331 PRA.AddedInstrMap[MInst]->InstrnsBefore.push_front(AdIBefCC);
1334 cerr << "\n!! Inserted caller saving (push) inst for %ccr:";
1335 if(AdIBefCC) cerr << "\t" << *(AdIBefCC);
1336 cerr << "\t" << *AdICpCC;
1337 if(AdIAftCC) cerr << "\t" << *(AdIAftCC);
1341 // for any other register type, just add the push inst
1342 AdIBef = cpReg2MemMI(Reg, getFramePointer(), StackOff, RegType );
1343 PRA.AddedInstrMap[MInst]->InstrnsBefore.push_front(AdIBef);
1347 //---- Insert code for popping the reg from the stack ----------
1349 if (RegType == IntCCRegType) {
1351 // Handle IntCCRegType specially since we cannot directly
1352 // pop %ccr on from the stack
1354 // get a free INT register
1356 PRA.getUsableUniRegAtMI(PRA.getRegClassByID(IntRegClassID) /* LR->getRegClass()*/,
1357 IntRegType, MInst, &LVSetAft, AdIBefCC, AdIAftCC);
1360 PRA.AddedInstrMap[MInst]->InstrnsAfter.push_back(AdIBefCC);
1362 AdICpCC = cpInt2CCRMI(FreeIntReg);
1363 PRA.AddedInstrMap[MInst]->InstrnsAfter.push_back(AdICpCC);
1366 PRA.AddedInstrMap[MInst]->InstrnsAfter.push_back(AdIAftCC);
1370 cerr << "\n!! Inserted caller saving (pop) inst for %ccr:";
1371 if(AdIBefCC) cerr << "\t" << *(AdIBefCC);
1372 cerr << "\t" << *AdICpCC;
1373 if(AdIAftCC) cerr << "\t" << *(AdIAftCC);
1377 // for any other register type, just add the pop inst
1378 AdIAft = cpMem2RegMI(getFramePointer(), StackOff, Reg, RegType );
1379 PRA.AddedInstrMap[MInst]->InstrnsAfter.push_back(AdIAft);
1382 PushedRegSet.insert(Reg);
1385 cerr << "\nFor call inst:" << *MInst;
1386 cerr << " -inserted caller saving instrs:\n\t ";
1387 if( RegType == IntCCRegType ) {
1388 if(AdIBefCC) cerr << *AdIBefCC << "\t";
1389 if(AdIAftCC) cerr << *AdIAftCC;
1392 if(AdIBef) cerr << *AdIBef << "\t";
1393 if(AdIAft) cerr << *AdIAft;
1396 } // if not already pushed
1398 } // if LR has a volatile color
1400 } // if LR has color
1402 } // if there is a LR for Var
1404 } // for each value in the LV set after instruction
1408 //---------------------------------------------------------------------------
1409 // Copies %ccr into an integer register. IntReg is the UNIFIED register
1411 //---------------------------------------------------------------------------
1413 MachineInstr * UltraSparcRegInfo::cpCCR2IntMI(unsigned IntReg) const {
1414 MachineInstr * MI = new MachineInstr(RDCCR, 2);
1415 MI->SetMachineOperandReg(0, this->getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID,
1416 SparcIntCCRegOrder::ccr),
1418 MI->SetMachineOperandReg(1, IntReg, true);
1422 //---------------------------------------------------------------------------
1423 // Copies an integer register into %ccr. IntReg is the UNIFIED register
1425 //---------------------------------------------------------------------------
1427 MachineInstr *UltraSparcRegInfo::cpInt2CCRMI(unsigned IntReg) const {
1428 MachineInstr *MI = new MachineInstr(WRCCR, 3);
1429 MI->SetMachineOperandReg(0, IntReg, false);
1430 MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
1431 MI->SetMachineOperandReg(2, this->getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID, SparcIntCCRegOrder::ccr),
1439 //---------------------------------------------------------------------------
1440 // Print the register assigned to a LR
1441 //---------------------------------------------------------------------------
1443 void UltraSparcRegInfo::printReg(const LiveRange *LR) {
1444 unsigned RegClassID = (LR->getRegClass())->getID();
1445 cerr << " *Node " << (LR->getUserIGNode())->getIndex();
1447 if (!LR->hasColor()) {
1448 cerr << " - could not find a color\n";
1452 // if a color is found
1454 cerr << " colored with color "<< LR->getColor();
1456 if (RegClassID == IntRegClassID) {
1457 cerr<< " [" << SparcIntRegOrder::getRegName(LR->getColor()) << "]\n";
1459 } else if (RegClassID == FloatRegClassID) {
1460 cerr << "[" << SparcFloatRegOrder::getRegName(LR->getColor());
1461 if( LR->getType() == Type::DoubleTy)
1462 cerr << "+" << SparcFloatRegOrder::getRegName(LR->getColor()+1);
1467 //---------------------------------------------------------------------------
1468 // This method examines instructions inserted by RegAlloc code before a
1469 // machine instruction to detect invalid orders that destroy values before
1470 // they are used. If it detects such conditions, it reorders the instructions.
1472 // The unordered instructions come in the UnordVec. These instructions are
1473 // instructions inserted by RegAlloc. All such instruction MUST have
1474 // their USES BEFORE THE DEFS after reordering.
1476 // The UnordVec & OrdVec must be DISTINCT. The OrdVec must be empty when
1477 // this method is called.
1479 // This method uses two vectors for efficiency in accessing
1481 // Since instructions are inserted in RegAlloc, this assumes that the
1482 // first operand is the source reg and the last operand is the dest reg.
1484 // All the uses are before THE def to a register
1487 //---------------------------------------------------------------------------
1488 void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
1489 std::vector<MachineInstr *> &OrdVec,
1490 PhyRegAlloc &PRA) const{
1493 Problem: We can have instructions inserted by RegAlloc like
1495 2. add %oy %g0 %oz, where z!=x or z==x
1497 This is wrong since %oy used by 2 is overwritten by 1
1500 We re-order the instructions so that the uses are before the defs
1505 for each instruction 'DefInst' in the UnOrdVec
1506 for each instruction 'UseInst' that follows the DefInst
1507 if the reg defined by DefInst is used by UseInst
1508 mark DefInst as not movable in this iteration
1509 If DefInst is not marked as not-movable, move DefInst to OrdVec
1510 while all instructions in DefInst are moved to OrdVec
1512 For moving, we call the move2OrdVec(). It checks whether there is a def
1513 in it for the uses in the instruction to be added to OrdVec. If there
1514 are no preceding defs, it just appends the instruction. If there is a
1515 preceding def, it puts two instructions to save the reg on stack before
1516 the load and puts a restore at use.
1521 bool DebugPrint = false;
1524 CouldMoveAll = true;
1525 std::vector<MachineInstr *>::iterator DefIt = UnordVec.begin();
1527 for( ; DefIt != UnordVec.end(); ++DefIt ) {
1529 // for each instruction in the UnordVec do ...
1531 MachineInstr *DefInst = *DefIt;
1533 if( DefInst == NULL) continue;
1535 //cerr << "\nInst in UnordVec = " << *DefInst;
1537 // last operand is the def (unless for a store which has no def reg)
1538 MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
1540 if( DefOp.opIsDef() &&
1541 DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1543 // If the operand in DefInst is a def ...
1545 bool DefEqUse = false;
1547 std::vector<MachineInstr *>::iterator UseIt = DefIt;
1550 for( ; UseIt != UnordVec.end(); ++UseIt ) {
1552 MachineInstr *UseInst = *UseIt;
1553 if( UseInst == NULL) continue;
1555 // for each inst (UseInst) that is below the DefInst do ...
1556 MachineOperand& UseOp = UseInst->getOperand(0);
1558 if( ! UseOp.opIsDef() &&
1559 UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1561 // if use is a register ...
1563 if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
1565 // if Def and this use are the same, it means that this use
1566 // is destroyed by a def before it is used
1568 // cerr << "\nCouldn't move " << *DefInst;
1571 CouldMoveAll = false;
1574 } // if two registers are equal
1576 } // if use is a register
1578 }// for all use instructions
1582 // after examining all the instructions that follow the DefInst
1583 // if there are no dependencies, we can move it to the OrdVec
1585 // cerr << "Moved to Ord: " << *DefInst;
1587 moveInst2OrdVec(OrdVec, DefInst, PRA);
1589 //OrdVec.push_back(DefInst);
1591 // mark the pos of DefInst with NULL to indicate that it is
1596 } // if Def is a machine register
1598 } // for all instructions in the UnordVec
1601 } while(!CouldMoveAll);
1604 cerr << "\nAdded instructions were reordered to:\n";
1605 for(unsigned int i=0; i < OrdVec.size(); i++)
1606 cerr << *(OrdVec[i]);
1614 void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
1615 MachineInstr *UnordInst,
1616 PhyRegAlloc &PRA) const {
1617 MachineOperand& UseOp = UnordInst->getOperand(0);
1619 if( ! UseOp.opIsDef() &&
1620 UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1622 // for the use of UnordInst, see whether there is a defining instr
1623 // before in the OrdVec
1624 bool DefEqUse = false;
1626 std::vector<MachineInstr *>::iterator OrdIt = OrdVec.begin();
1628 for( ; OrdIt != OrdVec.end(); ++OrdIt ) {
1630 MachineInstr *OrdInst = *OrdIt ;
1632 MachineOperand& DefOp =
1633 OrdInst->getOperand(OrdInst->getNumOperands()-1);
1635 if( DefOp.opIsDef() &&
1636 DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1638 //cerr << "\nDefining Ord Inst: " << *OrdInst;
1640 if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
1642 // we are here because there is a preceding def in the OrdVec
1643 // for the use in this intr we are going to insert. This
1644 // happened because the original code was like:
1645 // 1. add %ox %g0 %oy
1646 // 2. add %oy %g0 %ox
1647 // In Round1, we added 2 to OrdVec but 1 remained in UnordVec
1648 // Now we are processing %ox of 1.
1651 const int UReg = DefOp.getMachineRegNum();
1652 const int RegType = getRegType(UReg);
1653 MachineInstr *AdIBef, *AdIAft;
1655 const int StackOff = PRA.mcInfo.pushTempValue(target,
1656 getSpilledRegSize(RegType));
1658 // Save the UReg (%ox) on stack before it's destroyed
1659 AdIBef=cpReg2MemMI(UReg, getFramePointer(), StackOff, RegType);
1660 OrdIt = OrdVec.insert( OrdIt, AdIBef);
1661 OrdIt++; // points to current instr we processed
1663 // Load directly into DReg (%oy)
1664 MachineOperand& DOp=
1665 (UnordInst->getOperand(UnordInst->getNumOperands()-1));
1666 assert(DOp.opIsDef() && "Last operand is not the def");
1667 const int DReg = DOp.getMachineRegNum();
1669 AdIAft=cpMem2RegMI(getFramePointer(), StackOff, DReg, RegType);
1670 OrdVec.push_back(AdIAft);
1672 cerr << "\nFixed CIRCULAR references by reordering";
1675 cerr << "\nBefore CIRCULAR Reordering:\n";
1679 cerr << "\nAfter CIRCULAR Reordering - All Inst so far:\n";
1680 for(unsigned i=0; i < OrdVec.size(); i++)
1681 cerr << *(OrdVec[i]);
1684 // Do not copy the UseInst to OrdVec
1688 }// if two registers are equal
1690 } // if Def is a register
1692 } // for each instr in OrdVec
1696 // We didn't find a def in the OrdVec, so just append this inst
1697 OrdVec.push_back( UnordInst );
1698 //cerr << "Reordered Inst (Moved Dn): " << *UnordInst;
1701 }// if the operand in UnordInst is a use