1 //===-- SparcRegInfo.cpp - Sparc Target Register Information --------------===//
3 // This file contains implementation of Sparc specific helper methods
4 // used for register allocation.
6 //===----------------------------------------------------------------------===//
8 #include "SparcInternals.h"
9 #include "SparcRegClassInfo.h"
10 #include "llvm/Target/Sparc.h"
11 #include "llvm/CodeGen/MachineCodeForMethod.h"
12 #include "llvm/CodeGen/PhyRegAlloc.h"
13 #include "llvm/CodeGen/InstrSelection.h"
14 #include "llvm/CodeGen/InstrSelectionSupport.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/CodeGen/MachineInstrAnnot.h"
17 #include "llvm/CodeGen/RegAllocCommon.h"
18 #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h"
19 #include "llvm/iTerminators.h"
20 #include "llvm/iOther.h"
21 #include "llvm/Function.h"
22 #include "llvm/DerivedTypes.h"
28 UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
29 : MachineRegInfo(tgt), UltraSparcInfo(&tgt), NumOfIntArgRegs(6),
30 NumOfFloatArgRegs(32), InvalidRegNum(1000) {
32 MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID));
33 MachineRegClassArr.push_back(new SparcFloatRegClass(FloatRegClassID));
34 MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID));
35 MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID));
37 assert(SparcFloatRegOrder::StartOfNonVolatileRegs == 32 &&
38 "32 Float regs are used for float arg passing");
42 // getZeroRegNum - returns the register that contains always zero.
43 // this is the unified register number
45 int UltraSparcRegInfo::getZeroRegNum() const {
46 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
47 SparcIntRegOrder::g0);
50 // getCallAddressReg - returns the reg used for pushing the address when a
51 // method is called. This can be used for other purposes between calls
53 unsigned UltraSparcRegInfo::getCallAddressReg() const {
54 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
55 SparcIntRegOrder::o7);
58 // Returns the register containing the return address.
59 // It should be made sure that this register contains the return
60 // value when a return instruction is reached.
62 unsigned UltraSparcRegInfo::getReturnAddressReg() const {
63 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
64 SparcIntRegOrder::i7);
67 // given the unified register number, this gives the name
68 // for generating assembly code or debugging.
70 const std::string UltraSparcRegInfo::getUnifiedRegName(int reg) const {
72 return SparcIntRegOrder::getRegName(reg);
73 else if ( reg < (64 + 32) )
74 return SparcFloatRegOrder::getRegName( reg - 32);
75 else if( reg < (64+32+4) )
76 return SparcFloatCCRegOrder::getRegName( reg -32 - 64);
77 else if( reg < (64+32+4+2) ) // two names: %xcc and %ccr
78 return SparcIntCCRegOrder::getRegName( reg -32 - 64 - 4);
79 else if (reg== InvalidRegNum) //****** TODO: Remove */
82 assert(0 && "Invalid register number");
86 // Get unified reg number for frame pointer
87 unsigned UltraSparcRegInfo::getFramePointer() const {
88 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
89 SparcIntRegOrder::i6);
92 // Get unified reg number for stack pointer
93 unsigned UltraSparcRegInfo::getStackPointer() const {
94 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
95 SparcIntRegOrder::o6);
99 //---------------------------------------------------------------------------
100 // Finds whether a call is an indirect call
101 //---------------------------------------------------------------------------
104 isVarArgsFunction(const Type *funcType) {
105 return cast<FunctionType>(cast<PointerType>(funcType)
106 ->getElementType())->isVarArg();
110 isVarArgsCall(const MachineInstr *CallMI) {
111 Value* callee = CallMI->getOperand(0).getVRegValue();
112 // const Type* funcType = isa<Function>(callee)? callee->getType()
113 // : cast<PointerType>(callee->getType())->getElementType();
114 const Type* funcType = callee->getType();
115 return isVarArgsFunction(funcType);
119 // Get the register number for the specified integer arg#,
120 // assuming there are argNum total args, intArgNum int args,
121 // and fpArgNum FP args preceding (and not including) this one.
122 // Use INT regs for FP args if this is a varargs call.
125 // InvalidRegNum, if there is no int register available for the arg.
126 // regNum, otherwise (this is NOT the unified reg. num).
129 UltraSparcRegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall,
131 unsigned intArgNo, unsigned fpArgNo,
132 unsigned& regClassId) const
134 regClassId = IntRegClassID;
135 if (argNo >= NumOfIntArgRegs)
136 return InvalidRegNum;
138 return argNo + (inCallee? SparcIntRegOrder::i0 : SparcIntRegOrder::o0);
141 // Get the register number for the specified FP arg#,
142 // assuming there are argNum total args, intArgNum int args,
143 // and fpArgNum FP args preceding (and not including) this one.
144 // Use INT regs for FP args if this is a varargs call.
147 // InvalidRegNum, if there is no int register available for the arg.
148 // regNum, otherwise (this is NOT the unified reg. num).
151 UltraSparcRegInfo::regNumForFPArg(unsigned regType,
152 bool inCallee, bool isVarArgsCall,
154 unsigned intArgNo, unsigned fpArgNo,
155 unsigned& regClassId) const
158 return regNumForIntArg(inCallee, isVarArgsCall, argNo, intArgNo, fpArgNo,
162 regClassId = FloatRegClassID;
163 if (regType == FPSingleRegType)
164 return (argNo*2+1 >= NumOfFloatArgRegs)?
165 InvalidRegNum : SparcFloatRegOrder::f0 + (argNo * 2 + 1);
166 else if (regType == FPDoubleRegType)
167 return (argNo*2 >= NumOfFloatArgRegs)?
168 InvalidRegNum : SparcFloatRegOrder::f0 + (argNo * 2);
170 assert(0 && "Illegal FP register type");
176 //---------------------------------------------------------------------------
177 // Finds the return address of a call sparc specific call instruction
178 //---------------------------------------------------------------------------
180 // The following 4 methods are used to find the RegType (SparcInternals.h)
181 // of a LiveRange, a Value, and for a given register unified reg number.
183 int UltraSparcRegInfo::getRegType(unsigned regClassID,
184 const Type* type) const {
185 switch (regClassID) {
186 case IntRegClassID: return IntRegType;
187 case FloatRegClassID: {
188 if (type == Type::FloatTy)
189 return FPSingleRegType;
190 else if (type == Type::DoubleTy)
191 return FPDoubleRegType;
192 assert(0 && "Unknown type in FloatRegClass");
194 case IntCCRegClassID: return IntCCRegType;
195 case FloatCCRegClassID: return FloatCCRegType;
196 default: assert( 0 && "Unknown reg class ID"); return 0;
200 int UltraSparcRegInfo::getRegType(const LiveRange *LR) const {
201 return getRegType(LR->getRegClass()->getID(), LR->getType());
204 int UltraSparcRegInfo::getRegType(const Value *Val) const {
205 return getRegType(getRegClassIDOfValue(Val), Val->getType());
208 int UltraSparcRegInfo::getRegType(int unifiedRegNum) const {
209 if (unifiedRegNum < 32)
211 else if (unifiedRegNum < (32 + 32))
212 return FPSingleRegType;
213 else if (unifiedRegNum < (64 + 32))
214 return FPDoubleRegType;
215 else if (unifiedRegNum < (64+32+4))
216 return FloatCCRegType;
217 else if (unifiedRegNum < (64+32+4+2))
220 assert(0 && "Invalid unified register number in getRegType");
225 // To find the register class used for a specified Type
227 unsigned UltraSparcRegInfo::getRegClassIDOfType(const Type *type,
228 bool isCCReg) const {
229 Type::PrimitiveID ty = type->getPrimitiveID();
232 // FIXME: Comparing types like this isn't very safe...
233 if ((ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
234 (ty == Type::FunctionTyID) || (ty == Type::PointerTyID) )
235 res = IntRegClassID; // sparc int reg (ty=0: void)
236 else if (ty <= Type::DoubleTyID)
237 res = FloatRegClassID; // sparc float reg class
239 //std::cerr << "TypeID: " << ty << "\n";
240 assert(0 && "Cannot resolve register class for type");
245 return res + 2; // corresponidng condition code regiser
250 // To find the register class to which a specified register belongs
252 unsigned UltraSparcRegInfo::getRegClassIDOfReg(int unifiedRegNum) const {
253 unsigned classId = 0;
254 (void) getClassRegNum(unifiedRegNum, classId);
258 unsigned UltraSparcRegInfo::getRegClassIDOfRegType(int regType) const {
260 case IntRegType: return IntRegClassID;
261 case FPSingleRegType:
262 case FPDoubleRegType: return FloatRegClassID;
263 case IntCCRegType: return IntCCRegClassID;
264 case FloatCCRegType: return FloatCCRegClassID;
266 assert(0 && "Invalid register type in getRegClassIDOfRegType");
271 //---------------------------------------------------------------------------
272 // Suggests a register for the ret address in the RET machine instruction.
273 // We always suggest %i7 by convention.
274 //---------------------------------------------------------------------------
275 void UltraSparcRegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
276 LiveRangeInfo& LRI) const {
278 assert(target.getInstrInfo().isReturn(RetMI->getOpCode()));
280 // return address is always mapped to i7 so set it immediately
281 RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID,
282 SparcIntRegOrder::i7));
284 // Possible Optimization:
285 // Instead of setting the color, we can suggest one. In that case,
286 // we have to test later whether it received the suggested color.
287 // In that case, a LR has to be created at the start of method.
288 // It has to be done as follows (remove the setRegVal above):
290 // MachineOperand & MO = RetMI->getOperand(0);
291 // const Value *RetAddrVal = MO.getVRegValue();
292 // assert( RetAddrVal && "LR for ret address must be created at start");
293 // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
294 // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
295 // SparcIntRegOrdr::i7) );
299 //---------------------------------------------------------------------------
300 // Suggests a register for the ret address in the JMPL/CALL machine instr.
301 // Sparc ABI dictates that %o7 be used for this purpose.
302 //---------------------------------------------------------------------------
303 void UltraSparcRegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
305 std::vector<RegClass *> RCList) const {
306 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
307 const Value *RetAddrVal = argDesc->getReturnAddrReg();
308 assert(RetAddrVal && "Return address value is required");
310 // create a new LR for the return address and color it
311 LiveRange * RetAddrLR = new LiveRange();
312 RetAddrLR->insert( RetAddrVal );
313 unsigned RegClassID = getRegClassIDOfValue( RetAddrVal );
314 RetAddrLR->setRegClass( RCList[RegClassID] );
315 RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o7));
316 LRI.addLRToMap( RetAddrVal, RetAddrLR);
323 //---------------------------------------------------------------------------
324 // This method will suggest colors to incoming args to a method.
325 // According to the Sparc ABI, the first 6 incoming args are in
326 // %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float).
327 // If the arg is passed on stack due to the lack of regs, NOTHING will be
328 // done - it will be colored (or spilled) as a normal live range.
329 //---------------------------------------------------------------------------
330 void UltraSparcRegInfo::suggestRegs4MethodArgs(const Function *Meth,
331 LiveRangeInfo& LRI) const
333 // check if this is a varArgs function. needed for choosing regs.
334 bool isVarArgs = isVarArgsFunction(Meth->getType());
336 // for each argument. count INT and FP arguments separately.
337 unsigned argNo=0, intArgNo=0, fpArgNo=0;
338 for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend();
339 I != E; ++I, ++argNo) {
341 LiveRange *LR = LRI.getLiveRangeForValue(I);
342 assert(LR && "No live range found for method arg");
344 unsigned regType = getRegType(LR);
345 unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg (unused)
347 int regNum = (regType == IntRegType)
348 ? regNumForIntArg(/*inCallee*/ true, isVarArgs,
349 argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
350 : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs,
351 argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
353 if(regNum != InvalidRegNum)
354 LR->setSuggestedColor(regNum);
359 //---------------------------------------------------------------------------
360 // This method is called after graph coloring to move incoming args to
361 // the correct hardware registers if they did not receive the correct
362 // (suggested) color through graph coloring.
363 //---------------------------------------------------------------------------
364 void UltraSparcRegInfo::colorMethodArgs(const Function *Meth,
366 AddedInstrns *FirstAI) const {
368 // check if this is a varArgs function. needed for choosing regs.
369 bool isVarArgs = isVarArgsFunction(Meth->getType());
373 // for each argument. count INT and FP arguments separately.
374 unsigned argNo=0, intArgNo=0, fpArgNo=0;
375 for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend();
376 I != E; ++I, ++argNo) {
378 LiveRange *LR = LRI.getLiveRangeForValue(I);
379 assert( LR && "No live range found for method arg");
381 unsigned regType = getRegType( LR );
382 unsigned RegClassID = (LR->getRegClass())->getID();
384 // Find whether this argument is coming in a register (if not, on stack)
385 // Also find the correct register the argument must use (UniArgReg)
387 bool isArgInReg = false;
388 unsigned UniArgReg = InvalidRegNum; // reg that LR MUST be colored with
389 unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg
391 int regNum = (regType == IntRegType)
392 ? regNumForIntArg(/*inCallee*/ true, isVarArgs,
393 argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
394 : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs,
395 argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
397 if(regNum != InvalidRegNum) {
399 UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum);
402 if( LR->hasColor() ) { // if this arg received a register
404 unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
406 // if LR received the correct color, nothing to do
408 if( UniLRReg == UniArgReg )
411 // We are here because the LR did not receive the suggested
412 // but LR received another register.
413 // Now we have to copy the %i reg (or stack pos of arg)
414 // to the register the LR was colored with.
416 // if the arg is coming in UniArgReg register, it MUST go into
417 // the UniLRReg register
420 if( regClassIDOfArgReg != RegClassID ) {
421 assert(0 && "This could should work but it is not tested yet");
423 // It is a variable argument call: the float reg must go in a %o reg.
424 // We have to move an int reg to a float reg via memory.
427 RegClassID == FloatRegClassID &&
428 regClassIDOfArgReg == IntRegClassID &&
429 "This should only be an Int register for an FP argument");
431 int TmpOff = MachineCodeForMethod::get(Meth).pushTempValue(target,
432 getSpilledRegSize(regType));
433 cpReg2MemMI(FirstAI->InstrnsBefore,
434 UniArgReg, getFramePointer(), TmpOff, IntRegType);
436 cpMem2RegMI(FirstAI->InstrnsBefore,
437 getFramePointer(), TmpOff, UniLRReg, regType);
440 cpReg2RegMI(FirstAI->InstrnsBefore, UniArgReg, UniLRReg, regType);
445 // Now the arg is coming on stack. Since the LR recieved a register,
446 // we just have to load the arg on stack into that register
448 const MachineFrameInfo& frameInfo = target.getFrameInfo();
450 frameInfo.getIncomingArgOffset(MachineCodeForMethod::get(Meth),
453 cpMem2RegMI(FirstAI->InstrnsBefore,
454 getFramePointer(), offsetFromFP, UniLRReg, regType);
457 } // if LR received a color
461 // Now, the LR did not receive a color. But it has a stack offset for
463 // So, if the arg is coming in UniArgReg register, we can just move
464 // that on to the stack pos of LR
468 if( regClassIDOfArgReg != RegClassID ) {
470 "FP arguments to a varargs function should be explicitly "
471 "copied to/from int registers by instruction selection!");
473 // It must be a float arg for a variable argument call, which
474 // must come in a %o reg. Move the int reg to the stack.
476 assert(isVarArgs && regClassIDOfArgReg == IntRegClassID &&
477 "This should only be an Int register for an FP argument");
479 cpReg2MemMI(FirstAI->InstrnsBefore, UniArgReg,
480 getFramePointer(), LR->getSpillOffFromFP(), IntRegType);
483 cpReg2MemMI(FirstAI->InstrnsBefore, UniArgReg,
484 getFramePointer(), LR->getSpillOffFromFP(), regType);
490 // Now the arg is coming on stack. Since the LR did NOT
491 // recieved a register as well, it is allocated a stack position. We
492 // can simply change the stack position of the LR. We can do this,
493 // since this method is called before any other method that makes
494 // uses of the stack pos of the LR (e.g., updateMachineInstr)
496 const MachineFrameInfo& frameInfo = target.getFrameInfo();
498 frameInfo.getIncomingArgOffset(MachineCodeForMethod::get(Meth),
501 LR->modifySpillOffFromFP( offsetFromFP );
506 } // for each incoming argument
512 //---------------------------------------------------------------------------
513 // This method is called before graph coloring to suggest colors to the
514 // outgoing call args and the return value of the call.
515 //---------------------------------------------------------------------------
516 void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
518 std::vector<RegClass *> RCList) const {
519 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
521 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
523 suggestReg4CallAddr(CallMI, LRI, RCList);
525 // First color the return value of the call instruction. The return value
526 // will be in %o0 if the value is an integer type, or in %f0 if the
527 // value is a float type.
529 // the return value cannot have a LR in machine instruction since it is
530 // only defined by the call instruction
532 // if type is not void, create a new live range and set its
533 // register class and add to LRI
535 const Value *RetVal = argDesc->getReturnValue();
538 assert ((!LRI.getLiveRangeForValue(RetVal)) &&
539 "LR for ret Value of call already definded!");
541 // create a new LR for the return value
542 LiveRange *RetValLR = new LiveRange();
543 RetValLR->insert(RetVal);
544 unsigned RegClassID = getRegClassIDOfValue(RetVal);
545 RetValLR->setRegClass(RCList[RegClassID]);
546 LRI.addLRToMap(RetVal, RetValLR);
548 // now suggest a register depending on the register class of ret arg
550 if( RegClassID == IntRegClassID )
551 RetValLR->setSuggestedColor(SparcIntRegOrder::o0);
552 else if (RegClassID == FloatRegClassID )
553 RetValLR->setSuggestedColor(SparcFloatRegOrder::f0 );
554 else assert( 0 && "Unknown reg class for return value of call\n");
558 // Now suggest colors for arguments (operands) of the call instruction.
559 // Colors are suggested only if the arg number is smaller than the
560 // the number of registers allocated for argument passing.
561 // Now, go thru call args - implicit operands of the call MI
563 unsigned NumOfCallArgs = argDesc->getNumArgs();
565 for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0;
566 i < NumOfCallArgs; ++i, ++argNo) {
568 const Value *CallArg = argDesc->getArgInfo(i).getArgVal();
570 // get the LR of call operand (parameter)
571 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
573 // not possible to have a null LR since all args (even consts)
574 // must be defined before
576 cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) << "\n";
577 assert(0 && "NO LR for call arg");
580 unsigned regType = getRegType( LR );
581 unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg (unused)
583 // Choose a register for this arg depending on whether it is
584 // an INT or FP value. Here we ignore whether or not it is a
585 // varargs calls, because FP arguments will be explicitly copied
586 // to an integer Value and handled under (argCopy != NULL) below.
587 int regNum = (regType == IntRegType)
588 ? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false,
589 argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
590 : regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false,
591 argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
593 // If a register could be allocated, use it.
594 // If not, do NOTHING as this will be colored as a normal value.
595 if(regNum != InvalidRegNum)
596 LR->setSuggestedColor(regNum);
598 // Repeat for the second copy of the argument, which would be
599 // an FP argument being passed to a function with no prototype
600 const Value *argCopy = argDesc->getArgInfo(i).getArgCopy();
603 assert(regType != IntRegType && argCopy->getType()->isIntegral()
604 && "Must be passing copy of FP argument in int register");
605 int copyRegNum = regNumForIntArg(/*inCallee*/false, /*isVarArgs*/false,
606 argNo, intArgNo, fpArgNo-1,
608 assert(copyRegNum != InvalidRegNum);
609 LiveRange *const copyLR = LRI.getLiveRangeForValue(argCopy);
610 copyLR->setSuggestedColor(copyRegNum);
613 } // for all call arguments
618 //---------------------------------------------------------------------------
619 // Helper method for UltraSparcRegInfo::colorCallArgs().
620 //---------------------------------------------------------------------------
623 UltraSparcRegInfo::InitializeOutgoingArg(MachineInstr* CallMI,
624 AddedInstrns *CallAI,
625 PhyRegAlloc &PRA, LiveRange* LR,
626 unsigned regType, unsigned RegClassID,
627 int UniArgRegOrNone, unsigned int argNo,
628 std::vector<MachineInstr *>& AddedInstrnsBefore)
632 bool isArgInReg = false;
633 unsigned UniArgReg = MAXINT; // unused unless initialized below
634 if (UniArgRegOrNone != InvalidRegNum)
637 UniArgReg = (unsigned) UniArgRegOrNone;
638 CallMI->getRegsUsed().insert(UniArgReg); // mark the reg as used
641 if (LR->hasColor()) {
642 unsigned UniLRReg = getUnifiedRegNum(RegClassID, LR->getColor());
644 // if LR received the correct color, nothing to do
645 if( isArgInReg && UniArgReg == UniLRReg )
648 // The LR is allocated to a register UniLRReg and must be copied
649 // to UniArgReg or to the stack slot.
652 // Copy UniLRReg to UniArgReg
653 cpReg2RegMI(AddedInstrnsBefore, UniLRReg, UniArgReg, regType);
656 // Copy UniLRReg to the stack to pass the arg on stack.
657 const MachineFrameInfo& frameInfo = target.getFrameInfo();
658 int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo);
659 cpReg2MemMI(CallAI->InstrnsBefore,
660 UniLRReg, getStackPointer(), argOffset, regType);
663 } else { // LR is not colored (i.e., spilled)
666 // Insert a load instruction to load the LR to UniArgReg
667 cpMem2RegMI(AddedInstrnsBefore, getFramePointer(),
668 LR->getSpillOffFromFP(), UniArgReg, regType);
669 // Now add the instruction
673 // Now, we have to pass the arg on stack. Since LR also did NOT
674 // receive a register we have to move an argument in memory to
675 // outgoing parameter on stack.
676 // Use TReg to load and store the value.
677 // Use TmpOff to save TReg, since that may have a live value.
679 int TReg = PRA.getUniRegNotUsedByThisInst( LR->getRegClass(), CallMI );
680 int TmpOff = PRA.mcInfo.pushTempValue(target,
681 getSpilledRegSize(getRegType(LR)));
682 const MachineFrameInfo& frameInfo = target.getFrameInfo();
683 int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo);
685 MachineInstr *Ad1, *Ad2, *Ad3, *Ad4;
688 // (1) Save TReg on stack
689 // (2) Load LR value into TReg from stack pos of LR
690 // (3) Store Treg on outgoing Arg pos on stack
691 // (4) Load the old value of TReg from stack to TReg (restore it)
694 // When reverse pointers in MahineInstr are introduced:
695 // Call PRA.getUnusedRegAtMI(....) to get an unused reg. Step 1 is
696 // needed only if this fails. Currently, we cannot call the
697 // above method since we cannot find LVSetBefore without the BB
699 // NOTE: We directly add to CallAI->InstrnsBefore instead of adding to
700 // AddedInstrnsBefore since these instructions must not be reordered.
701 cpReg2MemMI(CallAI->InstrnsBefore,
702 TReg, getFramePointer(), TmpOff, regType);
703 cpMem2RegMI(CallAI->InstrnsBefore,
704 getFramePointer(), LR->getSpillOffFromFP(), TReg, regType);
705 cpReg2MemMI(CallAI->InstrnsBefore,
706 TReg, getStackPointer(), argOffset, regType);
707 cpMem2RegMI(CallAI->InstrnsBefore,
708 getFramePointer(), TmpOff, TReg, regType);
713 //---------------------------------------------------------------------------
714 // After graph coloring, we have call this method to see whehter the return
715 // value and the call args received the correct colors. If not, we have
716 // to instert copy instructions.
717 //---------------------------------------------------------------------------
719 void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI,
721 AddedInstrns *CallAI,
723 const BasicBlock *BB) const {
725 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
727 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
729 // First color the return value of the call.
730 // If there is a LR for the return value, it means this
731 // method returns a value
735 const Value *RetVal = argDesc->getReturnValue();
738 LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal );
741 cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
742 assert(RetValLR && "ERR:No LR for non-void return value");
745 unsigned RegClassID = (RetValLR->getRegClass())->getID();
746 bool recvCorrectColor;
747 unsigned CorrectCol; // correct color for ret value
748 unsigned UniRetReg; // unified number for CorrectCol
750 if(RegClassID == IntRegClassID)
751 CorrectCol = SparcIntRegOrder::o0;
752 else if(RegClassID == FloatRegClassID)
753 CorrectCol = SparcFloatRegOrder::f0;
755 assert( 0 && "Unknown RegClass");
759 // convert to unified number
760 UniRetReg = this->getUnifiedRegNum( RegClassID, CorrectCol);
762 // Mark the register as used by this instruction
763 CallMI->getRegsUsed().insert(UniRetReg);
765 // if the LR received the correct color, NOTHING to do
766 recvCorrectColor = RetValLR->hasColor()? RetValLR->getColor() == CorrectCol
769 // if we didn't receive the correct color for some reason,
770 // put copy instruction
771 if( !recvCorrectColor ) {
773 unsigned regType = getRegType( RetValLR );
775 if( RetValLR->hasColor() ) {
777 unsigned UniRetLRReg=getUnifiedRegNum(RegClassID,RetValLR->getColor());
779 // the return value is coming in UniRetReg but has to go into
782 cpReg2RegMI(CallAI->InstrnsAfter, UniRetReg, UniRetLRReg, regType);
787 // if the LR did NOT receive a color, we have to move the return
788 // value coming in UniRetReg to the stack pos of spilled LR
790 cpReg2MemMI(CallAI->InstrnsAfter, UniRetReg,
791 getFramePointer(),RetValLR->getSpillOffFromFP(), regType);
794 } // the LR didn't receive the suggested color
796 } // if there a return value
799 //-------------------------------------------
800 // Now color all args of the call instruction
801 //-------------------------------------------
803 std::vector<MachineInstr *> AddedInstrnsBefore;
805 unsigned NumOfCallArgs = argDesc->getNumArgs();
807 for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0;
808 i < NumOfCallArgs; ++i, ++argNo) {
810 const Value *CallArg = argDesc->getArgInfo(i).getArgVal();
812 // get the LR of call operand (parameter)
813 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
815 unsigned RegClassID = getRegClassIDOfValue( CallArg);
816 unsigned regType = getRegType( RegClassID, CallArg->getType() );
818 // Find whether this argument is coming in a register (if not, on stack)
819 // Also find the correct register the argument must use (UniArgReg)
821 bool isArgInReg = false;
822 unsigned UniArgReg = InvalidRegNum; // reg that LR MUST be colored with
823 unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg
825 // Find the register that must be used for this arg, depending on
826 // whether it is an INT or FP value. Here we ignore whether or not it
827 // is a varargs calls, because FP arguments will be explicitly copied
828 // to an integer Value and handled under (argCopy != NULL) below.
829 int regNum = (regType == IntRegType)
830 ? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false,
831 argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
832 : regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false,
833 argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
835 if(regNum != InvalidRegNum) {
837 UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum);
838 assert(regClassIDOfArgReg == RegClassID &&
839 "Moving values between reg classes must happen during selection");
842 // not possible to have a null LR since all args (even consts)
843 // must be defined before
845 cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) <<"\n";
846 assert(LR && "NO LR for call arg");
849 InitializeOutgoingArg(CallMI, CallAI, PRA, LR, regType, RegClassID,
850 UniArgReg, argNo, AddedInstrnsBefore);
852 // Repeat for the second copy of the argument, which would be
853 // an FP argument being passed to a function with no prototype.
854 // It may either be passed as a copy in an integer register
855 // (in argCopy), or on the stack (useStackSlot).
856 const Value *argCopy = argDesc->getArgInfo(i).getArgCopy();
859 assert(regType != IntRegType && argCopy->getType()->isIntegral()
860 && "Must be passing copy of FP argument in int register");
862 unsigned copyRegClassID = getRegClassIDOfValue(argCopy);
863 unsigned copyRegType = getRegType(copyRegClassID, argCopy->getType());
865 int copyRegNum = regNumForIntArg(/*inCallee*/false, /*isVarArgs*/false,
866 argNo, intArgNo, fpArgNo-1,
868 assert(copyRegNum != InvalidRegNum);
869 assert(regClassIDOfArgReg == copyRegClassID &&
870 "Moving values between reg classes must happen during selection");
872 InitializeOutgoingArg(CallMI, CallAI, PRA,
873 LRI.getLiveRangeForValue(argCopy), copyRegType,
874 copyRegClassID, copyRegNum, argNo,
878 if (regNum != InvalidRegNum &&
879 argDesc->getArgInfo(i).usesStackSlot())
881 // Pass the argument via the stack in addition to regNum
882 assert(regType != IntRegType && "Passing an integer arg. twice?");
883 assert(!argCopy && "Passing FP arg in FP reg, INT reg, and stack?");
884 InitializeOutgoingArg(CallMI, CallAI, PRA, LR, regType, RegClassID,
885 InvalidRegNum, argNo, AddedInstrnsBefore);
887 } // for each parameter in call instruction
889 // If we added any instruction before the call instruction, verify
890 // that they are in the proper order and if not, reorder them
892 std::vector<MachineInstr *> ReorderedVec;
893 if (!AddedInstrnsBefore.empty()) {
896 cerr << "\nCalling reorder with instrns: \n";
897 for(unsigned i=0; i < AddedInstrnsBefore.size(); i++)
898 cerr << *(AddedInstrnsBefore[i]);
901 OrderAddedInstrns(AddedInstrnsBefore, ReorderedVec, PRA);
902 assert(ReorderedVec.size() >= AddedInstrnsBefore.size()
903 && "Dropped some instructions when reordering!");
906 cerr << "\nAfter reordering instrns: \n";
907 for(unsigned i = 0; i < ReorderedVec.size(); i++)
908 cerr << *ReorderedVec[i];
912 // Now insert caller saving code for this call instruction
914 insertCallerSavingCode(CallAI->InstrnsBefore, CallAI->InstrnsAfter,
917 // Then insert the final reordered code for the call arguments.
919 for(unsigned i=0; i < ReorderedVec.size(); i++)
920 CallAI->InstrnsBefore.push_back( ReorderedVec[i] );
923 //---------------------------------------------------------------------------
924 // This method is called for an LLVM return instruction to identify which
925 // values will be returned from this method and to suggest colors.
926 //---------------------------------------------------------------------------
927 void UltraSparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI,
928 LiveRangeInfo &LRI) const {
930 assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) );
932 suggestReg4RetAddr(RetMI, LRI);
934 // if there is an implicit ref, that has to be the ret value
935 if( RetMI->getNumImplicitRefs() > 0 ) {
937 // The first implicit operand is the return value of a return instr
938 const Value *RetVal = RetMI->getImplicitRef(0);
940 LiveRange *const LR = LRI.getLiveRangeForValue( RetVal );
943 cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
944 assert(0 && "No LR for return value of non-void method");
947 unsigned RegClassID = (LR->getRegClass())->getID();
949 if (RegClassID == IntRegClassID)
950 LR->setSuggestedColor(SparcIntRegOrder::i0);
951 else if (RegClassID == FloatRegClassID)
952 LR->setSuggestedColor(SparcFloatRegOrder::f0);
958 //---------------------------------------------------------------------------
959 // Colors the return value of a method to %i0 or %f0, if possible. If it is
960 // not possilbe to directly color the LR, insert a copy instruction to move
961 // the LR to %i0 or %f0. When the LR is spilled, instead of the copy, we
962 // have to put a load instruction.
963 //---------------------------------------------------------------------------
964 void UltraSparcRegInfo::colorRetValue(MachineInstr *RetMI,
966 AddedInstrns *RetAI) const {
968 assert((UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode()));
970 // if there is an implicit ref, that has to be the ret value
971 if(RetMI->getNumImplicitRefs() > 0) {
973 // The first implicit operand is the return value of a return instr
974 const Value *RetVal = RetMI->getImplicitRef(0);
976 LiveRange *LR = LRI.getLiveRangeForValue(RetVal);
979 cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
980 // assert( LR && "No LR for return value of non-void method");
984 unsigned RegClassID = getRegClassIDOfValue(RetVal);
985 unsigned regType = getRegType( RetVal );
988 if(RegClassID == IntRegClassID)
989 CorrectCol = SparcIntRegOrder::i0;
990 else if(RegClassID == FloatRegClassID)
991 CorrectCol = SparcFloatRegOrder::f0;
993 assert (0 && "Unknown RegClass");
997 // convert to unified number
998 unsigned UniRetReg = this->getUnifiedRegNum(RegClassID, CorrectCol);
1000 // Mark the register as used by this instruction
1001 RetMI->getRegsUsed().insert(UniRetReg);
1003 // if the LR received the correct color, NOTHING to do
1005 if (LR->hasColor() && LR->getColor() == CorrectCol)
1008 if (LR->hasColor()) {
1010 // We are here because the LR was allocted a regiter
1011 // It may be the suggested register or not
1013 // copy the LR of retun value to i0 or f0
1015 unsigned UniLRReg =getUnifiedRegNum( RegClassID, LR->getColor());
1017 // the LR received UniLRReg but must be colored with UniRetReg
1018 // to pass as the return value
1019 cpReg2RegMI(RetAI->InstrnsBefore, UniLRReg, UniRetReg, regType);
1021 else { // if the LR is spilled
1022 cpMem2RegMI(RetAI->InstrnsBefore, getFramePointer(),
1023 LR->getSpillOffFromFP(), UniRetReg, regType);
1024 cerr << "\nCopied the return value from stack\n";
1027 } // if there is a return value
1031 //---------------------------------------------------------------------------
1032 // Check if a specified register type needs a scratch register to be
1033 // copied to/from memory. If it does, the reg. type that must be used
1034 // for scratch registers is returned in scratchRegType.
1036 // Only the int CC register needs such a scratch register.
1037 // The FP CC registers can (and must) be copied directly to/from memory.
1038 //---------------------------------------------------------------------------
1041 UltraSparcRegInfo::regTypeNeedsScratchReg(int RegType,
1042 int& scratchRegType) const
1044 if (RegType == IntCCRegType)
1046 scratchRegType = IntRegType;
1052 //---------------------------------------------------------------------------
1053 // Copy from a register to register. Register number must be the unified
1055 //---------------------------------------------------------------------------
1058 UltraSparcRegInfo::cpReg2RegMI(vector<MachineInstr*>& mvec,
1061 int RegType) const {
1062 assert( ((int)SrcReg != InvalidRegNum) && ((int)DestReg != InvalidRegNum) &&
1063 "Invalid Register");
1065 MachineInstr * MI = NULL;
1070 if (this->getRegType(DestReg) == IntRegType)
1071 { // copy intCC reg to int reg
1072 // Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR
1073 MI = Create2OperandInstr_Reg(RDCCR, SrcReg+1, DestReg);
1076 { // copy int reg to intCC reg
1077 // Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
1078 assert(this->getRegType(SrcReg) == IntRegType
1079 && "Can only copy CC reg to/from integer reg");
1080 MI = Create2OperandInstr_Reg(WRCCR, SrcReg, DestReg+1);
1084 case FloatCCRegType:
1085 assert(0 && "Cannot copy FPCC register to any other register");
1089 MI = Create3OperandInstr_Reg(ADD, SrcReg, this->getZeroRegNum(), DestReg);
1092 case FPSingleRegType:
1093 MI = Create2OperandInstr_Reg(FMOVS, SrcReg, DestReg);
1096 case FPDoubleRegType:
1097 MI = Create2OperandInstr_Reg(FMOVD, SrcReg, DestReg);
1101 assert(0 && "Unknown RegType");
1109 //---------------------------------------------------------------------------
1110 // Copy from a register to memory (i.e., Store). Register number must
1111 // be the unified register number
1112 //---------------------------------------------------------------------------
1116 UltraSparcRegInfo::cpReg2MemMI(vector<MachineInstr*>& mvec,
1118 unsigned DestPtrReg,
1119 int Offset, int RegType,
1120 int scratchReg) const {
1121 MachineInstr * MI = NULL;
1124 MI = new MachineInstr(STX, 3);
1125 MI->SetMachineOperandReg(0, SrcReg, false);
1126 MI->SetMachineOperandReg(1, DestPtrReg, false);
1127 MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
1132 case FPSingleRegType:
1133 MI = new MachineInstr(ST, 3);
1134 MI->SetMachineOperandReg(0, SrcReg, false);
1135 MI->SetMachineOperandReg(1, DestPtrReg, false);
1136 MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
1141 case FPDoubleRegType:
1142 MI = new MachineInstr(STD, 3);
1143 MI->SetMachineOperandReg(0, SrcReg, false);
1144 MI->SetMachineOperandReg(1, DestPtrReg, false);
1145 MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
1151 assert(scratchReg >= 0 && "Need scratch reg to store %ccr to memory");
1152 assert(this->getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
1154 // Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR
1155 MI = Create2OperandInstr_Reg(RDCCR, SrcReg+1, scratchReg);
1158 this->cpReg2MemMI(mvec, scratchReg, DestPtrReg, Offset, IntRegType);
1161 case FloatCCRegType:
1162 assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here");
1163 MI = new MachineInstr(STXFSR, 3);
1164 MI->SetMachineOperandReg(0, SrcReg, false);
1165 MI->SetMachineOperandReg(1, DestPtrReg, false);
1166 MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
1172 assert(0 && "Unknown RegType in cpReg2MemMI");
1177 //---------------------------------------------------------------------------
1178 // Copy from memory to a reg (i.e., Load) Register number must be the unified
1180 //---------------------------------------------------------------------------
1184 UltraSparcRegInfo::cpMem2RegMI(vector<MachineInstr*>& mvec,
1189 int scratchReg) const {
1190 MachineInstr * MI = NULL;
1193 MI = new MachineInstr(LDX, 3);
1194 MI->SetMachineOperandReg(0, SrcPtrReg, false);
1195 MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
1197 MI->SetMachineOperandReg(2, DestReg, true);
1201 case FPSingleRegType:
1202 MI = new MachineInstr(LD, 3);
1203 MI->SetMachineOperandReg(0, SrcPtrReg, false);
1204 MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
1206 MI->SetMachineOperandReg(2, DestReg, true);
1210 case FPDoubleRegType:
1211 MI = new MachineInstr(LDD, 3);
1212 MI->SetMachineOperandReg(0, SrcPtrReg, false);
1213 MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
1215 MI->SetMachineOperandReg(2, DestReg, true);
1220 assert(scratchReg >= 0 && "Need scratch reg to load %ccr from memory");
1221 assert(this->getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
1222 this->cpMem2RegMI(mvec, SrcPtrReg, Offset, scratchReg, IntRegType);
1224 // Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
1225 MI = Create2OperandInstr_Reg(WRCCR, scratchReg, DestReg+1);
1230 case FloatCCRegType:
1231 assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here");
1232 MI = new MachineInstr(LDXFSR, 3);
1233 MI->SetMachineOperandReg(0, SrcPtrReg, false);
1234 MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
1236 MI->SetMachineOperandReg(2, DestReg, true);
1241 assert(0 && "Unknown RegType in cpMem2RegMI");
1246 //---------------------------------------------------------------------------
1247 // Generate a copy instruction to copy a value to another. Temporarily
1248 // used by PhiElimination code.
1249 //---------------------------------------------------------------------------
1253 UltraSparcRegInfo::cpValue2Value(Value *Src,
1255 vector<MachineInstr*>& mvec) const {
1256 int RegType = getRegType( Src );
1258 assert( (RegType==getRegType(Src)) && "Src & Dest are diff types");
1260 MachineInstr * MI = NULL;
1264 MI = new MachineInstr(ADD, 3);
1265 MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
1266 MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
1267 MI->SetMachineOperandVal(2, MachineOperand:: MO_VirtualRegister, Dest, true);
1270 case FPSingleRegType:
1271 MI = new MachineInstr(FMOVS, 2);
1272 MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
1273 MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true);
1277 case FPDoubleRegType:
1278 MI = new MachineInstr(FMOVD, 2);
1279 MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
1280 MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true);
1284 assert(0 && "Unknow RegType in CpValu2Value");
1296 //----------------------------------------------------------------------------
1297 // This method inserts caller saving/restoring instructons before/after
1298 // a call machine instruction. The caller saving/restoring instructions are
1301 // ** caller saving instructions
1302 // other instructions inserted for the call by ColorCallArg
1304 // other instructions inserted for the call ColorCallArg
1305 // ** caller restoring instructions
1307 //----------------------------------------------------------------------------
1311 UltraSparcRegInfo::insertCallerSavingCode(vector<MachineInstr*>& instrnsBefore,
1312 vector<MachineInstr*>& instrnsAfter,
1313 MachineInstr *CallMI,
1314 const BasicBlock *BB,
1315 PhyRegAlloc &PRA) const
1317 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
1319 // has set to record which registers were saved/restored
1321 hash_set<unsigned> PushedRegSet;
1323 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
1325 // Now find the LR of the return value of the call
1326 // The last *implicit operand* is the return value of a call
1327 // Insert it to to he PushedRegSet since we must not save that register
1328 // and restore it after the call.
1329 // We do this because, we look at the LV set *after* the instruction
1330 // to determine, which LRs must be saved across calls. The return value
1331 // of the call is live in this set - but we must not save/restore it.
1333 const Value *RetVal = argDesc->getReturnValue();
1336 LiveRange *RetValLR = PRA.LRI.getLiveRangeForValue( RetVal );
1337 assert(RetValLR && "No LR for RetValue of call");
1339 if (RetValLR->hasColor())
1340 PushedRegSet.insert(
1341 getUnifiedRegNum((RetValLR->getRegClass())->getID(),
1342 RetValLR->getColor() ) );
1345 const ValueSet &LVSetAft = PRA.LVI->getLiveVarSetAfterMInst(CallMI, BB);
1346 ValueSet::const_iterator LIt = LVSetAft.begin();
1348 // for each live var in live variable set after machine inst
1349 for( ; LIt != LVSetAft.end(); ++LIt) {
1351 // get the live range corresponding to live var
1352 LiveRange *const LR = PRA.LRI.getLiveRangeForValue(*LIt );
1354 // LR can be null if it is a const since a const
1355 // doesn't have a dominating def - see Assumptions above
1358 if( LR->hasColor() ) {
1360 unsigned RCID = (LR->getRegClass())->getID();
1361 unsigned Color = LR->getColor();
1363 if ( isRegVolatile(RCID, Color) ) {
1365 // if the value is in both LV sets (i.e., live before and after
1366 // the call machine instruction)
1368 unsigned Reg = getUnifiedRegNum(RCID, Color);
1370 if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
1372 // if we haven't already pushed that register
1374 unsigned RegType = getRegType( LR );
1376 // Now get two instructions - to push on stack and pop from stack
1377 // and add them to InstrnsBefore and InstrnsAfter of the
1380 int StackOff = PRA.mcInfo.pushTempValue(target,
1381 getSpilledRegSize(RegType));
1383 vector<MachineInstr*> AdIBef, AdIAft;
1385 //---- Insert code for pushing the reg on stack ----------
1387 // We may need a scratch register to copy the saved value
1388 // to/from memory. This may itself have to insert code to
1389 // free up a scratch register. Any such code should go before
1391 int scratchRegType = -1;
1392 int scratchReg = -1;
1393 if (this->regTypeNeedsScratchReg(RegType, scratchRegType))
1394 { // Find a register not live in the LVSet before CallMI
1395 const ValueSet &LVSetBef =
1396 PRA.LVI->getLiveVarSetBeforeMInst(CallMI, BB);
1397 scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetBef,
1398 CallMI, AdIBef, AdIAft);
1399 assert(scratchReg != this->getInvalidRegNum());
1400 CallMI->getRegsUsed().insert(scratchReg);
1403 if (AdIBef.size() > 0)
1404 instrnsBefore.insert(instrnsBefore.end(),
1405 AdIBef.begin(), AdIBef.end());
1407 cpReg2MemMI(instrnsBefore, Reg,getFramePointer(),StackOff,RegType,
1410 if (AdIAft.size() > 0)
1411 instrnsBefore.insert(instrnsBefore.end(),
1412 AdIAft.begin(), AdIAft.end());
1414 //---- Insert code for popping the reg from the stack ----------
1416 // We may need a scratch register to copy the saved value
1417 // from memory. This may itself have to insert code to
1418 // free up a scratch register. Any such code should go
1419 // after the save code.
1421 scratchRegType = -1;
1423 if (this->regTypeNeedsScratchReg(RegType, scratchRegType))
1424 { // Find a register not live in the LVSet after CallMI
1425 scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetAft,
1426 CallMI, AdIBef, AdIAft);
1427 assert(scratchReg != this->getInvalidRegNum());
1428 CallMI->getRegsUsed().insert(scratchReg);
1431 if (AdIBef.size() > 0)
1432 instrnsAfter.insert(instrnsAfter.end(),
1433 AdIBef.begin(), AdIBef.end());
1435 cpMem2RegMI(instrnsAfter, getFramePointer(), StackOff,Reg,RegType,
1438 if (AdIAft.size() > 0)
1439 instrnsAfter.insert(instrnsAfter.end(),
1440 AdIAft.begin(), AdIAft.end());
1442 PushedRegSet.insert(Reg);
1445 cerr << "\nFor call inst:" << *CallMI;
1446 cerr << " -inserted caller saving instrs: Before:\n\t ";
1447 for_each(instrnsBefore.begin(), instrnsBefore.end(),
1448 std::mem_fun(&MachineInstr::dump));
1449 cerr << " -and After:\n\t ";
1450 for_each(instrnsAfter.begin(), instrnsAfter.end(),
1451 std::mem_fun(&MachineInstr::dump));
1453 } // if not already pushed
1455 } // if LR has a volatile color
1457 } // if LR has color
1459 } // if there is a LR for Var
1461 } // for each value in the LV set after instruction
1465 //---------------------------------------------------------------------------
1466 // Print the register assigned to a LR
1467 //---------------------------------------------------------------------------
1469 void UltraSparcRegInfo::printReg(const LiveRange *LR) {
1470 unsigned RegClassID = (LR->getRegClass())->getID();
1471 cerr << " *Node " << (LR->getUserIGNode())->getIndex();
1473 if (!LR->hasColor()) {
1474 cerr << " - could not find a color\n";
1478 // if a color is found
1480 cerr << " colored with color "<< LR->getColor();
1482 if (RegClassID == IntRegClassID) {
1483 cerr<< " [" << SparcIntRegOrder::getRegName(LR->getColor()) << "]\n";
1485 } else if (RegClassID == FloatRegClassID) {
1486 cerr << "[" << SparcFloatRegOrder::getRegName(LR->getColor());
1487 if( LR->getType() == Type::DoubleTy)
1488 cerr << "+" << SparcFloatRegOrder::getRegName(LR->getColor()+1);
1493 //---------------------------------------------------------------------------
1494 // This method examines instructions inserted by RegAlloc code before a
1495 // machine instruction to detect invalid orders that destroy values before
1496 // they are used. If it detects such conditions, it reorders the instructions.
1498 // The unordered instructions come in the UnordVec. These instructions are
1499 // instructions inserted by RegAlloc. All such instruction MUST have
1500 // their USES BEFORE THE DEFS after reordering.
1502 // The UnordVec & OrdVec must be DISTINCT. The OrdVec must be empty when
1503 // this method is called.
1505 // This method uses two vectors for efficiency in accessing
1507 // Since instructions are inserted in RegAlloc, this assumes that the
1508 // first operand is the source reg and the last operand is the dest reg.
1509 // It also does not consider operands that are both use and def.
1511 // All the uses are before THE def to a register
1512 //---------------------------------------------------------------------------
1514 void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr*> &UnordVec,
1515 std::vector<MachineInstr*> &OrdVec,
1516 PhyRegAlloc &PRA) const{
1519 Problem: We can have instructions inserted by RegAlloc like
1521 2. add %oy %g0 %oz, where z!=x or z==x
1523 This is wrong since %oy used by 2 is overwritten by 1
1526 We re-order the instructions so that the uses are before the defs
1531 for each instruction 'DefInst' in the UnOrdVec
1532 for each instruction 'UseInst' that follows the DefInst
1533 if the reg defined by DefInst is used by UseInst
1534 mark DefInst as not movable in this iteration
1535 If DefInst is not marked as not-movable, move DefInst to OrdVec
1536 while all instructions in DefInst are moved to OrdVec
1538 For moving, we call the move2OrdVec(). It checks whether there is a def
1539 in it for the uses in the instruction to be added to OrdVec. If there
1540 are no preceding defs, it just appends the instruction. If there is a
1541 preceding def, it puts two instructions to save the reg on stack before
1542 the load and puts a restore at use.
1547 bool DebugPrint = false;
1550 CouldMoveAll = true;
1551 std::vector<MachineInstr *>::iterator DefIt = UnordVec.begin();
1553 for( ; DefIt != UnordVec.end(); ++DefIt ) {
1555 // for each instruction in the UnordVec do ...
1557 MachineInstr *DefInst = *DefIt;
1559 if( DefInst == NULL) continue;
1561 //cerr << "\nInst in UnordVec = " << *DefInst;
1563 // last operand is the def (unless for a store which has no def reg)
1564 MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
1566 if( DefOp.opIsDef() &&
1567 DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1569 // If the operand in DefInst is a def ...
1571 bool DefEqUse = false;
1573 std::vector<MachineInstr *>::iterator UseIt = DefIt;
1576 for( ; UseIt != UnordVec.end(); ++UseIt ) {
1578 MachineInstr *UseInst = *UseIt;
1579 if( UseInst == NULL) continue;
1581 // for each inst (UseInst) that is below the DefInst do ...
1582 MachineOperand& UseOp = UseInst->getOperand(0);
1584 if( ! UseOp.opIsDef() &&
1585 UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1587 // if use is a register ...
1589 if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
1591 // if Def and this use are the same, it means that this use
1592 // is destroyed by a def before it is used
1594 // cerr << "\nCouldn't move " << *DefInst;
1597 CouldMoveAll = false;
1600 } // if two registers are equal
1602 } // if use is a register
1604 }// for all use instructions
1608 // after examining all the instructions that follow the DefInst
1609 // if there are no dependencies, we can move it to the OrdVec
1611 // cerr << "Moved to Ord: " << *DefInst;
1613 moveInst2OrdVec(OrdVec, DefInst, PRA);
1615 //OrdVec.push_back(DefInst);
1617 // mark the pos of DefInst with NULL to indicate that it is
1622 } // if Def is a machine register
1624 } // for all instructions in the UnordVec
1627 } while(!CouldMoveAll);
1629 if (DebugPrint && DEBUG_RA) {
1630 cerr << "\nAdded instructions were reordered to:\n";
1631 for(unsigned int i=0; i < OrdVec.size(); i++)
1632 cerr << *(OrdVec[i]);
1640 void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
1641 MachineInstr *UnordInst,
1642 PhyRegAlloc &PRA) const {
1643 MachineOperand& UseOp = UnordInst->getOperand(0);
1645 if( ! UseOp.opIsDef() &&
1646 UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1648 // for the use of UnordInst, see whether there is a defining instr
1649 // before in the OrdVec
1650 bool DefEqUse = false;
1652 std::vector<MachineInstr *>::iterator OrdIt = OrdVec.begin();
1654 for( ; OrdIt != OrdVec.end(); ++OrdIt ) {
1656 MachineInstr *OrdInst = *OrdIt ;
1658 MachineOperand& DefOp =
1659 OrdInst->getOperand(OrdInst->getNumOperands()-1);
1661 if( DefOp.opIsDef() &&
1662 DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1664 //cerr << "\nDefining Ord Inst: " << *OrdInst;
1666 if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
1668 // we are here because there is a preceding def in the OrdVec
1669 // for the use in this intr we are going to insert. This
1670 // happened because the original code was like:
1671 // 1. add %ox %g0 %oy
1672 // 2. add %oy %g0 %ox
1673 // In Round1, we added 2 to OrdVec but 1 remained in UnordVec
1674 // Now we are processing %ox of 1.
1677 const int UReg = DefOp.getMachineRegNum();
1678 const int RegType = getRegType(UReg);
1679 MachineInstr *AdIBef, *AdIAft;
1681 const int StackOff = PRA.mcInfo.pushTempValue(target,
1682 getSpilledRegSize(RegType));
1684 // Save the UReg (%ox) on stack before it's destroyed
1685 vector<MachineInstr*> mvec;
1686 cpReg2MemMI(mvec, UReg, getFramePointer(), StackOff, RegType);
1687 for (vector<MachineInstr*>::iterator MI=mvec.begin(); MI != mvec.end(); ++MI) {
1688 OrdIt = OrdVec.insert(OrdIt, *MI);
1689 ++OrdIt; // OrdIt must still point to current instr we processed
1692 // Load directly into DReg (%oy)
1693 MachineOperand& DOp=
1694 (UnordInst->getOperand(UnordInst->getNumOperands()-1));
1695 assert(DOp.opIsDef() && "Last operand is not the def");
1696 const int DReg = DOp.getMachineRegNum();
1698 cpMem2RegMI(OrdVec, getFramePointer(), StackOff, DReg, RegType);
1700 cerr << "\nFixed CIRCULAR references by reordering";
1703 cerr << "\nBefore CIRCULAR Reordering:\n";
1707 cerr << "\nAfter CIRCULAR Reordering - All Inst so far:\n";
1708 for(unsigned i=0; i < OrdVec.size(); i++)
1709 cerr << *(OrdVec[i]);
1712 // Do not copy the UseInst to OrdVec
1716 }// if two registers are equal
1718 } // if Def is a register
1720 } // for each instr in OrdVec
1724 // We didn't find a def in the OrdVec, so just append this inst
1725 OrdVec.push_back( UnordInst );
1726 //cerr << "Reordered Inst (Moved Dn): " << *UnordInst;
1729 }// if the operand in UnordInst is a use