1 //===-- SparcRegInfo.cpp - Sparc Target Register Information --------------===//
3 // This file contains implementation of Sparc specific helper methods
4 // used for register allocation.
6 //===----------------------------------------------------------------------===//
8 #include "SparcInternals.h"
9 #include "SparcRegClassInfo.h"
10 #include "llvm/Target/Sparc.h"
11 #include "llvm/CodeGen/MachineCodeForMethod.h"
12 #include "llvm/CodeGen/PhyRegAlloc.h"
13 #include "llvm/CodeGen/MachineInstr.h"
14 #include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h"
15 #include "llvm/iTerminators.h"
16 #include "llvm/iOther.h"
17 #include "llvm/DerivedTypes.h"
21 UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
22 : MachineRegInfo(tgt), UltraSparcInfo(&tgt), NumOfIntArgRegs(6),
23 NumOfFloatArgRegs(32), InvalidRegNum(1000) {
25 MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID));
26 MachineRegClassArr.push_back(new SparcFloatRegClass(FloatRegClassID));
27 MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID));
28 MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID));
30 assert(SparcFloatRegOrder::StartOfNonVolatileRegs == 32 &&
31 "32 Float regs are used for float arg passing");
35 // getZeroRegNum - returns the register that contains always zero this is the
36 // unified register number
38 int UltraSparcRegInfo::getZeroRegNum() const { return SparcIntRegOrder::g0; }
40 // getCallAddressReg - returns the reg used for pushing the address when a
41 // method is called. This can be used for other purposes between calls
43 unsigned UltraSparcRegInfo::getCallAddressReg() const {
44 return SparcIntRegOrder::o7;
47 // Returns the register containing the return address.
48 // It should be made sure that this register contains the return
49 // value when a return instruction is reached.
51 unsigned UltraSparcRegInfo::getReturnAddressReg() const {
52 return SparcIntRegOrder::i7;
55 // given the unified register number, this gives the name
56 // for generating assembly code or debugging.
58 const std::string UltraSparcRegInfo::getUnifiedRegName(int reg) const {
60 return SparcIntRegOrder::getRegName(reg);
61 else if ( reg < (64 + 32) )
62 return SparcFloatRegOrder::getRegName( reg - 32);
63 else if( reg < (64+32+4) )
64 return SparcFloatCCRegOrder::getRegName( reg -32 - 64);
65 else if( reg < (64+32+4+2) ) // two names: %xcc and %ccr
66 return SparcIntCCRegOrder::getRegName( reg -32 - 64 - 4);
67 else if (reg== InvalidRegNum) //****** TODO: Remove */
70 assert(0 && "Invalid register number");
74 unsigned UltraSparcRegInfo::getFramePointer() const {
75 return SparcIntRegOrder::i6;
78 unsigned UltraSparcRegInfo::getStackPointer() const {
79 return SparcIntRegOrder::o6;
84 //---------------------------------------------------------------------------
85 // Finds the return value of a sparc specific call instruction
86 //---------------------------------------------------------------------------
88 UltraSparcRegInfo::getCallInstRetVal(const MachineInstr *CallMI) const {
89 unsigned OpCode = CallMI->getOpCode();
90 unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
94 // The one before the last implicit operand is the return value of
97 if( NumOfImpRefs > 1 )
98 if (CallMI->implicitRefIsDefined(NumOfImpRefs-2))
99 return CallMI->getImplicitRef(NumOfImpRefs-2);
101 } else if (OpCode == JMPLCALL) {
103 // The last implicit operand is the return value of a JMPL
106 if (CallMI->implicitRefIsDefined(NumOfImpRefs-1))
107 return CallMI->getImplicitRef(NumOfImpRefs-1);
109 assert(0 && "OpCode must be CALL/JMPL for a call instr");
116 //---------------------------------------------------------------------------
117 // Finds the return address of a call sparc specific call instruction
118 //---------------------------------------------------------------------------
120 UltraSparcRegInfo::getCallInstRetAddr(const MachineInstr *CallMI) const {
121 unsigned OpCode = CallMI->getOpCode();
123 if (OpCode == CALL) {
124 unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
126 assert( NumOfImpRefs && "CALL instr must have at least on ImpRef");
128 // The last implicit operand is the return address of a CALL instr
130 return CallMI->getImplicitRef(NumOfImpRefs-1);
132 } else if(OpCode == JMPLCALL) {
133 MachineOperand &MO = (MachineOperand &)CallMI->getOperand(2);
134 return MO.getVRegValue();
137 assert(0 && "OpCode must be CALL/JMPL for a call instr");
141 // The following 3 methods are used to find the RegType (see enum above)
142 // of a LiveRange, Value and using the unified RegClassID
144 int UltraSparcRegInfo::getRegType(const LiveRange *LR) const {
145 switch (LR->getRegClass()->getID()) {
146 case IntRegClassID: return IntRegType;
147 case FloatRegClassID: {
148 const Type *Typ = LR->getType();
149 if (Typ == Type::FloatTy)
150 return FPSingleRegType;
151 else if (Typ == Type::DoubleTy)
152 return FPDoubleRegType;
153 assert(0 && "Unknown type in FloatRegClass");
155 case IntCCRegClassID: return IntCCRegType;
156 case FloatCCRegClassID: return FloatCCRegType;
157 default: assert( 0 && "Unknown reg class ID");
162 int UltraSparcRegInfo::getRegType(const Value *Val) const {
165 switch (getRegClassIDOfValue(Val)) {
166 case IntRegClassID: return IntRegType;
167 case FloatRegClassID:
168 Typ = Val->getType()->getPrimitiveID();
169 if (Typ == Type::FloatTyID)
170 return FPSingleRegType;
171 else if (Typ == Type::DoubleTyID)
172 return FPDoubleRegType;
173 assert(0 && "Unknown type in FloatRegClass");
175 case IntCCRegClassID: return IntCCRegType;
176 case FloatCCRegClassID: return FloatCCRegType ;
177 default: assert(0 && "Unknown reg class ID");
182 int UltraSparcRegInfo::getRegType(int reg) const {
185 else if (reg < (32 + 32))
186 return FPSingleRegType;
187 else if (reg < (64 + 32))
188 return FPDoubleRegType;
189 else if (reg < (64+32+4))
190 return FloatCCRegType;
191 else if (reg < (64+32+4+2))
194 assert(0 && "Invalid register number in getRegType");
201 //---------------------------------------------------------------------------
202 // Finds the # of actual arguments of the call instruction
203 //---------------------------------------------------------------------------
205 UltraSparcRegInfo::getCallInstNumArgs(const MachineInstr *CallMI) const {
207 unsigned OpCode = CallMI->getOpCode();
208 unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
210 if (OpCode == CALL) {
211 switch (NumOfImpRefs) {
212 case 0: assert(0 && "A CALL inst must have at least one ImpRef (RetAddr)");
214 default: // two or more implicit refs
215 if (CallMI->implicitRefIsDefined(NumOfImpRefs-2))
216 return NumOfImpRefs - 2;
218 return NumOfImpRefs - 1;
220 } else if (OpCode == JMPLCALL) {
222 // The last implicit operand is the return value of a JMPL instr
223 if( NumOfImpRefs > 0 ) {
224 if (CallMI->implicitRefIsDefined(NumOfImpRefs-1))
225 return NumOfImpRefs - 1;
233 assert(0 && "OpCode must be CALL/JMPL for a call instr");
239 //---------------------------------------------------------------------------
240 // Finds whether a call is an indirect call
241 //---------------------------------------------------------------------------
242 bool UltraSparcRegInfo::isVarArgCall(const MachineInstr *CallMI) const {
244 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
246 const MachineOperand & calleeOp = CallMI->getOperand(0);
247 Value *calleeVal = calleeOp.getVRegValue();
249 PointerType *PT = cast<PointerType> (calleeVal->getType());
250 MethodType *MT = cast<MethodType>(PT->getElementType());
252 return MT->isVarArg();
258 //---------------------------------------------------------------------------
259 // Suggests a register for the ret address in the RET machine instruction.
260 // We always suggest %i7 by convention.
261 //---------------------------------------------------------------------------
262 void UltraSparcRegInfo::suggestReg4RetAddr(const MachineInstr *RetMI,
263 LiveRangeInfo& LRI) const {
265 assert( (RetMI->getNumOperands() >= 2)
266 && "JMPL/RETURN must have 3 and 2 operands respectively");
268 MachineOperand & MO = ( MachineOperand &) RetMI->getOperand(0);
270 // return address is always mapped to i7
272 MO.setRegForValue( getUnifiedRegNum( IntRegClassID, SparcIntRegOrder::i7) );
274 // Possible Optimization:
275 // Instead of setting the color, we can suggest one. In that case,
276 // we have to test later whether it received the suggested color.
277 // In that case, a LR has to be created at the start of method.
278 // It has to be done as follows (remove the setRegVal above):
280 // const Value *RetAddrVal = MO.getVRegValue();
281 // assert( RetAddrVal && "LR for ret address must be created at start");
282 // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
283 // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
284 // SparcIntRegOrdr::i7) );
288 //---------------------------------------------------------------------------
289 // Suggests a register for the ret address in the JMPL/CALL machine instr.
290 // Sparc ABI dictates that %o7 be used for this purpose.
291 //---------------------------------------------------------------------------
292 void UltraSparcRegInfo::suggestReg4CallAddr(const MachineInstr * CallMI,
294 std::vector<RegClass *> RCList) const {
297 const Value *RetAddrVal = getCallInstRetAddr( CallMI );
299 // RetAddrVal cannot be NULL (asserted in getCallInstRetAddr)
300 // create a new LR for the return address and color it
302 LiveRange * RetAddrLR = new LiveRange();
303 RetAddrLR->insert( RetAddrVal );
304 unsigned RegClassID = getRegClassIDOfValue( RetAddrVal );
305 RetAddrLR->setRegClass( RCList[RegClassID] );
306 RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o7));
307 LRI.addLRToMap( RetAddrVal, RetAddrLR);
314 //---------------------------------------------------------------------------
315 // This method will suggest colors to incoming args to a method.
316 // According to the Sparc ABI, the first 6 incoming args are in
317 // %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float).
318 // If the arg is passed on stack due to the lack of regs, NOTHING will be
319 // done - it will be colored (or spilled) as a normal live range.
320 //---------------------------------------------------------------------------
321 void UltraSparcRegInfo::suggestRegs4MethodArgs(const Method *Meth,
322 LiveRangeInfo& LRI) const
325 // get the argument list
326 const Method::ArgumentListType& ArgList = Meth->getArgumentList();
327 // get an iterator to arg list
328 Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
331 for( unsigned argNo=0; ArgIt != ArgList.end() ; ++ArgIt, ++argNo) {
334 LiveRange *const LR = LRI.getLiveRangeForValue((const Value *) *ArgIt);
335 assert( LR && "No live range found for method arg");
337 unsigned RegType = getRegType( LR );
340 // if the arg is in int class - allocate a reg for an int arg
342 if( RegType == IntRegType ) {
344 if( argNo < NumOfIntArgRegs) {
345 LR->setSuggestedColor( SparcIntRegOrder::i0 + argNo );
348 // Do NOTHING as this will be colored as a normal value.
349 if (DEBUG_RA) cerr << " Int Regr not suggested for method arg\n";
353 else if( RegType==FPSingleRegType && (argNo*2+1) < NumOfFloatArgRegs)
354 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2 + 1) );
357 else if( RegType == FPDoubleRegType && (argNo*2) < NumOfFloatArgRegs)
358 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2) );
365 //---------------------------------------------------------------------------
366 // This method is called after graph coloring to move incoming args to
367 // the correct hardware registers if they did not receive the correct
368 // (suggested) color through graph coloring.
369 //---------------------------------------------------------------------------
370 void UltraSparcRegInfo::colorMethodArgs(const Method *Meth,
372 AddedInstrns *FirstAI) const {
374 // get the argument list
375 const Method::ArgumentListType& ArgList = Meth->getArgumentList();
376 // get an iterator to arg list
377 Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
383 for( unsigned argNo=0; ArgIt != ArgList.end() ; ++ArgIt, ++argNo) {
386 LiveRange *const LR = LRI.getLiveRangeForValue((const Value *) *ArgIt);
387 assert( LR && "No live range found for method arg");
390 unsigned RegType = getRegType( LR );
391 unsigned RegClassID = (LR->getRegClass())->getID();
393 // Find whether this argument is coming in a register (if not, on stack)
394 // Also find the correct register that the argument must go (UniArgReg)
396 bool isArgInReg = false;
397 unsigned UniArgReg = InvalidRegNum; // reg that LR MUST be colored with
399 if( (RegType== IntRegType && argNo < NumOfIntArgRegs)) {
401 UniArgReg = getUnifiedRegNum( RegClassID, SparcIntRegOrder::i0 + argNo );
403 else if(RegType == FPSingleRegType && argNo < NumOfFloatArgRegs) {
405 UniArgReg = getUnifiedRegNum( RegClassID,
406 SparcFloatRegOrder::f0 + argNo*2 + 1 ) ;
408 else if(RegType == FPDoubleRegType && argNo < NumOfFloatArgRegs) {
410 UniArgReg = getUnifiedRegNum(RegClassID, SparcFloatRegOrder::f0+argNo*2);
414 if( LR->hasColor() ) { // if this arg received a register
416 unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
418 // if LR received the correct color, nothing to do
420 if( UniLRReg == UniArgReg )
423 // We are here because the LR did not receive the suggested
424 // but LR received another register.
425 // Now we have to copy the %i reg (or stack pos of arg)
426 // to the register the LR was colored with.
428 // if the arg is coming in UniArgReg register, it MUST go into
429 // the UniLRReg register
432 AdMI = cpReg2RegMI( UniArgReg, UniLRReg, RegType );
436 // Now the arg is coming on stack. Since the LR recieved a register,
437 // we just have to load the arg on stack into that register
439 const MachineFrameInfo& frameInfo = target.getFrameInfo();
440 assert(frameInfo.argsOnStackHaveFixedSize());
442 bool growUp; // find the offset of arg in stack frame
444 frameInfo.getFirstIncomingArgOffset(MachineCodeForMethod::get(Meth),
447 growUp? firstArg + argNo * frameInfo.getSizeOfEachArgOnStack()
448 : firstArg - argNo * frameInfo.getSizeOfEachArgOnStack();
450 AdMI = cpMem2RegMI(getFramePointer(), offsetFromFP,
454 FirstAI->InstrnsBefore.push_back( AdMI );
456 } // if LR received a color
460 // Now, the LR did not receive a color. But it has a stack offset for
462 // So, if the arg is coming in UniArgReg register, we can just move
463 // that on to the stack pos of LR
466 cpReg2MemMI(UniArgReg, getFramePointer(),
467 LR->getSpillOffFromFP(), RegType );
469 FirstAI->InstrnsBefore.push_back( AdMI );
474 // Now the arg is coming on stack. Since the LR did NOT
475 // recieved a register as well, it is allocated a stack position. We
476 // can simply change the stack poistion of the LR. We can do this,
477 // since this method is called before any other method that makes
478 // uses of the stack pos of the LR (e.g., updateMachineInstr)
480 const MachineFrameInfo& frameInfo = target.getFrameInfo();
481 assert(frameInfo.argsOnStackHaveFixedSize());
484 int firstArg = frameInfo.getFirstIncomingArgOffset(MachineCodeForMethod::get(Meth), growUp);
486 growUp? firstArg + argNo * frameInfo.getSizeOfEachArgOnStack()
487 : firstArg - argNo * frameInfo.getSizeOfEachArgOnStack();
489 LR->modifySpillOffFromFP( offsetFromFP );
494 } // for each incoming argument
500 //---------------------------------------------------------------------------
501 // This method is called before graph coloring to suggest colors to the
502 // outgoing call args and the return value of the call.
503 //---------------------------------------------------------------------------
504 void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *CallMI,
506 std::vector<RegClass *> RCList) const {
508 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
510 suggestReg4CallAddr(CallMI, LRI, RCList);
513 // First color the return value of the call instruction. The return value
514 // will be in %o0 if the value is an integer type, or in %f0 if the
515 // value is a float type.
517 // the return value cannot have a LR in machine instruction since it is
518 // only defined by the call instruction
520 // if type is not void, create a new live range and set its
521 // register class and add to LRI
524 const Value *RetVal = getCallInstRetVal( CallMI );
528 assert ((!LRI.getLiveRangeForValue(RetVal)) &&
529 "LR for ret Value of call already definded!");
531 // create a new LR for the return value
532 LiveRange *RetValLR = new LiveRange();
533 RetValLR->insert(RetVal);
534 unsigned RegClassID = getRegClassIDOfValue(RetVal);
535 RetValLR->setRegClass(RCList[RegClassID]);
536 LRI.addLRToMap(RetVal, RetValLR);
538 // now suggest a register depending on the register class of ret arg
540 if( RegClassID == IntRegClassID )
541 RetValLR->setSuggestedColor(SparcIntRegOrder::o0);
542 else if (RegClassID == FloatRegClassID )
543 RetValLR->setSuggestedColor(SparcFloatRegOrder::f0 );
544 else assert( 0 && "Unknown reg class for return value of call\n");
548 // Now suggest colors for arguments (operands) of the call instruction.
549 // Colors are suggested only if the arg number is smaller than the
550 // the number of registers allocated for argument passing.
551 // Now, go thru call args - implicit operands of the call MI
553 unsigned NumOfCallArgs = getCallInstNumArgs( CallMI );
555 for(unsigned argNo=0, i=0; i < NumOfCallArgs; ++i, ++argNo ) {
557 const Value *CallArg = CallMI->getImplicitRef(i);
559 // get the LR of call operand (parameter)
560 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
562 // not possible to have a null LR since all args (even consts)
563 // must be defined before
565 cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) << "\n";
566 assert(0 && "NO LR for call arg");
569 unsigned RegType = getRegType( LR );
571 // if the arg is in int class - allocate a reg for an int arg
572 if( RegType == IntRegType ) {
574 if( argNo < NumOfIntArgRegs)
575 LR->setSuggestedColor( SparcIntRegOrder::o0 + argNo );
578 // Do NOTHING as this will be colored as a normal value.
579 cerr << " Regr not suggested for int call arg\n";
582 else if( RegType == FPSingleRegType && (argNo*2 +1)< NumOfFloatArgRegs)
583 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2 + 1) );
586 else if( RegType == FPDoubleRegType && (argNo*2) < NumOfFloatArgRegs)
587 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2) );
590 } // for all call arguments
595 //---------------------------------------------------------------------------
596 // After graph coloring, we have call this method to see whehter the return
597 // value and the call args received the correct colors. If not, we have
598 // to instert copy instructions.
599 //---------------------------------------------------------------------------
601 void UltraSparcRegInfo::colorCallArgs(const MachineInstr *CallMI,
603 AddedInstrns *CallAI,
605 const BasicBlock *BB) const {
607 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
609 // Reset the optional args area in the stack frame
610 // since that is reused for each call
612 PRA.mcInfo.resetOptionalArgs(target);
614 // First color the return value of the call.
615 // If there is a LR for the return value, it means this
616 // method returns a value
620 const Value *RetVal = getCallInstRetVal( CallMI );
623 LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal );
626 cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
627 assert(0 && "ERR:No LR for non-void return value");
630 unsigned RegClassID = (RetValLR->getRegClass())->getID();
631 bool recvCorrectColor = false;
633 unsigned CorrectCol; // correct color for ret value
634 if(RegClassID == IntRegClassID)
635 CorrectCol = SparcIntRegOrder::o0;
636 else if(RegClassID == FloatRegClassID)
637 CorrectCol = SparcFloatRegOrder::f0;
639 assert( 0 && "Unknown RegClass");
643 // if the LR received the correct color, NOTHING to do
645 if( RetValLR->hasColor() )
646 if( RetValLR->getColor() == CorrectCol )
647 recvCorrectColor = true;
650 // if we didn't receive the correct color for some reason,
651 // put copy instruction
653 if( !recvCorrectColor ) {
655 unsigned RegType = getRegType( RetValLR );
657 // the reg that LR must be colored with
658 unsigned UniRetReg = getUnifiedRegNum( RegClassID, CorrectCol);
660 if( RetValLR->hasColor() ) {
663 UniRetLRReg=getUnifiedRegNum(RegClassID,RetValLR->getColor());
665 // the return value is coming in UniRetReg but has to go into
668 AdMI = cpReg2RegMI( UniRetReg, UniRetLRReg, RegType );
673 // if the LR did NOT receive a color, we have to move the return
674 // value coming in UniRetReg to the stack pos of spilled LR
676 AdMI = cpReg2MemMI(UniRetReg, getFramePointer(),
677 RetValLR->getSpillOffFromFP(), RegType );
680 CallAI->InstrnsAfter.push_back( AdMI );
682 } // the LR didn't receive the suggested color
684 } // if there a return value
687 //-------------------------------------------
688 // Now color all args of the call instruction
689 //-------------------------------------------
691 std::vector<MachineInstr *> AddedInstrnsBefore;
693 unsigned NumOfCallArgs = getCallInstNumArgs( CallMI );
695 bool VarArgCall = isVarArgCall( CallMI );
697 if(VarArgCall) cerr << "\nVar arg call found!!\n";
699 for(unsigned argNo=0, i=0; i < NumOfCallArgs; ++i, ++argNo ) {
701 const Value *CallArg = CallMI->getImplicitRef(i);
703 // get the LR of call operand (parameter)
704 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
706 unsigned RegType = getRegType( CallArg );
707 unsigned RegClassID = getRegClassIDOfValue( CallArg);
709 // find whether this argument is coming in a register (if not, on stack)
711 bool isArgInReg = false;
712 unsigned UniArgReg = InvalidRegNum; // reg that LR must be colored with
714 if( (RegType== IntRegType && argNo < NumOfIntArgRegs)) {
716 UniArgReg = getUnifiedRegNum(RegClassID, SparcIntRegOrder::o0 + argNo );
718 else if(RegType == FPSingleRegType && argNo < NumOfFloatArgRegs) {
722 UniArgReg = getUnifiedRegNum(RegClassID,
723 SparcFloatRegOrder::f0 + (argNo*2 + 1) );
725 // a variable argument call - must pass float arg in %o's
726 if( argNo < NumOfIntArgRegs)
727 UniArgReg=getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o0+argNo);
733 else if(RegType == FPDoubleRegType && argNo < NumOfFloatArgRegs) {
737 UniArgReg =getUnifiedRegNum(RegClassID,SparcFloatRegOrder::f0+argNo*2);
739 // a variable argument call - must pass float arg in %o's
740 if( argNo < NumOfIntArgRegs)
741 UniArgReg=getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o0+argNo);
747 // not possible to have a null LR since all args (even consts)
748 // must be defined before
750 cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) << "\n";
751 assert(0 && "NO LR for call arg");
755 if (LR->hasColor()) {
756 unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
758 // if LR received the correct color, nothing to do
759 if( UniLRReg == UniArgReg )
762 // We are here because though the LR is allocated a register, it
763 // was not allocated the suggested register. So, we have to copy %ix reg
764 // (or stack pos of arg) to the register it was colored with
766 // the LR is colored with UniLRReg but has to go into UniArgReg
767 // to pass it as an argument
771 if( VarArgCall && RegClassID == FloatRegClassID ) {
774 // for a variable argument call, the float reg must go in a %o reg.
775 // We have to move a float reg to an int reg via memory.
776 // The store instruction will be directly added to
777 // CallAI->InstrnsBefore since it does not need reordering
779 int TmpOff = PRA.mcInfo.pushTempValue(target,
780 getSpilledRegSize(RegType));
782 AdMI = cpReg2MemMI(UniLRReg, getFramePointer(), TmpOff, RegType );
783 CallAI->InstrnsBefore.push_back( AdMI );
785 AdMI = cpMem2RegMI(getFramePointer(), TmpOff, UniArgReg, IntRegType);
786 AddedInstrnsBefore.push_back( AdMI );
790 AdMI = cpReg2RegMI(UniLRReg, UniArgReg, RegType );
791 AddedInstrnsBefore.push_back( AdMI );
795 // Now, we have to pass the arg on stack. Since LR received a register
796 // we just have to move that register to the stack position where
797 // the argument must be passed
799 int argOffset = PRA.mcInfo.allocateOptionalArg(target, LR->getType());
801 AdMI = cpReg2MemMI(UniLRReg, getStackPointer(), argOffset, RegType );
803 // Now add the instruction. We can directly add to
804 // CallAI->InstrnsBefore since we are just saving a reg on stack
806 CallAI->InstrnsBefore.push_back( AdMI );
808 //cerr << "\nCaution: Passing a reg on stack";
812 } else { // LR is not colored (i.e., spilled)
816 // Now the LR did NOT recieve a register but has a stack poistion.
817 // Since, the outgoing arg goes in a register we just have to insert
818 // a load instruction to load the LR to outgoing register
820 if( VarArgCall && RegClassID == FloatRegClassID )
821 AdMI = cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
822 UniArgReg, IntRegType );
824 AdMI = cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
825 UniArgReg, RegType );
827 cerr << "\nCaution: Loading a spilled val to a reg as a call arg";
828 AddedInstrnsBefore.push_back( AdMI ); // Now add the instruction
832 // Now, we have to pass the arg on stack. Since LR also did NOT
833 // receive a register we have to move an argument in memory to
834 // outgoing parameter on stack.
836 // Optoimize: Optimize when reverse pointers in MahineInstr are
838 // call PRA.getUnusedRegAtMI(....) to get an unused reg. Only if this
839 // fails, then use the following code. Currently, we cannot call the
840 // above method since we cannot find LVSetBefore without the BB
842 int TReg = PRA.getUniRegNotUsedByThisInst( LR->getRegClass(), CallMI );
844 int TmpOff = PRA.mcInfo.pushTempValue(target,
845 getSpilledRegSize(getRegType(LR)) );
848 int argOffset = PRA.mcInfo.allocateOptionalArg(target, LR->getType());
850 MachineInstr *Ad1, *Ad2, *Ad3, *Ad4;
853 // (1) Save TReg on stack
854 // (2) Load LR value into TReg from stack pos of LR
855 // (3) Store Treg on outgoing Arg pos on stack
856 // (4) Load the old value of TReg from stack to TReg (restore it)
858 Ad1 = cpReg2MemMI(TReg, getFramePointer(), TmpOff, RegType );
859 Ad2 = cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
861 Ad3 = cpReg2MemMI(TReg, getStackPointer(), argOffset, RegType );
862 Ad4 = cpMem2RegMI(getFramePointer(), TmpOff, TReg, RegType );
864 // We directly add to CallAI->InstrnsBefore instead of adding to
865 // AddedInstrnsBefore since these instructions must not be
868 CallAI->InstrnsBefore.push_back( Ad1 );
869 CallAI->InstrnsBefore.push_back( Ad2 );
870 CallAI->InstrnsBefore.push_back( Ad3 );
871 CallAI->InstrnsBefore.push_back( Ad4 );
873 cerr << "\nCaution: Call arg moved from stack2stack for: " << *CallMI ;
876 } // for each parameter in call instruction
879 // if we added any instruction before the call instruction, verify
880 // that they are in the proper order and if not, reorder them
882 if (!AddedInstrnsBefore.empty()) {
885 cerr << "\nCalling reorder with instrns: \n";
886 for(unsigned i=0; i < AddedInstrnsBefore.size(); i++)
887 cerr << *(AddedInstrnsBefore[i]);
890 std::vector<MachineInstr *> TmpVec;
891 OrderAddedInstrns(AddedInstrnsBefore, TmpVec, PRA);
894 cerr << "\nAfter reordering instrns: \n";
895 for(unsigned i = 0; i < TmpVec.size(); i++)
899 // copy the results back from TmpVec to InstrnsBefore
900 for(unsigned i=0; i < TmpVec.size(); i++)
901 CallAI->InstrnsBefore.push_back( TmpVec[i] );
905 // now insert caller saving code for this call instruction
907 insertCallerSavingCode(CallMI, BB, PRA);
909 // Reset optional args area again to be safe
910 PRA.mcInfo.resetOptionalArgs(target);
913 //---------------------------------------------------------------------------
914 // This method is called for an LLVM return instruction to identify which
915 // values will be returned from this method and to suggest colors.
916 //---------------------------------------------------------------------------
917 void UltraSparcRegInfo::suggestReg4RetValue(const MachineInstr *RetMI,
918 LiveRangeInfo &LRI) const {
920 assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) );
922 suggestReg4RetAddr(RetMI, LRI);
924 // if there is an implicit ref, that has to be the ret value
925 if( RetMI->getNumImplicitRefs() > 0 ) {
927 // The first implicit operand is the return value of a return instr
928 const Value *RetVal = RetMI->getImplicitRef(0);
930 LiveRange *const LR = LRI.getLiveRangeForValue( RetVal );
933 cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
934 assert(0 && "No LR for return value of non-void method");
937 unsigned RegClassID = (LR->getRegClass())->getID();
939 if (RegClassID == IntRegClassID)
940 LR->setSuggestedColor(SparcIntRegOrder::i0);
941 else if (RegClassID == FloatRegClassID)
942 LR->setSuggestedColor(SparcFloatRegOrder::f0);
948 //---------------------------------------------------------------------------
949 // Colors the return value of a method to %i0 or %f0, if possible. If it is
950 // not possilbe to directly color the LR, insert a copy instruction to move
951 // the LR to %i0 or %f0. When the LR is spilled, instead of the copy, we
952 // have to put a load instruction.
953 //---------------------------------------------------------------------------
954 void UltraSparcRegInfo::colorRetValue(const MachineInstr *RetMI,
956 AddedInstrns *RetAI) const {
958 assert((UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode()));
960 // if there is an implicit ref, that has to be the ret value
961 if(RetMI->getNumImplicitRefs() > 0) {
963 // The first implicit operand is the return value of a return instr
964 const Value *RetVal = RetMI->getImplicitRef(0);
966 LiveRange *LR = LRI.getLiveRangeForValue(RetVal);
969 cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
970 // assert( LR && "No LR for return value of non-void method");
974 unsigned RegClassID = getRegClassIDOfValue(RetVal);
975 unsigned RegType = getRegType( RetVal );
978 if(RegClassID == IntRegClassID)
979 CorrectCol = SparcIntRegOrder::i0;
980 else if(RegClassID == FloatRegClassID)
981 CorrectCol = SparcFloatRegOrder::f0;
983 assert (0 && "Unknown RegClass");
987 // if the LR received the correct color, NOTHING to do
989 if (LR->hasColor() && LR->getColor() == CorrectCol)
992 unsigned UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
994 if (LR->hasColor()) {
996 // We are here because the LR was allocted a regiter
997 // It may be the suggested register or not
999 // copy the LR of retun value to i0 or f0
1001 unsigned UniLRReg =getUnifiedRegNum( RegClassID, LR->getColor());
1003 // the LR received UniLRReg but must be colored with UniRetReg
1004 // to pass as the return value
1005 RetAI->InstrnsBefore.push_back(cpReg2RegMI(UniLRReg, UniRetReg, RegType));
1007 else { // if the LR is spilled
1008 MachineInstr *AdMI = cpMem2RegMI(getFramePointer(),
1009 LR->getSpillOffFromFP(),
1010 UniRetReg, RegType);
1011 RetAI->InstrnsBefore.push_back(AdMI);
1012 cerr << "\nCopied the return value from stack\n";
1015 } // if there is a return value
1020 //---------------------------------------------------------------------------
1021 // Copy from a register to register. Register number must be the unified
1023 //---------------------------------------------------------------------------
1025 MachineInstr * UltraSparcRegInfo::cpReg2RegMI(unsigned SrcReg, unsigned DestReg,
1026 int RegType) const {
1028 assert( ((int)SrcReg != InvalidRegNum) && ((int)DestReg != InvalidRegNum) &&
1029 "Invalid Register");
1031 MachineInstr * MI = NULL;
1037 case FloatCCRegType:
1038 MI = new MachineInstr(ADD, 3);
1039 MI->SetMachineOperand(0, SrcReg, false);
1040 MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
1041 MI->SetMachineOperand(2, DestReg, true);
1044 case FPSingleRegType:
1045 MI = new MachineInstr(FMOVS, 2);
1046 MI->SetMachineOperand(0, SrcReg, false);
1047 MI->SetMachineOperand(1, DestReg, true);
1050 case FPDoubleRegType:
1051 MI = new MachineInstr(FMOVD, 2);
1052 MI->SetMachineOperand(0, SrcReg, false);
1053 MI->SetMachineOperand(1, DestReg, true);
1057 assert(0 && "Unknow RegType");
1064 //---------------------------------------------------------------------------
1065 // Copy from a register to memory (i.e., Store). Register number must
1066 // be the unified register number
1067 //---------------------------------------------------------------------------
1070 MachineInstr * UltraSparcRegInfo::cpReg2MemMI(unsigned SrcReg,
1071 unsigned DestPtrReg,
1072 int Offset, int RegType) const {
1073 MachineInstr * MI = NULL;
1076 case FloatCCRegType:
1077 MI = new MachineInstr(STX, 3);
1078 MI->SetMachineOperand(0, SrcReg, false);
1079 MI->SetMachineOperand(1, DestPtrReg, false);
1080 MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
1081 (int64_t) Offset, false);
1084 case FPSingleRegType:
1085 MI = new MachineInstr(ST, 3);
1086 MI->SetMachineOperand(0, SrcReg, false);
1087 MI->SetMachineOperand(1, DestPtrReg, false);
1088 MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
1089 (int64_t) Offset, false);
1092 case FPDoubleRegType:
1093 MI = new MachineInstr(STD, 3);
1094 MI->SetMachineOperand(0, SrcReg, false);
1095 MI->SetMachineOperand(1, DestPtrReg, false);
1096 MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
1097 (int64_t) Offset, false);
1101 assert( 0 && "Cannot directly store %ccr to memory");
1104 assert(0 && "Unknow RegType in cpReg2MemMI");
1111 //---------------------------------------------------------------------------
1112 // Copy from memory to a reg (i.e., Load) Register number must be the unified
1114 //---------------------------------------------------------------------------
1117 MachineInstr * UltraSparcRegInfo::cpMem2RegMI(unsigned SrcPtrReg,
1120 int RegType) const {
1121 MachineInstr * MI = NULL;
1124 case FloatCCRegType:
1125 MI = new MachineInstr(LDX, 3);
1126 MI->SetMachineOperand(0, SrcPtrReg, false);
1127 MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,
1128 (int64_t) Offset, false);
1129 MI->SetMachineOperand(2, DestReg, true);
1132 case FPSingleRegType:
1133 MI = new MachineInstr(LD, 3);
1134 MI->SetMachineOperand(0, SrcPtrReg, false);
1135 MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,
1136 (int64_t) Offset, false);
1137 MI->SetMachineOperand(2, DestReg, true);
1141 case FPDoubleRegType:
1142 MI = new MachineInstr(LDD, 3);
1143 MI->SetMachineOperand(0, SrcPtrReg, false);
1144 MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,
1145 (int64_t) Offset, false);
1146 MI->SetMachineOperand(2, DestReg, true);
1150 assert( 0 && "Cannot directly load into %ccr from memory");
1153 assert(0 && "Unknown RegType in cpMem2RegMI");
1163 //---------------------------------------------------------------------------
1164 // Generate a copy instruction to copy a value to another. Temporarily
1165 // used by PhiElimination code.
1166 //---------------------------------------------------------------------------
1169 MachineInstr *UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest) const {
1170 int RegType = getRegType( Src );
1172 assert( (RegType==getRegType(Src)) && "Src & Dest are diff types");
1174 MachineInstr * MI = NULL;
1178 MI = new MachineInstr(ADD, 3);
1179 MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
1180 MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
1181 MI->SetMachineOperand(2, MachineOperand:: MO_VirtualRegister, Dest, true);
1184 case FPSingleRegType:
1185 MI = new MachineInstr(FMOVS, 2);
1186 MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
1187 MI->SetMachineOperand(1, MachineOperand:: MO_VirtualRegister, Dest, true);
1191 case FPDoubleRegType:
1192 MI = new MachineInstr(FMOVD, 2);
1193 MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
1194 MI->SetMachineOperand(1, MachineOperand:: MO_VirtualRegister, Dest, true);
1198 assert(0 && "Unknow RegType in CpValu2Value");
1209 //----------------------------------------------------------------------------
1210 // This method inserts caller saving/restoring instructons before/after
1211 // a call machine instruction. The caller saving/restoring instructions are
1214 // ** caller saving instructions
1215 // other instructions inserted for the call by ColorCallArg
1217 // other instructions inserted for the call ColorCallArg
1218 // ** caller restoring instructions
1220 //----------------------------------------------------------------------------
1223 void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *MInst,
1224 const BasicBlock *BB,
1225 PhyRegAlloc &PRA) const {
1227 // has set to record which registers were saved/restored
1229 std::hash_set<unsigned> PushedRegSet;
1231 // Now find the LR of the return value of the call
1232 // The last *implicit operand* is the return value of a call
1233 // Insert it to to he PushedRegSet since we must not save that register
1234 // and restore it after the call.
1235 // We do this because, we look at the LV set *after* the instruction
1236 // to determine, which LRs must be saved across calls. The return value
1237 // of the call is live in this set - but we must not save/restore it.
1240 const Value *RetVal = getCallInstRetVal( MInst );
1243 LiveRange *RetValLR = PRA.LRI.getLiveRangeForValue( RetVal );
1244 assert(RetValLR && "No LR for RetValue of call");
1246 if (RetValLR->hasColor())
1247 PushedRegSet.insert(
1248 getUnifiedRegNum((RetValLR->getRegClass())->getID(),
1249 RetValLR->getColor() ) );
1253 const ValueSet &LVSetAft = PRA.LVI->getLiveVarSetAfterMInst(MInst, BB);
1254 ValueSet::const_iterator LIt = LVSetAft.begin();
1256 // for each live var in live variable set after machine inst
1257 for( ; LIt != LVSetAft.end(); ++LIt) {
1259 // get the live range corresponding to live var
1260 LiveRange *const LR = PRA.LRI.getLiveRangeForValue(*LIt );
1262 // LR can be null if it is a const since a const
1263 // doesn't have a dominating def - see Assumptions above
1266 if( LR->hasColor() ) {
1268 unsigned RCID = (LR->getRegClass())->getID();
1269 unsigned Color = LR->getColor();
1271 if ( isRegVolatile(RCID, Color) ) {
1273 // if the value is in both LV sets (i.e., live before and after
1274 // the call machine instruction)
1276 unsigned Reg = getUnifiedRegNum(RCID, Color);
1278 if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
1280 // if we haven't already pushed that register
1282 unsigned RegType = getRegType( LR );
1284 // Now get two instructions - to push on stack and pop from stack
1285 // and add them to InstrnsBefore and InstrnsAfter of the
1289 int StackOff = PRA.mcInfo.pushTempValue(target,
1290 getSpilledRegSize(RegType));
1293 MachineInstr *AdIBefCC, *AdIAftCC, *AdICpCC;
1294 MachineInstr *AdIBef, *AdIAft;
1297 //---- Insert code for pushing the reg on stack ----------
1299 if( RegType == IntCCRegType ) {
1301 // Handle IntCCRegType specially since we cannot directly
1302 // push %ccr on to the stack
1304 const ValueSet &LVSetBef =
1305 PRA.LVI->getLiveVarSetBeforeMInst(MInst, BB);
1307 // get a free INTEGER register
1309 PRA.getUsableUniRegAtMI(LR->getRegClass(), IntRegType, MInst,
1310 &LVSetBef, AdIBefCC, AdIAftCC);
1312 // insert the instructions in reverse order since we are
1313 // adding them to the front of InstrnsBefore
1316 PRA.AddedInstrMap[MInst]->InstrnsBefore.push_front(AdIAftCC);
1318 AdICpCC = cpCCR2IntMI(FreeIntReg);
1319 PRA.AddedInstrMap[MInst]->InstrnsBefore.push_front(AdICpCC);
1322 PRA.AddedInstrMap[MInst]->InstrnsBefore.push_front(AdIBefCC);
1325 cerr << "\n!! Inserted caller saving (push) inst for %ccr:";
1326 if(AdIBefCC) cerr << "\t" << *(AdIBefCC);
1327 cerr << "\t" << *AdICpCC;
1328 if(AdIAftCC) cerr << "\t" << *(AdIAftCC);
1332 // for any other register type, just add the push inst
1333 AdIBef = cpReg2MemMI(Reg, getFramePointer(), StackOff, RegType );
1334 PRA.AddedInstrMap[MInst]->InstrnsBefore.push_front(AdIBef);
1338 //---- Insert code for popping the reg from the stack ----------
1340 if (RegType == IntCCRegType) {
1342 // Handle IntCCRegType specially since we cannot directly
1343 // pop %ccr on from the stack
1345 // get a free INT register
1347 PRA.getUsableUniRegAtMI(LR->getRegClass(), IntRegType, MInst,
1348 &LVSetAft, AdIBefCC, AdIAftCC);
1351 PRA.AddedInstrMap[MInst]->InstrnsAfter.push_back(AdIBefCC);
1353 AdICpCC = cpInt2CCRMI(FreeIntReg);
1354 PRA.AddedInstrMap[MInst]->InstrnsAfter.push_back(AdICpCC);
1357 PRA.AddedInstrMap[MInst]->InstrnsAfter.push_back(AdIAftCC);
1361 cerr << "\n!! Inserted caller saving (pop) inst for %ccr:";
1362 if(AdIBefCC) cerr << "\t" << *(AdIBefCC);
1363 cerr << "\t" << *AdICpCC;
1364 if(AdIAftCC) cerr << "\t" << *(AdIAftCC);
1368 // for any other register type, just add the pop inst
1369 AdIAft = cpMem2RegMI(getFramePointer(), StackOff, Reg, RegType );
1370 PRA.AddedInstrMap[MInst]->InstrnsAfter.push_back(AdIAft);
1373 PushedRegSet.insert(Reg);
1376 cerr << "\nFor call inst:" << *MInst;
1377 cerr << " -inserted caller saving instrs:\n\t ";
1378 if( RegType == IntCCRegType )
1379 cerr << *AdIBefCC << "\t" << *AdIAftCC ;
1381 cerr << *AdIBef << "\t" << *AdIAft ;
1383 } // if not already pushed
1385 } // if LR has a volatile color
1387 } // if LR has color
1389 } // if there is a LR for Var
1391 } // for each value in the LV set after instruction
1395 //---------------------------------------------------------------------------
1396 // Copies %ccr into an integer register. IntReg is the UNIFIED register
1398 //---------------------------------------------------------------------------
1400 MachineInstr * UltraSparcRegInfo::cpCCR2IntMI(unsigned IntReg) const {
1401 MachineInstr * MI = new MachineInstr(RDCCR, 2);
1402 MI->SetMachineOperand(0, SparcIntCCRegOrder::ccr, false);
1403 MI->SetMachineOperand(1, IntReg, true);
1407 //---------------------------------------------------------------------------
1408 // Copies an integer register into %ccr. IntReg is the UNIFIED register
1410 //---------------------------------------------------------------------------
1412 MachineInstr *UltraSparcRegInfo::cpInt2CCRMI(unsigned IntReg) const {
1413 MachineInstr *MI = new MachineInstr(WRCCR, 3);
1414 MI->SetMachineOperand(0, IntReg, false);
1415 MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
1416 MI->SetMachineOperand(2, SparcIntCCRegOrder::ccr, true);
1423 //---------------------------------------------------------------------------
1424 // Print the register assigned to a LR
1425 //---------------------------------------------------------------------------
1427 void UltraSparcRegInfo::printReg(const LiveRange *LR) {
1428 unsigned RegClassID = (LR->getRegClass())->getID();
1429 cerr << " *Node " << (LR->getUserIGNode())->getIndex();
1431 if (!LR->hasColor()) {
1432 cerr << " - could not find a color\n";
1436 // if a color is found
1438 cerr << " colored with color "<< LR->getColor();
1440 if (RegClassID == IntRegClassID) {
1441 cerr<< " [" << SparcIntRegOrder::getRegName(LR->getColor()) << "]\n";
1443 } else if (RegClassID == FloatRegClassID) {
1444 cerr << "[" << SparcFloatRegOrder::getRegName(LR->getColor());
1445 if( LR->getType() == Type::DoubleTy)
1446 cerr << "+" << SparcFloatRegOrder::getRegName(LR->getColor()+1);
1451 //---------------------------------------------------------------------------
1452 // This method examines instructions inserted by RegAlloc code before a
1453 // machine instruction to detect invalid orders that destroy values before
1454 // they are used. If it detects such conditions, it reorders the instructions.
1456 // The unordered instructions come in the UnordVec. These instructions are
1457 // instructions inserted by RegAlloc. All such instruction MUST have
1458 // their USES BEFORE THE DEFS after reordering.
1460 // The UnordVec & OrdVec must be DISTINCT. The OrdVec must be empty when
1461 // this method is called.
1463 // This method uses two vectors for efficiency in accessing
1465 // Since instructions are inserted in RegAlloc, this assumes that the
1466 // first operand is the source reg and the last operand is the dest reg.
1468 // All the uses are before THE def to a register
1471 //---------------------------------------------------------------------------
1472 void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
1473 std::vector<MachineInstr *> &OrdVec,
1474 PhyRegAlloc &PRA) const{
1477 Problem: We can have instructions inserted by RegAlloc like
1479 2. add %oy %g0 %oz, where z!=x or z==x
1481 This is wrong since %oy used by 2 is overwritten by 1
1484 We re-order the instructions so that the uses are before the defs
1489 for each instruction 'DefInst' in the UnOrdVec
1490 for each instruction 'UseInst' that follows the DefInst
1491 if the reg defined by DefInst is used by UseInst
1492 mark DefInst as not movable in this iteration
1493 If DefInst is not marked as not-movable, move DefInst to OrdVec
1494 while all instructions in DefInst are moved to OrdVec
1496 For moving, we call the move2OrdVec(). It checks whether there is a def
1497 in it for the uses in the instruction to be added to OrdVec. If there
1498 are no preceding defs, it just appends the instruction. If there is a
1499 preceding def, it puts two instructions to save the reg on stack before
1500 the load and puts a restore at use.
1505 bool DebugPrint = false;
1508 CouldMoveAll = true;
1509 std::vector<MachineInstr *>::iterator DefIt = UnordVec.begin();
1511 for( ; DefIt != UnordVec.end(); ++DefIt ) {
1513 // for each instruction in the UnordVec do ...
1515 MachineInstr *DefInst = *DefIt;
1517 if( DefInst == NULL) continue;
1519 //cerr << "\nInst in UnordVec = " << *DefInst;
1521 // last operand is the def (unless for a store which has no def reg)
1522 MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
1524 if( DefOp.opIsDef() &&
1525 DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1527 // If the operand in DefInst is a def ...
1529 bool DefEqUse = false;
1531 std::vector<MachineInstr *>::iterator UseIt = DefIt;
1534 for( ; UseIt != UnordVec.end(); ++UseIt ) {
1536 MachineInstr *UseInst = *UseIt;
1537 if( UseInst == NULL) continue;
1539 // for each inst (UseInst) that is below the DefInst do ...
1540 MachineOperand& UseOp = UseInst->getOperand(0);
1542 if( ! UseOp.opIsDef() &&
1543 UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1545 // if use is a register ...
1547 if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
1549 // if Def and this use are the same, it means that this use
1550 // is destroyed by a def before it is used
1552 // cerr << "\nCouldn't move " << *DefInst;
1555 CouldMoveAll = false;
1558 } // if two registers are equal
1560 } // if use is a register
1562 }// for all use instructions
1566 // after examining all the instructions that follow the DefInst
1567 // if there are no dependencies, we can move it to the OrdVec
1569 // cerr << "Moved to Ord: " << *DefInst;
1571 moveInst2OrdVec(OrdVec, DefInst, PRA);
1573 //OrdVec.push_back(DefInst);
1575 // mark the pos of DefInst with NULL to indicate that it is
1580 } // if Def is a machine register
1582 } // for all instructions in the UnordVec
1585 } while(!CouldMoveAll);
1588 cerr << "\nAdded instructions were reordered to:\n";
1589 for(unsigned int i=0; i < OrdVec.size(); i++)
1590 cerr << *(OrdVec[i]);
1598 void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
1599 MachineInstr *UnordInst,
1600 PhyRegAlloc &PRA) const {
1601 MachineOperand& UseOp = UnordInst->getOperand(0);
1603 if( ! UseOp.opIsDef() &&
1604 UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1606 // for the use of UnordInst, see whether there is a defining instr
1607 // before in the OrdVec
1608 bool DefEqUse = false;
1610 std::vector<MachineInstr *>::iterator OrdIt = OrdVec.begin();
1612 for( ; OrdIt != OrdVec.end(); ++OrdIt ) {
1614 MachineInstr *OrdInst = *OrdIt ;
1616 MachineOperand& DefOp =
1617 OrdInst->getOperand(OrdInst->getNumOperands()-1);
1619 if( DefOp.opIsDef() &&
1620 DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1622 //cerr << "\nDefining Ord Inst: " << *OrdInst;
1624 if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
1626 // we are here because there is a preceding def in the OrdVec
1627 // for the use in this intr we are going to insert. This
1628 // happened because the original code was like:
1629 // 1. add %ox %g0 %oy
1630 // 2. add %oy %g0 %ox
1631 // In Round1, we added 2 to OrdVec but 1 remained in UnordVec
1632 // Now we are processing %ox of 1.
1635 const int UReg = DefOp.getMachineRegNum();
1636 const int RegType = getRegType(UReg);
1637 MachineInstr *AdIBef, *AdIAft;
1639 const int StackOff = PRA.mcInfo.pushTempValue(target,
1640 getSpilledRegSize(RegType));
1642 // Save the UReg (%ox) on stack before it's destroyed
1643 AdIBef=cpReg2MemMI(UReg, getFramePointer(), StackOff, RegType);
1644 OrdIt = OrdVec.insert( OrdIt, AdIBef);
1645 OrdIt++; // points to current instr we processed
1647 // Load directly into DReg (%oy)
1648 MachineOperand& DOp=
1649 (UnordInst->getOperand(UnordInst->getNumOperands()-1));
1650 assert(DOp.opIsDef() && "Last operand is not the def");
1651 const int DReg = DOp.getMachineRegNum();
1653 AdIAft=cpMem2RegMI(getFramePointer(), StackOff, DReg, RegType);
1654 OrdVec.push_back(AdIAft);
1656 cerr << "\nFixed CIRCULAR references by reordering";
1659 cerr << "\nBefore CIRCULAR Reordering:\n";
1663 cerr << "\nAfter CIRCULAR Reordering - All Inst so far:\n";
1664 for(unsigned i=0; i < OrdVec.size(); i++)
1665 cerr << *(OrdVec[i]);
1668 // Do not copy the UseInst to OrdVec
1672 }// if two registers are equal
1674 } // if Def is a register
1676 } // for each instr in OrdVec
1680 // We didn't find a def in the OrdVec, so just append this inst
1681 OrdVec.push_back( UnordInst );
1682 //cerr << "Reordered Inst (Moved Dn): " << *UnordInst;
1685 }// if the operand in UnordInst is a use