1 //===-- SparcV9RegInfo.cpp - SparcV9 Target Register Information ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains implementations of SparcV9 specific helper methods
11 // used for register allocation.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineCodeForInstruction.h"
19 #include "MachineInstrAnnot.h"
20 #include "RegAlloc/LiveRangeInfo.h"
21 #include "RegAlloc/LiveRange.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/Instructions.h"
25 #include "SparcV9Internals.h"
26 #include "SparcV9RegClassInfo.h"
27 #include "SparcV9RegInfo.h"
28 #include "SparcV9TargetMachine.h"
29 #include "SparcV9TmpInstr.h"
38 SparcV9RegInfo::SparcV9RegInfo(const SparcV9TargetMachine &tgt)
39 : target (tgt), NumOfIntArgRegs (6), NumOfFloatArgRegs (32)
41 MachineRegClassArr.push_back(new SparcV9IntRegClass(IntRegClassID));
42 MachineRegClassArr.push_back(new SparcV9FloatRegClass(FloatRegClassID));
43 MachineRegClassArr.push_back(new SparcV9IntCCRegClass(IntCCRegClassID));
44 MachineRegClassArr.push_back(new SparcV9FloatCCRegClass(FloatCCRegClassID));
45 MachineRegClassArr.push_back(new SparcV9SpecialRegClass(SpecialRegClassID));
47 assert(SparcV9FloatRegClass::StartOfNonVolatileRegs == 32 &&
48 "32 Float regs are used for float arg passing");
52 // getZeroRegNum - returns the register that contains always zero.
53 // this is the unified register number
55 unsigned SparcV9RegInfo::getZeroRegNum() const {
56 return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
57 SparcV9IntRegClass::g0);
60 // getCallAddressReg - returns the reg used for pushing the address when a
61 // method is called. This can be used for other purposes between calls
63 unsigned SparcV9RegInfo::getCallAddressReg() const {
64 return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
65 SparcV9IntRegClass::o7);
68 // Returns the register containing the return address.
69 // It should be made sure that this register contains the return
70 // value when a return instruction is reached.
72 unsigned SparcV9RegInfo::getReturnAddressReg() const {
73 return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
74 SparcV9IntRegClass::i7);
77 // Register get name implementations...
79 // Int register names in same order as enum in class SparcV9IntRegClass
80 static const char * const IntRegNames[] = {
81 "o0", "o1", "o2", "o3", "o4", "o5", "o7",
82 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
83 "i0", "i1", "i2", "i3", "i4", "i5",
85 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
89 const char * const SparcV9IntRegClass::getRegName(unsigned reg) const {
90 assert(reg < NumOfAllRegs);
91 return IntRegNames[reg];
94 static const char * const FloatRegNames[] = {
95 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
96 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
97 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
98 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
99 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
100 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
101 "f60", "f61", "f62", "f63"
104 const char * const SparcV9FloatRegClass::getRegName(unsigned reg) const {
105 assert (reg < NumOfAllRegs);
106 return FloatRegNames[reg];
109 static const char * const IntCCRegNames[] = {
113 const char * const SparcV9IntCCRegClass::getRegName(unsigned reg) const {
115 return IntCCRegNames[reg];
118 static const char * const FloatCCRegNames[] = {
119 "fcc0", "fcc1", "fcc2", "fcc3"
122 const char * const SparcV9FloatCCRegClass::getRegName(unsigned reg) const {
124 return FloatCCRegNames[reg];
127 static const char * const SpecialRegNames[] = {
131 const char * const SparcV9SpecialRegClass::getRegName(unsigned reg) const {
133 return SpecialRegNames[reg];
136 // Get unified reg number for frame pointer
137 unsigned SparcV9RegInfo::getFramePointer() const {
138 return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
139 SparcV9IntRegClass::i6);
142 // Get unified reg number for stack pointer
143 unsigned SparcV9RegInfo::getStackPointer() const {
144 return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
145 SparcV9IntRegClass::o6);
149 //---------------------------------------------------------------------------
150 // Finds whether a call is an indirect call
151 //---------------------------------------------------------------------------
154 isVarArgsFunction(const Type *funcType) {
155 return cast<FunctionType>(cast<PointerType>(funcType)
156 ->getElementType())->isVarArg();
160 isVarArgsCall(const MachineInstr *CallMI) {
161 Value* callee = CallMI->getOperand(0).getVRegValue();
162 // const Type* funcType = isa<Function>(callee)? callee->getType()
163 // : cast<PointerType>(callee->getType())->getElementType();
164 const Type* funcType = callee->getType();
165 return isVarArgsFunction(funcType);
169 // Get the register number for the specified argument #argNo,
172 // getInvalidRegNum(), if there is no int register available for the arg.
173 // regNum, otherwise (this is NOT the unified reg. num).
174 // regClassId is set to the register class ID.
177 SparcV9RegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall,
178 unsigned argNo, unsigned& regClassId) const
180 regClassId = IntRegClassID;
181 if (argNo >= NumOfIntArgRegs)
182 return getInvalidRegNum();
184 return argNo + (inCallee? SparcV9IntRegClass::i0 : SparcV9IntRegClass::o0);
187 // Get the register number for the specified FP argument #argNo,
188 // Use INT regs for FP args if this is a varargs call.
191 // getInvalidRegNum(), if there is no int register available for the arg.
192 // regNum, otherwise (this is NOT the unified reg. num).
193 // regClassId is set to the register class ID.
196 SparcV9RegInfo::regNumForFPArg(unsigned regType,
197 bool inCallee, bool isVarArgsCall,
198 unsigned argNo, unsigned& regClassId) const
201 return regNumForIntArg(inCallee, isVarArgsCall, argNo, regClassId);
204 regClassId = FloatRegClassID;
205 if (regType == FPSingleRegType)
206 return (argNo*2+1 >= NumOfFloatArgRegs)?
207 getInvalidRegNum() : SparcV9FloatRegClass::f0 + (argNo * 2 + 1);
208 else if (regType == FPDoubleRegType)
209 return (argNo*2 >= NumOfFloatArgRegs)?
210 getInvalidRegNum() : SparcV9FloatRegClass::f0 + (argNo * 2);
212 assert(0 && "Illegal FP register type");
218 //---------------------------------------------------------------------------
219 // Finds the return address of a call sparc specific call instruction
220 //---------------------------------------------------------------------------
222 // The following 4 methods are used to find the RegType (SparcV9Internals.h)
223 // of a LiveRange, a Value, and for a given register unified reg number.
225 int SparcV9RegInfo::getRegTypeForClassAndType(unsigned regClassID,
226 const Type* type) const
228 switch (regClassID) {
229 case IntRegClassID: return IntRegType;
230 case FloatRegClassID:
231 if (type == Type::FloatTy) return FPSingleRegType;
232 else if (type == Type::DoubleTy) return FPDoubleRegType;
233 assert(0 && "Unknown type in FloatRegClass"); return 0;
234 case IntCCRegClassID: return IntCCRegType;
235 case FloatCCRegClassID: return FloatCCRegType;
236 case SpecialRegClassID: return SpecialRegType;
237 default: assert( 0 && "Unknown reg class ID"); return 0;
241 int SparcV9RegInfo::getRegTypeForDataType(const Type* type) const
243 return getRegTypeForClassAndType(getRegClassIDOfType(type), type);
246 int SparcV9RegInfo::getRegTypeForLR(const LiveRange *LR) const
248 return getRegTypeForClassAndType(LR->getRegClassID(), LR->getType());
251 int SparcV9RegInfo::getRegType(int unifiedRegNum) const
253 if (unifiedRegNum < 32)
255 else if (unifiedRegNum < (32 + 32))
256 return FPSingleRegType;
257 else if (unifiedRegNum < (64 + 32))
258 return FPDoubleRegType;
259 else if (unifiedRegNum < (64+32+3))
261 else if (unifiedRegNum < (64+32+3+4))
262 return FloatCCRegType;
263 else if (unifiedRegNum < (64+32+3+4+1))
264 return SpecialRegType;
266 assert(0 && "Invalid unified register number in getRegType");
271 // To find the register class used for a specified Type
273 unsigned SparcV9RegInfo::getRegClassIDOfType(const Type *type,
274 bool isCCReg) const {
275 Type::TypeID ty = type->getTypeID();
278 // FIXME: Comparing types like this isn't very safe...
279 if ((ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
280 (ty == Type::FunctionTyID) || (ty == Type::PointerTyID) )
281 res = IntRegClassID; // sparc int reg (ty=0: void)
282 else if (ty <= Type::DoubleTyID)
283 res = FloatRegClassID; // sparc float reg class
285 //std::cerr << "TypeID: " << ty << "\n";
286 assert(0 && "Cannot resolve register class for type");
291 return res + 2; // corresponding condition code register
296 unsigned SparcV9RegInfo::getRegClassIDOfRegType(int regType) const {
298 case IntRegType: return IntRegClassID;
299 case FPSingleRegType:
300 case FPDoubleRegType: return FloatRegClassID;
301 case IntCCRegType: return IntCCRegClassID;
302 case FloatCCRegType: return FloatCCRegClassID;
303 case SpecialRegType: return SpecialRegClassID;
305 assert(0 && "Invalid register type in getRegClassIDOfRegType");
310 //---------------------------------------------------------------------------
311 // Suggests a register for the ret address in the RET machine instruction.
312 // We always suggest %i7 by convention.
313 //---------------------------------------------------------------------------
314 void SparcV9RegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
315 LiveRangeInfo& LRI) const {
317 assert(target.getInstrInfo()->isReturn(RetMI->getOpcode()));
319 // return address is always mapped to i7 so set it immediately
320 RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID,
321 SparcV9IntRegClass::i7));
323 // Possible Optimization:
324 // Instead of setting the color, we can suggest one. In that case,
325 // we have to test later whether it received the suggested color.
326 // In that case, a LR has to be created at the start of method.
327 // It has to be done as follows (remove the setRegVal above):
329 // MachineOperand & MO = RetMI->getOperand(0);
330 // const Value *RetAddrVal = MO.getVRegValue();
331 // assert( RetAddrVal && "LR for ret address must be created at start");
332 // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
333 // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
334 // SparcV9IntRegOrdr::i7) );
338 //---------------------------------------------------------------------------
339 // Suggests a register for the ret address in the JMPL/CALL machine instr.
340 // SparcV9 ABI dictates that %o7 be used for this purpose.
341 //---------------------------------------------------------------------------
343 SparcV9RegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
344 LiveRangeInfo& LRI) const
346 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
347 const Value *RetAddrVal = argDesc->getReturnAddrReg();
348 assert(RetAddrVal && "INTERNAL ERROR: Return address value is required");
350 // A LR must already exist for the return address.
351 LiveRange *RetAddrLR = LRI.getLiveRangeForValue(RetAddrVal);
352 assert(RetAddrLR && "INTERNAL ERROR: No LR for return address of call!");
354 unsigned RegClassID = RetAddrLR->getRegClassID();
355 RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID, SparcV9IntRegClass::o7));
360 //---------------------------------------------------------------------------
361 // This method will suggest colors to incoming args to a method.
362 // According to the SparcV9 ABI, the first 6 incoming args are in
363 // %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float).
364 // If the arg is passed on stack due to the lack of regs, NOTHING will be
365 // done - it will be colored (or spilled) as a normal live range.
366 //---------------------------------------------------------------------------
367 void SparcV9RegInfo::suggestRegs4MethodArgs(const Function *Meth,
368 LiveRangeInfo& LRI) const
370 // Check if this is a varArgs function. needed for choosing regs.
371 bool isVarArgs = isVarArgsFunction(Meth->getType());
373 // Count the arguments, *ignoring* whether they are int or FP args.
374 // Use this common arg numbering to pick the right int or fp register.
376 for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend();
377 I != E; ++I, ++argNo) {
378 LiveRange *LR = LRI.getLiveRangeForValue(I);
379 assert(LR && "No live range found for method arg");
381 unsigned regType = getRegTypeForLR(LR);
382 unsigned regClassIDOfArgReg = BadRegClass; // for chosen reg (unused)
384 int regNum = (regType == IntRegType)
385 ? regNumForIntArg(/*inCallee*/ true, isVarArgs, argNo, regClassIDOfArgReg)
386 : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs, argNo,
389 if (regNum != getInvalidRegNum())
390 LR->setSuggestedColor(regNum);
395 //---------------------------------------------------------------------------
396 // This method is called after graph coloring to move incoming args to
397 // the correct hardware registers if they did not receive the correct
398 // (suggested) color through graph coloring.
399 //---------------------------------------------------------------------------
400 void SparcV9RegInfo::colorMethodArgs(const Function *Meth,
402 std::vector<MachineInstr*>& InstrnsBefore,
403 std::vector<MachineInstr*>& InstrnsAfter) const {
405 // check if this is a varArgs function. needed for choosing regs.
406 bool isVarArgs = isVarArgsFunction(Meth->getType());
410 // for each argument. count INT and FP arguments separately.
411 unsigned argNo=0, intArgNo=0, fpArgNo=0;
412 for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend();
413 I != E; ++I, ++argNo) {
415 LiveRange *LR = LRI.getLiveRangeForValue(I);
416 assert( LR && "No live range found for method arg");
418 unsigned regType = getRegTypeForLR(LR);
419 unsigned RegClassID = LR->getRegClassID();
421 // Find whether this argument is coming in a register (if not, on stack)
422 // Also find the correct register the argument must use (UniArgReg)
424 bool isArgInReg = false;
425 unsigned UniArgReg = getInvalidRegNum(); // reg that LR MUST be colored with
426 unsigned regClassIDOfArgReg = BadRegClass; // reg class of chosen reg
428 int regNum = (regType == IntRegType)
429 ? regNumForIntArg(/*inCallee*/ true, isVarArgs,
430 argNo, regClassIDOfArgReg)
431 : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs,
432 argNo, regClassIDOfArgReg);
434 if(regNum != getInvalidRegNum()) {
436 UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum);
439 if( ! LR->isMarkedForSpill() ) { // if this arg received a register
441 unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
443 // if LR received the correct color, nothing to do
445 if( UniLRReg == UniArgReg )
448 // We are here because the LR did not receive the suggested
449 // but LR received another register.
450 // Now we have to copy the %i reg (or stack pos of arg)
451 // to the register the LR was colored with.
453 // if the arg is coming in UniArgReg register, it MUST go into
454 // the UniLRReg register
457 if( regClassIDOfArgReg != RegClassID ) {
458 assert(0 && "This could should work but it is not tested yet");
460 // It is a variable argument call: the float reg must go in a %o reg.
461 // We have to move an int reg to a float reg via memory.
464 RegClassID == FloatRegClassID &&
465 regClassIDOfArgReg == IntRegClassID &&
466 "This should only be an Int register for an FP argument");
468 int TmpOff = MachineFunction::get(Meth).getInfo()->pushTempValue(
469 getSpilledRegSize(regType));
470 cpReg2MemMI(InstrnsBefore,
471 UniArgReg, getFramePointer(), TmpOff, IntRegType);
473 cpMem2RegMI(InstrnsBefore,
474 getFramePointer(), TmpOff, UniLRReg, regType);
477 cpReg2RegMI(InstrnsBefore, UniArgReg, UniLRReg, regType);
482 // Now the arg is coming on stack. Since the LR received a register,
483 // we just have to load the arg on stack into that register
485 const TargetFrameInfo& frameInfo = *target.getFrameInfo();
487 frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
490 // float arguments on stack are right justified so adjust the offset!
491 // int arguments are also right justified but they are always loaded as
492 // a full double-word so the offset does not need to be adjusted.
493 if (regType == FPSingleRegType) {
494 unsigned argSize = target.getTargetData().getTypeSize(LR->getType());
495 unsigned slotSize = frameInfo.getSizeOfEachArgOnStack();
496 assert(argSize <= slotSize && "Insufficient slot size!");
497 offsetFromFP += slotSize - argSize;
500 cpMem2RegMI(InstrnsBefore,
501 getFramePointer(), offsetFromFP, UniLRReg, regType);
504 } // if LR received a color
508 // Now, the LR did not receive a color. But it has a stack offset for
510 // So, if the arg is coming in UniArgReg register, we can just move
511 // that on to the stack pos of LR
515 if( regClassIDOfArgReg != RegClassID ) {
517 "FP arguments to a varargs function should be explicitly "
518 "copied to/from int registers by instruction selection!");
520 // It must be a float arg for a variable argument call, which
521 // must come in a %o reg. Move the int reg to the stack.
523 assert(isVarArgs && regClassIDOfArgReg == IntRegClassID &&
524 "This should only be an Int register for an FP argument");
526 cpReg2MemMI(InstrnsBefore, UniArgReg,
527 getFramePointer(), LR->getSpillOffFromFP(), IntRegType);
530 cpReg2MemMI(InstrnsBefore, UniArgReg,
531 getFramePointer(), LR->getSpillOffFromFP(), regType);
537 // Now the arg is coming on stack. Since the LR did NOT
538 // received a register as well, it is allocated a stack position. We
539 // can simply change the stack position of the LR. We can do this,
540 // since this method is called before any other method that makes
541 // uses of the stack pos of the LR (e.g., updateMachineInstr)
543 const TargetFrameInfo& frameInfo = *target.getFrameInfo();
545 frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
548 // FP arguments on stack are right justified so adjust offset!
549 // int arguments are also right justified but they are always loaded as
550 // a full double-word so the offset does not need to be adjusted.
551 if (regType == FPSingleRegType) {
552 unsigned argSize = target.getTargetData().getTypeSize(LR->getType());
553 unsigned slotSize = frameInfo.getSizeOfEachArgOnStack();
554 assert(argSize <= slotSize && "Insufficient slot size!");
555 offsetFromFP += slotSize - argSize;
558 LR->modifySpillOffFromFP( offsetFromFP );
563 } // for each incoming argument
569 //---------------------------------------------------------------------------
570 // This method is called before graph coloring to suggest colors to the
571 // outgoing call args and the return value of the call.
572 //---------------------------------------------------------------------------
573 void SparcV9RegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
574 LiveRangeInfo& LRI) const {
575 assert ( (target.getInstrInfo())->isCall(CallMI->getOpcode()) );
577 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
579 suggestReg4CallAddr(CallMI, LRI);
581 // First color the return value of the call instruction, if any.
582 // The return value will be in %o0 if the value is an integer type,
583 // or in %f0 if the value is a float type.
585 if (const Value *RetVal = argDesc->getReturnValue()) {
586 LiveRange *RetValLR = LRI.getLiveRangeForValue(RetVal);
587 assert(RetValLR && "No LR for return Value of call!");
589 unsigned RegClassID = RetValLR->getRegClassID();
591 // now suggest a register depending on the register class of ret arg
592 if( RegClassID == IntRegClassID )
593 RetValLR->setSuggestedColor(SparcV9IntRegClass::o0);
594 else if (RegClassID == FloatRegClassID )
595 RetValLR->setSuggestedColor(SparcV9FloatRegClass::f0 );
596 else assert( 0 && "Unknown reg class for return value of call\n");
599 // Now suggest colors for arguments (operands) of the call instruction.
600 // Colors are suggested only if the arg number is smaller than the
601 // the number of registers allocated for argument passing.
602 // Now, go thru call args - implicit operands of the call MI
604 unsigned NumOfCallArgs = argDesc->getNumArgs();
606 for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0;
607 i < NumOfCallArgs; ++i, ++argNo) {
609 const Value *CallArg = argDesc->getArgInfo(i).getArgVal();
611 // get the LR of call operand (parameter)
612 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
614 continue; // no live ranges for constants and labels
616 unsigned regType = getRegTypeForLR(LR);
617 unsigned regClassIDOfArgReg = BadRegClass; // chosen reg class (unused)
619 // Choose a register for this arg depending on whether it is
620 // an INT or FP value. Here we ignore whether or not it is a
621 // varargs calls, because FP arguments will be explicitly copied
622 // to an integer Value and handled under (argCopy != NULL) below.
623 int regNum = (regType == IntRegType)
624 ? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false,
625 argNo, regClassIDOfArgReg)
626 : regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false,
627 argNo, regClassIDOfArgReg);
629 // If a register could be allocated, use it.
630 // If not, do NOTHING as this will be colored as a normal value.
631 if(regNum != getInvalidRegNum())
632 LR->setSuggestedColor(regNum);
633 } // for all call arguments
637 //---------------------------------------------------------------------------
638 // this method is called for an LLVM return instruction to identify which
639 // values will be returned from this method and to suggest colors.
640 //---------------------------------------------------------------------------
641 void SparcV9RegInfo::suggestReg4RetValue(MachineInstr *RetMI,
642 LiveRangeInfo& LRI) const {
644 assert( target.getInstrInfo()->isReturn( RetMI->getOpcode() ) );
646 suggestReg4RetAddr(RetMI, LRI);
648 // To find the return value (if any), we can get the LLVM return instr.
649 // from the return address register, which is the first operand
650 Value* tmpI = RetMI->getOperand(0).getVRegValue();
651 ReturnInst* retI=cast<ReturnInst>(cast<TmpInstruction>(tmpI)->getOperand(0));
652 if (const Value *RetVal = retI->getReturnValue())
653 if (LiveRange *const LR = LRI.getLiveRangeForValue(RetVal))
654 LR->setSuggestedColor(LR->getRegClassID() == IntRegClassID
655 ? (unsigned) SparcV9IntRegClass::i0
656 : (unsigned) SparcV9FloatRegClass::f0);
659 //---------------------------------------------------------------------------
660 // Check if a specified register type needs a scratch register to be
661 // copied to/from memory. If it does, the reg. type that must be used
662 // for scratch registers is returned in scratchRegType.
664 // Only the int CC register needs such a scratch register.
665 // The FP CC registers can (and must) be copied directly to/from memory.
666 //---------------------------------------------------------------------------
669 SparcV9RegInfo::regTypeNeedsScratchReg(int RegType,
670 int& scratchRegType) const
672 if (RegType == IntCCRegType)
674 scratchRegType = IntRegType;
680 //---------------------------------------------------------------------------
681 // Copy from a register to register. Register number must be the unified
683 //---------------------------------------------------------------------------
686 SparcV9RegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
690 assert( ((int)SrcReg != getInvalidRegNum()) &&
691 ((int)DestReg != getInvalidRegNum()) &&
694 MachineInstr * MI = NULL;
699 if (getRegType(DestReg) == IntRegType) {
700 // copy intCC reg to int reg
701 MI = (BuildMI(V9::RDCCR, 2)
702 .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
703 SparcV9IntCCRegClass::ccr))
704 .addMReg(DestReg,MachineOperand::Def));
706 // copy int reg to intCC reg
707 assert(getRegType(SrcReg) == IntRegType
708 && "Can only copy CC reg to/from integer reg");
709 MI = (BuildMI(V9::WRCCRr, 3)
711 .addMReg(SparcV9IntRegClass::g0)
712 .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
713 SparcV9IntCCRegClass::ccr),
714 MachineOperand::Def));
719 assert(0 && "Cannot copy FPCC register to any other register");
723 MI = BuildMI(V9::ADDr, 3).addMReg(SrcReg).addMReg(getZeroRegNum())
724 .addMReg(DestReg, MachineOperand::Def);
727 case FPSingleRegType:
728 MI = BuildMI(V9::FMOVS, 2).addMReg(SrcReg)
729 .addMReg(DestReg, MachineOperand::Def);
732 case FPDoubleRegType:
733 MI = BuildMI(V9::FMOVD, 2).addMReg(SrcReg)
734 .addMReg(DestReg, MachineOperand::Def);
738 assert(0 && "Unknown RegType");
746 //---------------------------------------------------------------------------
747 // Copy from a register to memory (i.e., Store). Register number must
748 // be the unified register number
749 //---------------------------------------------------------------------------
753 SparcV9RegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
756 int Offset, int RegType,
757 int scratchReg) const {
758 MachineInstr * MI = NULL;
761 // If the Offset will not fit in the signed-immediate field, find an
762 // unused register to hold the offset value. This takes advantage of
763 // the fact that all the opcodes used below have the same size immed. field.
764 // Use the register allocator, PRA, to find an unused reg. at this MI.
766 if (RegType != IntCCRegType) // does not use offset below
767 if (! target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) {
768 #ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY
769 RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
770 OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
772 // Default to using register g4 for holding large offsets
773 OffReg = getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
774 SparcV9IntRegClass::g4);
776 assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg.");
777 mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg));
782 if (target.getInstrInfo()->constantFitsInImmedField(V9::STXi, Offset))
783 MI = BuildMI(V9::STXi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
785 MI = BuildMI(V9::STXr,3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg);
788 case FPSingleRegType:
789 if (target.getInstrInfo()->constantFitsInImmedField(V9::STFi, Offset))
790 MI = BuildMI(V9::STFi, 3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
792 MI = BuildMI(V9::STFr, 3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg);
795 case FPDoubleRegType:
796 if (target.getInstrInfo()->constantFitsInImmedField(V9::STDFi, Offset))
797 MI = BuildMI(V9::STDFi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
799 MI = BuildMI(V9::STDFr,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(OffReg);
803 assert(scratchReg >= 0 && "Need scratch reg to store %ccr to memory");
804 assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
805 MI = (BuildMI(V9::RDCCR, 2)
806 .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
807 SparcV9IntCCRegClass::ccr))
808 .addMReg(scratchReg, MachineOperand::Def));
811 cpReg2MemMI(mvec, scratchReg, PtrReg, Offset, IntRegType);
814 case SpecialRegType: // used only for %fsr itself.
815 case FloatCCRegType: {
816 unsigned fsrReg = getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID,
817 SparcV9SpecialRegClass::fsr);
818 if (target.getInstrInfo()->constantFitsInImmedField(V9::STXFSRi, Offset))
819 MI=BuildMI(V9::STXFSRi,3).addMReg(fsrReg).addMReg(PtrReg).addSImm(Offset);
821 MI=BuildMI(V9::STXFSRr,3).addMReg(fsrReg).addMReg(PtrReg).addMReg(OffReg);
825 assert(0 && "Unknown RegType in cpReg2MemMI");
831 //---------------------------------------------------------------------------
832 // Copy from memory to a reg (i.e., Load) Register number must be the unified
834 //---------------------------------------------------------------------------
838 SparcV9RegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
843 int scratchReg) const {
844 MachineInstr * MI = NULL;
847 // If the Offset will not fit in the signed-immediate field, find an
848 // unused register to hold the offset value. This takes advantage of
849 // the fact that all the opcodes used below have the same size immed. field.
850 // Use the register allocator, PRA, to find an unused reg. at this MI.
852 if (RegType != IntCCRegType) // does not use offset below
853 if (! target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) {
854 #ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY
855 RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
856 OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
858 // Default to using register g4 for holding large offsets
859 OffReg = getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
860 SparcV9IntRegClass::g4);
862 assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg.");
863 mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg));
868 if (target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset))
869 MI = BuildMI(V9::LDXi, 3).addMReg(PtrReg).addSImm(Offset)
870 .addMReg(DestReg, MachineOperand::Def);
872 MI = BuildMI(V9::LDXr, 3).addMReg(PtrReg).addMReg(OffReg)
873 .addMReg(DestReg, MachineOperand::Def);
876 case FPSingleRegType:
877 if (target.getInstrInfo()->constantFitsInImmedField(V9::LDFi, Offset))
878 MI = BuildMI(V9::LDFi, 3).addMReg(PtrReg).addSImm(Offset)
879 .addMReg(DestReg, MachineOperand::Def);
881 MI = BuildMI(V9::LDFr, 3).addMReg(PtrReg).addMReg(OffReg)
882 .addMReg(DestReg, MachineOperand::Def);
885 case FPDoubleRegType:
886 if (target.getInstrInfo()->constantFitsInImmedField(V9::LDDFi, Offset))
887 MI= BuildMI(V9::LDDFi, 3).addMReg(PtrReg).addSImm(Offset)
888 .addMReg(DestReg, MachineOperand::Def);
890 MI= BuildMI(V9::LDDFr, 3).addMReg(PtrReg).addMReg(OffReg)
891 .addMReg(DestReg, MachineOperand::Def);
895 assert(scratchReg >= 0 && "Need scratch reg to load %ccr from memory");
896 assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
897 cpMem2RegMI(mvec, PtrReg, Offset, scratchReg, IntRegType);
898 MI = (BuildMI(V9::WRCCRr, 3)
900 .addMReg(SparcV9IntRegClass::g0)
901 .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
902 SparcV9IntCCRegClass::ccr), MachineOperand::Def));
905 case SpecialRegType: // used only for %fsr itself
906 case FloatCCRegType: {
907 unsigned fsrRegNum = getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID,
908 SparcV9SpecialRegClass::fsr);
909 if (target.getInstrInfo()->constantFitsInImmedField(V9::LDXFSRi, Offset))
910 MI = BuildMI(V9::LDXFSRi, 3).addMReg(PtrReg).addSImm(Offset)
911 .addMReg(fsrRegNum, MachineOperand::UseAndDef);
913 MI = BuildMI(V9::LDXFSRr, 3).addMReg(PtrReg).addMReg(OffReg)
914 .addMReg(fsrRegNum, MachineOperand::UseAndDef);
918 assert(0 && "Unknown RegType in cpMem2RegMI");
924 //---------------------------------------------------------------------------
925 // Generate a copy instruction to copy a value to another. Temporarily
926 // used by PhiElimination code.
927 //---------------------------------------------------------------------------
931 SparcV9RegInfo::cpValue2Value(Value *Src, Value *Dest,
932 std::vector<MachineInstr*>& mvec) const {
933 int RegType = getRegTypeForDataType(Src->getType());
934 MachineInstr * MI = NULL;
938 MI = BuildMI(V9::ADDr, 3).addReg(Src).addMReg(getZeroRegNum())
941 case FPSingleRegType:
942 MI = BuildMI(V9::FMOVS, 2).addReg(Src).addRegDef(Dest);
944 case FPDoubleRegType:
945 MI = BuildMI(V9::FMOVD, 2).addReg(Src).addRegDef(Dest);
948 assert(0 && "Unknown RegType in cpValue2Value");
956 //---------------------------------------------------------------------------
957 // Print the register assigned to a LR
958 //---------------------------------------------------------------------------
960 void SparcV9RegInfo::printReg(const LiveRange *LR) const {
961 unsigned RegClassID = LR->getRegClassID();
962 std::cerr << " Node ";
964 if (!LR->hasColor()) {
965 std::cerr << " - could not find a color\n";
969 // if a color is found
971 std::cerr << " colored with color "<< LR->getColor();
973 unsigned uRegName = getUnifiedRegNum(RegClassID, LR->getColor());
976 std::cerr<< getUnifiedRegName(uRegName);
977 if (RegClassID == FloatRegClassID && LR->getType() == Type::DoubleTy)
978 std::cerr << "+" << getUnifiedRegName(uRegName+1);
982 } // End llvm namespace