1 #include "llvm/Target/Sparc.h"
2 #include "SparcInternals.h"
3 #include "llvm/Method.h"
4 #include "llvm/iTerminators.h"
5 #include "llvm/iOther.h"
6 #include "llvm/CodeGen/InstrScheduling.h"
7 #include "llvm/CodeGen/InstrSelection.h"
9 #include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h"
10 #include "llvm/CodeGen/PhyRegAlloc.h"
15 //---------------------------------------------------------------------------
17 //---------------------------------------------------------------------------
19 //---------------------------------------------------------------------------
20 // Finds the return value of a call instruction
21 //---------------------------------------------------------------------------
24 UltraSparcRegInfo::getCallInstRetVal(const MachineInstr *CallMI) const{
26 unsigned OpCode = CallMI->getOpCode();
27 unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
29 if( OpCode == CALL ) {
31 // The one before the last implicit operand is the return value of
33 if( NumOfImpRefs > 1 )
34 if( CallMI->implicitRefIsDefined(NumOfImpRefs-2) )
35 return CallMI->getImplicitRef(NumOfImpRefs-2);
38 else if( OpCode == JMPLCALL) {
40 // The last implicit operand is the return value of a JMPL in
41 if( NumOfImpRefs > 0 )
42 if( CallMI->implicitRefIsDefined(NumOfImpRefs-1) )
43 return CallMI->getImplicitRef(NumOfImpRefs-1);
46 assert(0 && "OpCode must be CALL/JMPL for a call instr");
52 //---------------------------------------------------------------------------
53 // Finds the return address of a call instruction
54 //---------------------------------------------------------------------------
57 UltraSparcRegInfo::getCallInstRetAddr(const MachineInstr *CallMI)const {
59 unsigned OpCode = CallMI->getOpCode();
63 unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
65 assert( NumOfImpRefs && "CALL instr must have at least on ImpRef");
66 // The last implicit operand is the return address of a CALL instr
67 return CallMI->getImplicitRef(NumOfImpRefs-1);
70 else if( OpCode == JMPLCALL ) {
72 MachineOperand & MO = ( MachineOperand &) CallMI->getOperand(2);
73 return MO.getVRegValue();
77 assert(0 && "OpCode must be CALL/JMPL for a call instr");
79 assert(0 && "There must be a return addr for a call instr");
86 //---------------------------------------------------------------------------
87 // Finds the # of actual arguments of the call instruction
88 //---------------------------------------------------------------------------
91 UltraSparcRegInfo::getCallInstNumArgs(const MachineInstr *CallMI) const {
93 unsigned OpCode = CallMI->getOpCode();
94 unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
97 if( OpCode == CALL ) {
99 switch( NumOfImpRefs ) {
101 case 0: assert(0 && "A CALL inst must have at least one ImpRef (RetAddr)");
106 default: // two or more implicit refs
107 if( CallMI->implicitRefIsDefined(NumOfImpRefs-2) )
108 NumArgs = NumOfImpRefs - 2; // i.e., NumOfImpRef-2 is the ret val
110 NumArgs = NumOfImpRefs - 1;
114 else if( OpCode == JMPLCALL ) {
116 // The last implicit operand is the return value of a JMPL instr
117 if( NumOfImpRefs > 0 ) {
118 if( CallMI->implicitRefIsDefined(NumOfImpRefs-1) )
119 NumArgs = NumOfImpRefs - 1; // i.e., NumOfImpRef-1 is the ret val
121 NumArgs = NumOfImpRefs;
124 NumArgs = NumOfImpRefs;
127 assert(0 && "OpCode must be CALL/JMPL for a call instr");
129 assert( (NumArgs != -1) && "Internal error in getCallInstNumArgs" );
130 return (unsigned) NumArgs;
136 //---------------------------------------------------------------------------
137 // Suggests a register for the ret address in the RET machine instruction
138 //---------------------------------------------------------------------------
140 void UltraSparcRegInfo::suggestReg4RetAddr(const MachineInstr * RetMI,
141 LiveRangeInfo& LRI) const {
143 assert( (RetMI->getNumOperands() >= 2)
144 && "JMPL/RETURN must have 3 and 2 operands respectively");
146 MachineOperand & MO = ( MachineOperand &) RetMI->getOperand(0);
148 MO.setRegForValue( getUnifiedRegNum( IntRegClassID, SparcIntRegOrder::i7) );
151 // Instead of setting the color, we can suggest one. In that case,
152 // we have to test later whether it received the suggested color.
153 // In that case, a LR has to be created at the start of method.
154 // It has to be done as follows (remove the setRegVal above):
157 const Value *RetAddrVal = MO.getVRegValue();
159 assert( RetAddrVal && "LR for ret address must be created at start");
161 LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
162 RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
163 SparcIntRegOrdr::i7) );
170 //---------------------------------------------------------------------------
171 // Suggests a register for the ret address in the JMPL/CALL machine instr
172 //---------------------------------------------------------------------------
173 void UltraSparcRegInfo::suggestReg4CallAddr(const MachineInstr * CallMI,
175 vector<RegClass *> RCList) const {
178 const Value *RetAddrVal = getCallInstRetAddr( CallMI );
180 // RetAddrVal cannot be NULL (asserted in getCallInstRetAddr)
181 // create a new LR for the return address and color it
183 LiveRange * RetAddrLR = new LiveRange();
184 RetAddrLR->add( RetAddrVal );
185 unsigned RegClassID = getRegClassIDOfValue( RetAddrVal );
186 RetAddrLR->setRegClass( RCList[RegClassID] );
187 RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o7));
188 LRI.addLRToMap( RetAddrVal, RetAddrLR);
192 assert( (CallMI->getNumOperands() == 3) && "JMPL must have 3 operands");
194 // directly set color since the LR of ret address (if there were one)
195 // will not extend after the call instr
197 MachineOperand & MO = ( MachineOperand &) CallMI->getOperand(2);
198 MO.setRegForValue( getUnifiedRegNum( IntRegClassID,SparcIntRegOrder::o7) );
207 //---------------------------------------------------------------------------
208 // This method will suggest colors to incoming args to a method.
209 // If the arg is passed on stack due to the lack of regs, NOTHING will be
210 // done - it will be colored (or spilled) as a normal value.
211 //---------------------------------------------------------------------------
213 void UltraSparcRegInfo::suggestRegs4MethodArgs(const Method *const Meth,
214 LiveRangeInfo& LRI) const
217 // get the argument list
218 const Method::ArgumentListType& ArgList = Meth->getArgumentList();
219 // get an iterator to arg list
220 Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
223 for( unsigned argNo=0; ArgIt != ArgList.end() ; ++ArgIt, ++argNo) {
226 LiveRange *const LR = LRI.getLiveRangeForValue((const Value *) *ArgIt);
227 assert( LR && "No live range found for method arg");
229 unsigned RegType = getRegType( LR );
232 // if the arg is in int class - allocate a reg for an int arg
233 if( RegType == IntRegType ) {
235 if( argNo < NumOfIntArgRegs) {
236 LR->setSuggestedColor( SparcIntRegOrder::i0 + argNo );
241 // Do NOTHING as this will be colored as a normal value.
242 if (DEBUG_RA) cerr << " Int Regr not suggested for method arg\n";
246 else if( RegType==FPSingleRegType && (argNo*2+1) < NumOfFloatArgRegs)
247 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2 + 1) );
250 else if( RegType == FPDoubleRegType && (argNo*2) < NumOfFloatArgRegs)
251 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2) );
258 //---------------------------------------------------------------------------
260 //---------------------------------------------------------------------------
262 void UltraSparcRegInfo::colorMethodArgs(const Method *const Meth,
264 AddedInstrns *const FirstAI) const {
266 // get the argument list
267 const Method::ArgumentListType& ArgList = Meth->getArgumentList();
268 // get an iterator to arg list
269 Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
275 for( unsigned argNo=0; ArgIt != ArgList.end() ; ++ArgIt, ++argNo) {
278 LiveRange *const LR = LRI.getLiveRangeForValue((const Value *) *ArgIt);
279 assert( LR && "No live range found for method arg");
282 unsigned RegType = getRegType( LR );
283 unsigned RegClassID = (LR->getRegClass())->getID();
286 // find whether this argument is coming in a register (if not, on stack)
288 bool isArgInReg = false;
289 unsigned UniArgReg = InvalidRegNum; // reg that LR MUST be colored with
291 if( (RegType== IntRegType && argNo < NumOfIntArgRegs)) {
293 UniArgReg = getUnifiedRegNum( RegClassID, SparcIntRegOrder::i0 + argNo );
295 else if(RegType == FPSingleRegType && argNo < NumOfFloatArgRegs) {
297 UniArgReg = getUnifiedRegNum( RegClassID,
298 SparcFloatRegOrder::f0 + argNo*2 + 1 ) ;
300 else if(RegType == FPDoubleRegType && argNo < NumOfFloatArgRegs) {
302 UniArgReg = getUnifiedRegNum(RegClassID, SparcFloatRegOrder::f0+argNo*2);
306 if( LR->hasColor() ) {
308 unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
310 // if LR received the correct color, nothing to do
311 if( UniLRReg == UniArgReg )
314 // We are here because the LR did not have a suggested
315 // color or did not receive the suggested color but LR got a register.
316 // Now we have to copy %ix reg (or stack pos of arg)
317 // to the register it was colored with.
319 // if the arg is coming in UniArgReg register MUST go into
320 // the UniLRReg register
322 AdMI = cpReg2RegMI( UniArgReg, UniLRReg, RegType );
326 // Now the arg is coming on stack. Since the LR recieved a register,
327 // we just have to load the arg on stack into that register
328 const MachineFrameInfo& frameInfo = target.getFrameInfo();
329 assert(frameInfo.argsOnStackHaveFixedSize());
333 frameInfo.getFirstIncomingArgOffset(MachineCodeForMethod::get(Meth), growUp);
335 growUp? firstArg + argNo * frameInfo.getSizeOfEachArgOnStack()
336 : firstArg - argNo * frameInfo.getSizeOfEachArgOnStack();
338 AdMI = cpMem2RegMI(getFramePointer(), offsetFromFP,
342 FirstAI->InstrnsBefore.push_back( AdMI );
344 } // if LR received a color
348 // Now, the LR did not receive a color. But it has a stack offset for
351 // So, if the arg is coming in UniArgReg register, we can just move
352 // that on to the stack pos of LR
357 MachineInstr *AdIBef =
358 cpReg2MemMI(UniArgReg, getFramePointer(),
359 LR->getSpillOffFromFP(), RegType );
361 FirstAI->InstrnsBefore.push_back( AdMI );
366 // Now the arg is coming on stack. Since the LR did NOT
367 // recieved a register as well, it is allocated a stack position. We
368 // can simply change the stack poistion of the LR. We can do this,
369 // since this method is called before any other method that makes
370 // uses of the stack pos of the LR (e.g., updateMachineInstr)
372 const MachineFrameInfo& frameInfo = target.getFrameInfo();
373 assert(frameInfo.argsOnStackHaveFixedSize());
376 int firstArg = frameInfo.getFirstIncomingArgOffset(MachineCodeForMethod::get(Meth), growUp);
378 growUp? firstArg + argNo * frameInfo.getSizeOfEachArgOnStack()
379 : firstArg - argNo * frameInfo.getSizeOfEachArgOnStack();
381 LR->modifySpillOffFromFP( offsetFromFP );
386 } // for each incoming argument
393 //---------------------------------------------------------------------------
394 // This method is called before graph coloring to suggest colors to the
395 // outgoing call args and the return value of the call.
396 //---------------------------------------------------------------------------
397 void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *const CallMI,
399 vector<RegClass *> RCList) const {
401 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
403 suggestReg4CallAddr(CallMI, LRI, RCList);
406 // First color the return value of the call instruction. The return value
407 // will be in %o0 if the value is an integer type, or in %f0 if the
408 // value is a float type.
410 // the return value cannot have a LR in machine instruction since it is
411 // only defined by the call instruction
413 // if type is not void, create a new live range and set its
414 // register class and add to LRI
417 const Value *RetVal = getCallInstRetVal( CallMI );
422 assert( (! LRI.getLiveRangeForValue( RetVal ) ) &&
423 "LR for ret Value of call already definded!");
426 // create a new LR for the return value
428 LiveRange * RetValLR = new LiveRange();
429 RetValLR->add( RetVal );
430 unsigned RegClassID = getRegClassIDOfValue( RetVal );
431 RetValLR->setRegClass( RCList[RegClassID] );
432 LRI.addLRToMap( RetVal, RetValLR);
434 // now suggest a register depending on the register class of ret arg
436 if( RegClassID == IntRegClassID )
437 RetValLR->setSuggestedColor(SparcIntRegOrder::o0);
438 else if (RegClassID == FloatRegClassID )
439 RetValLR->setSuggestedColor(SparcFloatRegOrder::f0 );
440 else assert( 0 && "Unknown reg class for return value of call\n");
445 // Now suggest colors for arguments (operands) of the call instruction.
446 // Colors are suggested only if the arg number is smaller than the
447 // the number of registers allocated for argument passing.
448 // Now, go thru call args - implicit operands of the call MI
450 unsigned NumOfCallArgs = getCallInstNumArgs( CallMI );
452 for(unsigned argNo=0, i=0; i < NumOfCallArgs; ++i, ++argNo ) {
454 const Value *CallArg = CallMI->getImplicitRef(i);
456 // get the LR of call operand (parameter)
457 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
459 // not possible to have a null LR since all args (even consts)
460 // must be defined before
463 cerr << " ERROR: In call instr, no LR for arg: " ;
464 printValue(CallArg); cerr << endl;
466 assert(0 && "NO LR for call arg");
470 unsigned RegType = getRegType( LR );
472 // if the arg is in int class - allocate a reg for an int arg
473 if( RegType == IntRegType ) {
475 if( argNo < NumOfIntArgRegs)
476 LR->setSuggestedColor( SparcIntRegOrder::o0 + argNo );
479 // Do NOTHING as this will be colored as a normal value.
480 cerr << " Regr not suggested for int call arg" << endl;
483 else if( RegType == FPSingleRegType && (argNo*2 +1)< NumOfFloatArgRegs)
484 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2 + 1) );
487 else if( RegType == FPDoubleRegType && (argNo*2) < NumOfFloatArgRegs)
488 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2) );
491 } // for all call arguments
496 //---------------------------------------------------------------------------
497 // After graph coloring, we have call this method to see whehter the return
498 // value and the call args received the correct colors. If not, we have
499 // to instert copy instructions.
500 //---------------------------------------------------------------------------
502 void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
504 AddedInstrns *const CallAI,
505 PhyRegAlloc &PRA) const {
507 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
509 // Reset the optional args area in the stack frame
510 // since that is reused for each call
512 PRA.mcInfo.resetOptionalArgs(target);
514 // First color the return value of the call.
515 // If there is a LR for the return value, it means this
516 // method returns a value
520 const Value *RetVal = getCallInstRetVal( CallMI );
524 LiveRange * RetValLR = LRI.getLiveRangeForValue( RetVal );
527 cerr << "\nNo LR for:";
528 printValue( RetVal );
530 assert( RetValLR && "ERR:No LR for non-void return value");
534 unsigned RegClassID = (RetValLR->getRegClass())->getID();
535 bool recvCorrectColor = false;
537 unsigned CorrectCol; // correct color for ret value
538 if(RegClassID == IntRegClassID)
539 CorrectCol = SparcIntRegOrder::o0;
540 else if(RegClassID == FloatRegClassID)
541 CorrectCol = SparcFloatRegOrder::f0;
543 assert( 0 && "Unknown RegClass");
547 // if the LR received the correct color, NOTHING to do
549 if( RetValLR->hasColor() )
550 if( RetValLR->getColor() == CorrectCol )
551 recvCorrectColor = true;
554 // if we didn't receive the correct color for some reason,
555 // put copy instruction
557 if( !recvCorrectColor ) {
559 unsigned RegType = getRegType( RetValLR );
561 // the reg that LR must be colored with
562 unsigned UniRetReg = getUnifiedRegNum( RegClassID, CorrectCol);
564 if( RetValLR->hasColor() ) {
567 UniRetLRReg=getUnifiedRegNum(RegClassID,RetValLR->getColor());
569 // the return value is coming in UniRetReg but has to go into
572 AdMI = cpReg2RegMI( UniRetReg, UniRetLRReg, RegType );
577 // if the LR did NOT receive a color, we have to move the return
578 // value coming in UniRetReg to the stack pos of spilled LR
580 AdMI = cpReg2MemMI(UniRetReg, getFramePointer(),
581 RetValLR->getSpillOffFromFP(), RegType );
584 CallAI->InstrnsAfter.push_back( AdMI );
586 } // the LR didn't receive the suggested color
588 } // if there a return value
591 // Now color all args of the call instruction
593 vector <MachineInstr *> AddedInstrnsBefore;
595 unsigned NumOfCallArgs = getCallInstNumArgs( CallMI );
597 for(unsigned argNo=0, i=0; i < NumOfCallArgs; ++i, ++argNo ) {
599 const Value *CallArg = CallMI->getImplicitRef(i);
601 // get the LR of call operand (parameter)
602 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
604 unsigned RegType = getRegType( CallArg );
605 unsigned RegClassID = getRegClassIDOfValue( CallArg);
607 // find whether this argument is coming in a register (if not, on stack)
609 bool isArgInReg = false;
610 unsigned UniArgReg = InvalidRegNum; // reg that LR must be colored with
612 if( (RegType== IntRegType && argNo < NumOfIntArgRegs)) {
614 UniArgReg = getUnifiedRegNum(RegClassID, SparcIntRegOrder::o0 + argNo );
616 else if(RegType == FPSingleRegType && argNo < NumOfFloatArgRegs) {
618 UniArgReg = getUnifiedRegNum(RegClassID,
619 SparcFloatRegOrder::f0 + (argNo*2 + 1) );
621 else if(RegType == FPDoubleRegType && argNo < NumOfFloatArgRegs) {
623 UniArgReg = getUnifiedRegNum(RegClassID, SparcFloatRegOrder::f0+argNo*2);
627 // not possible to have a null LR since all args (even consts)
628 // must be defined before
631 cerr << " ERROR: In call instr, no LR for arg: " ;
632 printValue(CallArg); cerr << endl;
634 assert(0 && "NO LR for call arg");
639 // if the LR received the suggested color, NOTHING to do
642 if( LR->hasColor() ) {
645 unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
647 // if LR received the correct color, nothing to do
648 if( UniLRReg == UniArgReg )
651 // We are here because though the LR is allocated a register, it
652 // was not allocated the suggested register. So, we have to copy %ix reg
653 // (or stack pos of arg) to the register it was colored with
655 // the LR is colored with UniLRReg but has to go into UniArgReg
656 // to pass it as an argument
659 AdMI = cpReg2RegMI(UniLRReg, UniArgReg, RegType );
660 AddedInstrnsBefore.push_back( AdMI );
664 // Now, we have to pass the arg on stack. Since LR received a register
665 // we just have to move that register to the stack position where
666 // the argument must be passed
668 int argOffset = PRA.mcInfo.allocateOptionalArg(target, LR->getType());
670 AdMI = cpReg2MemMI(UniLRReg, getStackPointer(), argOffset, RegType );
672 // Now add the instruction. We can directly add to
673 // CallAI->InstrnsBefore since we are just saving a reg on stack
675 CallAI->InstrnsBefore.push_back( AdMI );
677 //cerr << "\nCaution: Passing a reg on stack";
683 else { // LR is not colored (i.e., spilled)
687 // Now the LR did NOT recieve a register but has a stack poistion.
688 // Since, the outgoing arg goes in a register we just have to insert
689 // a load instruction to load the LR to outgoing register
692 AdMI = cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
693 UniArgReg, RegType );
695 cerr << "\nCaution: Loading a spilled val to a reg as a call arg";
696 AddedInstrnsBefore.push_back( AdMI ); // Now add the instruction
700 // Now, we have to pass the arg on stack. Since LR also did NOT
701 // receive a register we have to move an argument in memory to
702 // outgoing parameter on stack.
704 // Optoimize: Optimize when reverse pointers in MahineInstr are
706 // call PRA.getUnusedRegAtMI(....) to get an unused reg. Only if this
707 // fails, then use the following code. Currently, we cannot call the
708 // above method since we cannot find LVSetBefore without the BB
710 int TReg = PRA.getRegNotUsedByThisInst( LR->getRegClass(), CallMI );
712 /**** NOTE: THIS SHOULD USE THE RIGHT SIZE FOR THE REG BEING PUSHED ****/
713 int TmpOff = PRA.mcInfo.pushTempValue(target, 8);
714 // target.findOptimalStorageSize(LR->getType()));
716 int argOffset = PRA.mcInfo.allocateOptionalArg(target, LR->getType());
718 MachineInstr *Ad1, *Ad2, *Ad3, *Ad4;
721 // (1) Save TReg on stack
722 // (2) Load LR value into TReg from stack pos of LR
723 // (3) Store Treg on outgoing Arg pos on stack
724 // (4) Load the old value of TReg from stack to TReg (restore it)
726 Ad1 = cpReg2MemMI(TReg, getFramePointer(), TmpOff, RegType );
727 Ad2 = cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
729 Ad3 = cpReg2MemMI(TReg, getStackPointer(), argOffset, RegType );
730 Ad4 = cpMem2RegMI(getFramePointer(), TmpOff, TReg, RegType );
732 // We directly add to CallAI->InstrnsBefore instead of adding to
733 // AddedInstrnsBefore since these instructions must not be
736 CallAI->InstrnsBefore.push_back( Ad1 );
737 CallAI->InstrnsBefore.push_back( Ad2 );
738 CallAI->InstrnsBefore.push_back( Ad3 );
739 CallAI->InstrnsBefore.push_back( Ad4 );
741 cerr << "\nCaution: Call arg moved from stack2stack for: " << *CallMI ;
746 } // for each parameter in call instruction
749 // if we added any instruction before the call instruction, verify
750 // that they are in the proper order and if not, reorder them
752 if( ! AddedInstrnsBefore.empty() ) {
755 cerr << "\nCalling reorder with instrns: \n";
756 for(unsigned i=0; i < AddedInstrnsBefore.size(); i++)
757 cerr << *(AddedInstrnsBefore[i]);
760 vector <MachineInstr *> TmpVec;
761 OrderAddedInstrns(AddedInstrnsBefore, TmpVec, PRA);
764 cerr << "\nAfter reordering instrns: \n";
765 for(unsigned i=0; i < TmpVec.size(); i++)
766 cerr << *(TmpVec[i]);
769 // copy the results back from TmpVec to InstrnsBefore
770 for(unsigned i=0; i < TmpVec.size(); i++)
771 CallAI->InstrnsBefore.push_back( TmpVec[i] );
775 // Reset optional args area again to be safe
776 PRA.mcInfo.resetOptionalArgs(target);
781 //---------------------------------------------------------------------------
782 // This method is called for an LLVM return instruction to identify which
783 // values will be returned from this method and to suggest colors.
784 //---------------------------------------------------------------------------
785 void UltraSparcRegInfo::suggestReg4RetValue(const MachineInstr *const RetMI,
786 LiveRangeInfo& LRI) const {
788 assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) );
790 suggestReg4RetAddr(RetMI, LRI);
792 // if there is an implicit ref, that has to be the ret value
793 if( RetMI->getNumImplicitRefs() > 0 ) {
795 // The first implicit operand is the return value of a return instr
796 const Value *RetVal = RetMI->getImplicitRef(0);
799 LiveRange *const LR = LRI.getLiveRangeForValue( RetVal );
802 cerr << "\nNo LR for:";
803 printValue( RetVal );
805 assert( LR && "No LR for return value of non-void method");
809 unsigned RegClassID = (LR->getRegClass())->getID();
811 if( RegClassID == IntRegClassID )
812 LR->setSuggestedColor(SparcIntRegOrder::i0);
814 else if ( RegClassID == FloatRegClassID )
815 LR->setSuggestedColor(SparcFloatRegOrder::f0);
823 //---------------------------------------------------------------------------
824 // Colors the return value of a method to %i0 or %f0, if possible. If it is
825 // not possilbe to directly color the LR, insert a copy instruction to move
826 // the LR to %i0 or %f0. When the LR is spilled, instead of the copy, we
827 // have to put a load instruction.
828 //---------------------------------------------------------------------------
829 void UltraSparcRegInfo::colorRetValue(const MachineInstr *const RetMI,
831 AddedInstrns *const RetAI) const {
833 assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) );
835 // if there is an implicit ref, that has to be the ret value
836 if( RetMI->getNumImplicitRefs() > 0 ) {
838 // The first implicit operand is the return value of a return instr
839 const Value *RetVal = RetMI->getImplicitRef(0);
842 LiveRange *const LR = LRI.getLiveRangeForValue( RetVal );
845 cerr << "\nNo LR for:";
846 printValue( RetVal );
848 // assert( LR && "No LR for return value of non-void method");
852 unsigned RegClassID = getRegClassIDOfValue(RetVal);
853 unsigned RegType = getRegType( RetVal );
856 if(RegClassID == IntRegClassID)
857 CorrectCol = SparcIntRegOrder::i0;
858 else if(RegClassID == FloatRegClassID)
859 CorrectCol = SparcFloatRegOrder::f0;
861 assert( 0 && "Unknown RegClass");
865 // if the LR received the correct color, NOTHING to do
868 if( LR->getColor() == CorrectCol )
871 unsigned UniRetReg = getUnifiedRegNum( RegClassID, CorrectCol );
873 if( LR->hasColor() ) {
875 // We are here because the LR was allocted a regiter
876 // It may be the suggested register or not
878 // copy the LR of retun value to i0 or f0
880 unsigned UniLRReg =getUnifiedRegNum( RegClassID, LR->getColor());
882 // the LR received UniLRReg but must be colored with UniRetReg
883 // to pass as the return value
885 AdMI = cpReg2RegMI( UniLRReg, UniRetReg, RegType);
886 RetAI->InstrnsBefore.push_back( AdMI );
888 else { // if the LR is spilled
890 AdMI = cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
892 RetAI->InstrnsBefore.push_back( AdMI );
893 cout << "\nCopied the return value from stack";
896 } // if there is a return value
901 //---------------------------------------------------------------------------
902 // Copy from a register to register. Register number must be the unified
904 //---------------------------------------------------------------------------
906 MachineInstr * UltraSparcRegInfo::cpReg2RegMI(const unsigned SrcReg,
907 const unsigned DestReg,
908 const int RegType) const {
910 assert( ((int)SrcReg != InvalidRegNum) && ((int)DestReg != InvalidRegNum) &&
913 MachineInstr * MI = NULL;
920 MI = new MachineInstr(ADD, 3);
921 MI->SetMachineOperand(0, SrcReg, false);
922 MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
923 MI->SetMachineOperand(2, DestReg, true);
926 case FPSingleRegType:
927 MI = new MachineInstr(FMOVS, 2);
928 MI->SetMachineOperand(0, SrcReg, false);
929 MI->SetMachineOperand(1, DestReg, true);
932 case FPDoubleRegType:
933 MI = new MachineInstr(FMOVD, 2);
934 MI->SetMachineOperand(0, SrcReg, false);
935 MI->SetMachineOperand(1, DestReg, true);
939 assert(0 && "Unknow RegType");
946 //---------------------------------------------------------------------------
947 // Copy from a register to memory (i.e., Store). Register number must
948 // be the unified register number
949 //---------------------------------------------------------------------------
952 MachineInstr * UltraSparcRegInfo::cpReg2MemMI(const unsigned SrcReg,
953 const unsigned DestPtrReg,
955 const int RegType) const {
958 MachineInstr * MI = NULL;
964 MI = new MachineInstr(STX, 3);
965 MI->SetMachineOperand(0, SrcReg, false);
966 MI->SetMachineOperand(1, DestPtrReg, false);
967 MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
968 (int64_t) Offset, false);
971 case FPSingleRegType:
972 MI = new MachineInstr(ST, 3);
973 MI->SetMachineOperand(0, SrcReg, false);
974 MI->SetMachineOperand(1, DestPtrReg, false);
975 MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
976 (int64_t) Offset, false);
979 case FPDoubleRegType:
980 MI = new MachineInstr(STD, 3);
981 MI->SetMachineOperand(0, SrcReg, false);
982 MI->SetMachineOperand(1, DestPtrReg, false);
983 MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
984 (int64_t) Offset, false);
988 assert( 0 && "Cannot directly store %ccr to memory");
991 assert(0 && "Unknow RegType in cpReg2MemMI");
998 //---------------------------------------------------------------------------
999 // Copy from memory to a reg (i.e., Load) Register number must be the unified
1001 //---------------------------------------------------------------------------
1004 MachineInstr * UltraSparcRegInfo::cpMem2RegMI(const unsigned SrcPtrReg,
1006 const unsigned DestReg,
1007 const int RegType) const {
1009 MachineInstr * MI = NULL;
1014 case FloatCCRegType:
1015 MI = new MachineInstr(LDX, 3);
1016 MI->SetMachineOperand(0, SrcPtrReg, false);
1017 MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,
1018 (int64_t) Offset, false);
1019 MI->SetMachineOperand(2, DestReg, true);
1022 case FPSingleRegType:
1023 MI = new MachineInstr(LD, 3);
1024 MI->SetMachineOperand(0, SrcPtrReg, false);
1025 MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,
1026 (int64_t) Offset, false);
1027 MI->SetMachineOperand(2, DestReg, true);
1031 case FPDoubleRegType:
1032 MI = new MachineInstr(LDD, 3);
1033 MI->SetMachineOperand(0, SrcPtrReg, false);
1034 MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,
1035 (int64_t) Offset, false);
1036 MI->SetMachineOperand(2, DestReg, true);
1040 assert( 0 && "Cannot directly load into %ccr from memory");
1043 assert(0 && "Unknown RegType in cpMem2RegMI");
1053 //---------------------------------------------------------------------------
1054 // Generate a copy instruction to copy a value to another. Temporarily
1055 // used by PhiElimination code.
1056 //---------------------------------------------------------------------------
1059 MachineInstr * UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest) const{
1061 int RegType = getRegType( Src );
1063 assert( (RegType==getRegType(Src)) && "Src & Dest are diff types");
1065 MachineInstr * MI = NULL;
1071 MI = new MachineInstr(ADD, 3);
1072 MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
1073 MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
1074 MI->SetMachineOperand(2, MachineOperand:: MO_VirtualRegister, Dest, true);
1077 case FPSingleRegType:
1078 MI = new MachineInstr(FMOVS, 2);
1079 MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
1080 MI->SetMachineOperand(1, MachineOperand:: MO_VirtualRegister, Dest, true);
1084 case FPDoubleRegType:
1085 MI = new MachineInstr(FMOVD, 2);
1086 MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
1087 MI->SetMachineOperand(1, MachineOperand:: MO_VirtualRegister, Dest, true);
1091 assert(0 && "Unknow RegType in CpValu2Value");
1102 //----------------------------------------------------------------------------
1103 // This method inserts caller saving/restoring instructons before/after
1104 // a call machine instruction.
1105 //----------------------------------------------------------------------------
1108 void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *MInst,
1109 const BasicBlock *BB,
1110 PhyRegAlloc &PRA) const {
1111 // assert( (getInstrInfo()).isCall( MInst->getOpCode() ) );
1113 // Clear the temp area of the stack
1114 PRA.mcInfo.popAllTempValues(target);
1116 hash_set<unsigned> PushedRegSet;
1118 // Now find the LR of the return value of the call
1119 // The last *implicit operand* is the return value of a call
1120 // Insert it to to he PushedRegSet since we must not save that register
1121 // and restore it after the call.
1122 // We do this because, we look at the LV set *after* the instruction
1123 // to determine, which LRs must be saved across calls. The return value
1124 // of the call is live in this set - but we must not save/restore it.
1127 const Value *RetVal = getCallInstRetVal( MInst );
1131 LiveRange *RetValLR = PRA.LRI.getLiveRangeForValue( RetVal );
1132 assert( RetValLR && "No LR for RetValue of call");
1134 if( RetValLR->hasColor())
1135 PushedRegSet.insert(
1136 getUnifiedRegNum((RetValLR->getRegClass())->getID(),
1137 RetValLR->getColor() ) );
1141 const LiveVarSet *LVSetAft = PRA.LVI->getLiveVarSetAfterMInst(MInst, BB);
1143 LiveVarSet::const_iterator LIt = LVSetAft->begin();
1145 // for each live var in live variable set after machine inst
1146 for( ; LIt != LVSetAft->end(); ++LIt) {
1148 // get the live range corresponding to live var
1149 LiveRange *const LR = PRA.LRI.getLiveRangeForValue(*LIt );
1151 // LR can be null if it is a const since a const
1152 // doesn't have a dominating def - see Assumptions above
1155 if( LR->hasColor() ) {
1157 unsigned RCID = (LR->getRegClass())->getID();
1158 unsigned Color = LR->getColor();
1160 if ( isRegVolatile(RCID, Color) ) {
1162 // if the value is in both LV sets (i.e., live before and after
1163 // the call machine instruction)
1165 unsigned Reg = getUnifiedRegNum(RCID, Color);
1167 if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
1169 // if we haven't already pushed that register
1171 unsigned RegType = getRegType( LR );
1173 // Now get two instructions - to push on stack and pop from stack
1174 // and add them to InstrnsBefore and InstrnsAfter of the
1177 /**** NOTE: THIS SHOULD USE THE RIGHT SIZE FOR THE REG BEING PUSHED ****/
1178 int StackOff = PRA.mcInfo.pushTempValue(target, 8);
1179 // target.findOptimalStorageSize(LR->getType()));
1181 MachineInstr *AdIBefCC, *AdIAftCC, *AdICpCC;
1182 MachineInstr *AdIBef, *AdIAft;
1185 //---- Insert code for pushing the reg on stack ----------
1187 if( RegType == IntCCRegType ) {
1189 // Handle IntCCRegType specially since we cannot directly
1190 // push %ccr on to the stack
1192 const LiveVarSet *LVSetBef =
1193 PRA.LVI->getLiveVarSetBeforeMInst(MInst, BB);
1195 // get a free INTEGER register
1197 PRA.getUsableRegAtMI(LR->getRegClass(), IntRegType, MInst,
1198 LVSetBef, AdIBefCC, AdIAftCC);
1200 // insert the instructions in reverse order since we are
1201 // adding them to the front of InstrnsBefore
1204 (PRA.AddedInstrMap[MInst]->InstrnsBefore).push_front(AdIAftCC);
1206 AdICpCC = cpCCR2IntMI(FreeIntReg);
1207 (PRA.AddedInstrMap[MInst]->InstrnsBefore).push_front(AdICpCC);
1210 (PRA.AddedInstrMap[MInst]->InstrnsBefore).push_front(AdIBefCC);
1213 cerr << "\n!! Inserted caller saving (push) inst for %ccr:";
1214 if(AdIBefCC) cerr << "\t" << *(AdIBefCC);
1215 cerr << "\t" << *AdICpCC;
1216 if(AdIAftCC) cerr << "\t" << *(AdIAftCC);
1220 // for any other register type, just add the push inst
1221 AdIBef = cpReg2MemMI(Reg, getFramePointer(), StackOff, RegType );
1222 ((PRA.AddedInstrMap[MInst])->InstrnsBefore).push_front(AdIBef);
1226 //---- Insert code for popping the reg from the stack ----------
1228 if( RegType == IntCCRegType ) {
1230 // Handle IntCCRegType specially since we cannot directly
1231 // pop %ccr on from the stack
1233 // get a free INT register
1235 PRA.getUsableRegAtMI(LR->getRegClass(), IntRegType, MInst,
1236 LVSetAft, AdIBefCC, AdIAftCC);
1239 (PRA.AddedInstrMap[MInst]->InstrnsAfter).push_back(AdIBefCC);
1241 AdICpCC = cpInt2CCRMI(FreeIntReg);
1242 (PRA.AddedInstrMap[MInst]->InstrnsAfter).push_back(AdICpCC);
1245 (PRA.AddedInstrMap[MInst]->InstrnsAfter).push_back(AdIAftCC);
1249 cerr << "\n!! Inserted caller saving (pop) inst for %ccr:";
1250 if(AdIBefCC) cerr << "\t" << *(AdIBefCC);
1251 cerr << "\t" << *AdICpCC;
1252 if(AdIAftCC) cerr << "\t" << *(AdIAftCC);
1256 // for any other register type, just add the pop inst
1257 AdIAft = cpMem2RegMI(getFramePointer(), StackOff, Reg, RegType );
1258 ((PRA.AddedInstrMap[MInst])->InstrnsAfter).push_back(AdIAft);
1261 PushedRegSet.insert( Reg );
1264 cerr << "\nFor call inst:" << *MInst;
1265 cerr << " -inserted caller saving instrs:\n\t ";
1266 if( RegType == IntCCRegType )
1267 cerr << *AdIBefCC << "\t" << *AdIAftCC ;
1269 cerr << *AdIBef << "\t" << *AdIAft ;
1271 } // if not already pushed
1273 } // if LR has a volatile color
1275 } // if LR has color
1277 } // if there is a LR for Var
1279 } // for each value in the LV set after instruction
1281 // Clear the temp area of the stack
1282 PRA.mcInfo.popAllTempValues(target);
1286 //---------------------------------------------------------------------------
1287 // Copies %ccr into an integer register. IntReg is the UNIFIED register
1289 //---------------------------------------------------------------------------
1291 MachineInstr * UltraSparcRegInfo::cpCCR2IntMI(const unsigned IntReg) const {
1292 MachineInstr * MI = NULL;
1294 MI = new MachineInstr(RDCCR, 2);
1295 MI->SetMachineOperand(0, SparcIntCCRegOrder::ccr, false);
1296 MI->SetMachineOperand(1, IntReg, true);
1301 //---------------------------------------------------------------------------
1302 // Copies an integer register into %ccr. IntReg is the UNIFIED register
1304 //---------------------------------------------------------------------------
1306 MachineInstr * UltraSparcRegInfo::cpInt2CCRMI(const unsigned IntReg) const {
1307 MachineInstr * MI = NULL;
1309 MI = new MachineInstr(WRCCR, 3);
1310 MI->SetMachineOperand(0, IntReg, false);
1311 MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
1312 MI->SetMachineOperand(2, SparcIntCCRegOrder::ccr, true);
1320 //---------------------------------------------------------------------------
1321 // Print the register assigned to a LR
1322 //---------------------------------------------------------------------------
1324 void UltraSparcRegInfo::printReg(const LiveRange *const LR) {
1326 unsigned RegClassID = (LR->getRegClass())->getID();
1328 cerr << " *Node " << (LR->getUserIGNode())->getIndex();
1330 if( ! LR->hasColor() ) {
1331 cerr << " - could not find a color" << endl;
1335 // if a color is found
1337 cerr << " colored with color "<< LR->getColor();
1339 if( RegClassID == IntRegClassID ) {
1341 cerr<< " [" << SparcIntRegOrder::getRegName(LR->getColor()) ;
1342 cerr << "]" << endl;
1344 else if ( RegClassID == FloatRegClassID) {
1345 cerr << "[" << SparcFloatRegOrder::getRegName(LR->getColor());
1346 if( LR->getTypeID() == Type::DoubleTyID )
1347 cerr << "+" << SparcFloatRegOrder::getRegName(LR->getColor()+1);
1348 cerr << "]" << endl;
1352 //---------------------------------------------------------------------------
1353 // This method examines instructions inserted by RegAlloc code before a
1354 // machine instruction to detect invalid orders that destroy values before
1355 // they are used. If it detects such conditions, it reorders the instructions.
1357 // The unordered instructions come in the UnordVec. These instructions are
1358 // instructions inserted by RegAlloc. All such instruction MUST have
1359 // their USES BEFORE THE DEFS after reordering.
1361 // The UnordVec & OrdVec must be DISTINCT. The OrdVec must be empty when
1362 // this method is called.
1364 // This method uses two vectors for efficiency in accessing
1366 // Since instructions are inserted in RegAlloc, this assumes that the
1367 // first operand is the source reg and the last operand is the dest reg.
1369 // All the uses are before THE def to a register
1372 //---------------------------------------------------------------------------
1373 void UltraSparcRegInfo::OrderAddedInstrns( vector<MachineInstr *> &UnordVec,
1374 vector<MachineInstr *> &OrdVec,
1375 PhyRegAlloc &PRA) const{
1378 Problem: We can have instructions inserted by RegAlloc like
1380 2. add %oy %g0 %oz, where z!=x or z==x
1382 This is wrong since %oy used by 2 is overwritten by 1
1385 We re-order the instructions so that the uses are before the defs
1390 for each instruction 'DefInst' in the UnOrdVec
1391 for each instruction 'UseInst' that follows the DefInst
1392 if the reg defined by DefInst is used by UseInst
1393 mark DefInst as not movable in this iteration
1394 If DefInst is not marked as not-movable, move DefInst to OrdVec
1395 while all instructions in DefInst are moved to OrdVec
1397 For moving, we call the move2OrdVec(). It checks whether there is a def
1398 in it for the uses in the instruction to be added to OrdVec. If there
1399 are no preceding defs, it just appends the instruction. If there is a
1400 preceding def, it puts two instructions to save the reg on stack before
1401 the load and puts a restore at use.
1407 bool DebugPrint = false;
1411 CouldMoveAll = true;
1413 vector<MachineInstr *>::iterator DefIt = UnordVec.begin();
1415 for( ; DefIt != UnordVec.end(); ++DefIt ) {
1417 // for each instruction in the UnordVec do ...
1419 MachineInstr *DefInst = *DefIt;
1421 if( DefInst == NULL) continue;
1423 //cerr << "\nInst in UnordVec = " << *DefInst;
1425 // last operand is the def (unless for a store which has no def reg)
1426 MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
1428 if( DefOp.opIsDef() &&
1429 DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1431 // If the operand in DefInst is a def ...
1433 bool DefEqUse = false;
1435 vector<MachineInstr *>::iterator UseIt = DefIt;
1438 for( ; UseIt != UnordVec.end(); ++UseIt ) {
1440 MachineInstr *UseInst = *UseIt;
1441 if( UseInst == NULL) continue;
1443 // for each inst (UseInst) that is below the DefInst do ...
1446 MachineOperand& UseOp = UseInst->getOperand(0);
1448 if( ! UseOp.opIsDef() &&
1449 UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1451 // if use is a register ...
1453 if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
1455 // if Def and this use are the same, it means that this use
1456 // is destroyed by a def before it is used
1458 // cerr << "\nCouldn't move " << *DefInst;
1461 CouldMoveAll = false;
1464 } // if two registers are equal
1466 } // if use is a register
1468 }// for all use instructions
1472 // after examining all the instructions that follow the DefInst
1473 // if there are no dependencies, we can move it to the OrdVec
1475 // cerr << "Moved to Ord: " << *DefInst;
1477 moveInst2OrdVec(OrdVec, DefInst, PRA);
1479 //OrdVec.push_back(DefInst);
1481 // mark the pos of DefInst with NULL to indicate that it is
1486 } // if Def is a machine register
1488 } // for all instructions in the UnordVec
1491 } while( !CouldMoveAll);
1495 cerr << "\nAdded instructions were reordered to:\n";
1496 for(unsigned int i=0; i < OrdVec.size(); i++)
1497 cerr << *(OrdVec[i]);
1509 void UltraSparcRegInfo::moveInst2OrdVec(vector<MachineInstr *> &OrdVec,
1510 MachineInstr *UnordInst,
1511 PhyRegAlloc &PRA ) const {
1513 MachineOperand& UseOp = UnordInst->getOperand(0);
1515 if( ! UseOp.opIsDef() &&
1516 UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1518 // for the use of UnordInst, see whether there is a defining instr
1519 // before in the OrdVec
1520 bool DefEqUse = false;
1522 vector<MachineInstr *>::iterator OrdIt = OrdVec.begin();
1524 for( ; OrdIt != OrdVec.end(); ++OrdIt ) {
1526 MachineInstr *OrdInst = *OrdIt ;
1528 MachineOperand& DefOp =
1529 OrdInst->getOperand(OrdInst->getNumOperands()-1);
1531 if( DefOp.opIsDef() &&
1532 DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1534 //cerr << "\nDefining Ord Inst: " << *OrdInst;
1536 if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
1538 // we are here because there is a preceding def in the OrdVec
1539 // for the use in this intr we are going to insert. This
1540 // happened because the original code was like:
1541 // 1. add %ox %g0 %oy
1542 // 2. add %oy %g0 %ox
1543 // In Round1, we added 2 to OrdVec but 1 remained in UnordVec
1544 // Now we are processing %ox of 1.
1547 const int UReg = DefOp.getMachineRegNum();
1548 const int RegType = getRegType(UReg);
1549 MachineInstr *AdIBef, *AdIAft;
1551 // TODO: Change 8 below
1552 /**** NOTE: THIS SHOULD USE THE RIGHT SIZE FOR THE REG BEING PUSHED ****/
1553 const int StackOff = PRA.mcInfo.pushTempValue(target, 8);
1555 // Save the UReg (%ox) on stack before it's destroyed
1556 AdIBef=cpReg2MemMI(UReg, getFramePointer(), StackOff, RegType);
1557 OrdIt = OrdVec.insert( OrdIt, AdIBef);
1558 OrdIt++; // points to current instr we processed
1560 // Load directly into DReg (%oy)
1561 MachineOperand& DOp=
1562 (UnordInst->getOperand(UnordInst->getNumOperands()-1));
1563 assert(DOp.opIsDef() && "Last operand is not the def");
1564 const int DReg = DOp.getMachineRegNum();
1566 AdIAft=cpMem2RegMI(getFramePointer(), StackOff, DReg, RegType);
1567 OrdVec.push_back(AdIAft);
1569 cerr << "\nFixed CIRCULAR references by reordering";
1572 cerr << "\nBefore CIRCULAR Reordering:\n";
1576 cerr << "\nAfter CIRCULAR Reordering - All Inst so far:\n";
1577 for(unsigned i=0; i < OrdVec.size(); i++)
1578 cerr << *(OrdVec[i]);
1581 // Do not copy the UseInst to OrdVec
1585 }// if two registers are equal
1587 } // if Def is a register
1589 } // for each instr in OrdVec
1593 // We didn't find a def in the OrdVec, so just append this inst
1594 OrdVec.push_back( UnordInst );
1595 //cerr << "Reordered Inst (Moved Dn): " << *UnordInst;
1598 }// if the operand in UnordInst is a use