1 //===-- SparcRegInfo.cpp - Sparc Target Register Information --------------===//
3 // This file contains implementation of Sparc specific helper methods
4 // used for register allocation.
6 //===----------------------------------------------------------------------===//
8 #include "SparcInternals.h"
9 #include "SparcRegClassInfo.h"
10 #include "llvm/Target/Sparc.h"
11 #include "llvm/CodeGen/MachineCodeForMethod.h"
12 #include "llvm/CodeGen/PhyRegAlloc.h"
13 #include "llvm/CodeGen/InstrSelection.h"
14 #include "llvm/CodeGen/InstrSelectionSupport.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/CodeGen/MachineInstrAnnot.h"
17 #include "llvm/CodeGen/RegAllocCommon.h"
18 #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h"
19 #include "llvm/iTerminators.h"
20 #include "llvm/iOther.h"
21 #include "llvm/Function.h"
22 #include "llvm/DerivedTypes.h"
28 UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
29 : MachineRegInfo(tgt), UltraSparcInfo(&tgt), NumOfIntArgRegs(6),
30 NumOfFloatArgRegs(32), InvalidRegNum(1000) {
32 MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID));
33 MachineRegClassArr.push_back(new SparcFloatRegClass(FloatRegClassID));
34 MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID));
35 MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID));
37 assert(SparcFloatRegOrder::StartOfNonVolatileRegs == 32 &&
38 "32 Float regs are used for float arg passing");
42 // getZeroRegNum - returns the register that contains always zero.
43 // this is the unified register number
45 int UltraSparcRegInfo::getZeroRegNum() const {
46 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
47 SparcIntRegOrder::g0);
50 // getCallAddressReg - returns the reg used for pushing the address when a
51 // method is called. This can be used for other purposes between calls
53 unsigned UltraSparcRegInfo::getCallAddressReg() const {
54 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
55 SparcIntRegOrder::o7);
58 // Returns the register containing the return address.
59 // It should be made sure that this register contains the return
60 // value when a return instruction is reached.
62 unsigned UltraSparcRegInfo::getReturnAddressReg() const {
63 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
64 SparcIntRegOrder::i7);
67 // given the unified register number, this gives the name
68 // for generating assembly code or debugging.
70 const std::string UltraSparcRegInfo::getUnifiedRegName(int reg) const {
72 return SparcIntRegOrder::getRegName(reg);
73 else if ( reg < (64 + 32) )
74 return SparcFloatRegOrder::getRegName( reg - 32);
75 else if( reg < (64+32+4) )
76 return SparcFloatCCRegOrder::getRegName( reg -32 - 64);
77 else if( reg < (64+32+4+2) ) // two names: %xcc and %ccr
78 return SparcIntCCRegOrder::getRegName( reg -32 - 64 - 4);
79 else if (reg== InvalidRegNum) //****** TODO: Remove */
82 assert(0 && "Invalid register number");
86 // Get unified reg number for frame pointer
87 unsigned UltraSparcRegInfo::getFramePointer() const {
88 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
89 SparcIntRegOrder::i6);
92 // Get unified reg number for stack pointer
93 unsigned UltraSparcRegInfo::getStackPointer() const {
94 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
95 SparcIntRegOrder::o6);
99 //---------------------------------------------------------------------------
100 // Finds whether a call is an indirect call
101 //---------------------------------------------------------------------------
104 isVarArgsFunction(const Type *funcType) {
105 return cast<FunctionType>(cast<PointerType>(funcType)
106 ->getElementType())->isVarArg();
110 isVarArgsCall(const MachineInstr *CallMI) {
111 Value* callee = CallMI->getOperand(0).getVRegValue();
112 // const Type* funcType = isa<Function>(callee)? callee->getType()
113 // : cast<PointerType>(callee->getType())->getElementType();
114 const Type* funcType = callee->getType();
115 return isVarArgsFunction(funcType);
119 // Get the register number for the specified integer arg#,
120 // assuming there are argNum total args, intArgNum int args,
121 // and fpArgNum FP args preceding (and not including) this one.
122 // Use INT regs for FP args if this is a varargs call.
125 // InvalidRegNum, if there is no int register available for the arg.
126 // regNum, otherwise (this is NOT the unified reg. num).
129 UltraSparcRegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall,
131 unsigned intArgNo, unsigned fpArgNo,
132 unsigned& regClassId) const
134 regClassId = IntRegClassID;
135 if (argNo >= NumOfIntArgRegs)
136 return InvalidRegNum;
138 return argNo + (inCallee? SparcIntRegOrder::i0 : SparcIntRegOrder::o0);
141 // Get the register number for the specified FP arg#,
142 // assuming there are argNum total args, intArgNum int args,
143 // and fpArgNum FP args preceding (and not including) this one.
144 // Use INT regs for FP args if this is a varargs call.
147 // InvalidRegNum, if there is no int register available for the arg.
148 // regNum, otherwise (this is NOT the unified reg. num).
151 UltraSparcRegInfo::regNumForFPArg(unsigned regType,
152 bool inCallee, bool isVarArgsCall,
154 unsigned intArgNo, unsigned fpArgNo,
155 unsigned& regClassId) const
158 return regNumForIntArg(inCallee, isVarArgsCall, argNo, intArgNo, fpArgNo,
162 regClassId = FloatRegClassID;
163 if (regType == FPSingleRegType)
164 return (argNo*2+1 >= NumOfFloatArgRegs)?
165 InvalidRegNum : SparcFloatRegOrder::f0 + (argNo * 2 + 1);
166 else if (regType == FPDoubleRegType)
167 return (argNo*2 >= NumOfFloatArgRegs)?
168 InvalidRegNum : SparcFloatRegOrder::f0 + (argNo * 2);
170 assert(0 && "Illegal FP register type");
175 //---------------------------------------------------------------------------
176 // Finds the return address of a call sparc specific call instruction
177 //---------------------------------------------------------------------------
179 // The following 4 methods are used to find the RegType (SparcInternals.h)
180 // of a LiveRange, a Value, and for a given register unified reg number.
182 int UltraSparcRegInfo::getRegType(unsigned regClassID,
183 const Type* type) const {
184 switch (regClassID) {
185 case IntRegClassID: return IntRegType;
186 case FloatRegClassID: {
187 if (type == Type::FloatTy)
188 return FPSingleRegType;
189 else if (type == Type::DoubleTy)
190 return FPDoubleRegType;
191 assert(0 && "Unknown type in FloatRegClass");
193 case IntCCRegClassID: return IntCCRegType;
194 case FloatCCRegClassID: return FloatCCRegType;
195 default: assert( 0 && "Unknown reg class ID"); return 0;
199 int UltraSparcRegInfo::getRegType(const LiveRange *LR) const {
200 return getRegType(LR->getRegClass()->getID(), LR->getType());
203 int UltraSparcRegInfo::getRegType(const Value *Val) const {
204 return getRegType(getRegClassIDOfValue(Val), Val->getType());
207 int UltraSparcRegInfo::getRegType(int unifiedRegNum) const {
208 if (unifiedRegNum < 32)
210 else if (unifiedRegNum < (32 + 32))
211 return FPSingleRegType;
212 else if (unifiedRegNum < (64 + 32))
213 return FPDoubleRegType;
214 else if (unifiedRegNum < (64+32+4))
215 return FloatCCRegType;
216 else if (unifiedRegNum < (64+32+4+2))
219 assert(0 && "Invalid unified register number in getRegType");
224 // To find the register class used for a specified Type
226 unsigned UltraSparcRegInfo::getRegClassIDOfType(const Type *type,
227 bool isCCReg = false) const {
228 Type::PrimitiveID ty = type->getPrimitiveID();
231 // FIXME: Comparing types like this isn't very safe...
232 if ((ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
233 (ty == Type::FunctionTyID) || (ty == Type::PointerTyID) )
234 res = IntRegClassID; // sparc int reg (ty=0: void)
235 else if (ty <= Type::DoubleTyID)
236 res = FloatRegClassID; // sparc float reg class
238 //std::cerr << "TypeID: " << ty << "\n";
239 assert(0 && "Cannot resolve register class for type");
244 return res + 2; // corresponidng condition code regiser
249 // To find the register class to which a specified register belongs
251 unsigned UltraSparcRegInfo::getRegClassIDOfReg(int unifiedRegNum) const {
252 unsigned classId = 0;
253 (void) getClassRegNum(unifiedRegNum, classId);
257 unsigned UltraSparcRegInfo::getRegClassIDOfRegType(int regType) const {
259 case IntRegType: return IntRegClassID;
260 case FPSingleRegType:
261 case FPDoubleRegType: return FloatRegClassID;
262 case IntCCRegType: return IntCCRegClassID;
263 case FloatCCRegType: return FloatCCRegClassID;
265 assert(0 && "Invalid register type in getRegClassIDOfRegType");
270 //---------------------------------------------------------------------------
271 // Suggests a register for the ret address in the RET machine instruction.
272 // We always suggest %i7 by convention.
273 //---------------------------------------------------------------------------
274 void UltraSparcRegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
275 LiveRangeInfo& LRI) const {
277 assert(target.getInstrInfo().isReturn(RetMI->getOpCode()));
279 // return address is always mapped to i7 so set it immediately
280 RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID,
281 SparcIntRegOrder::i7));
283 // Possible Optimization:
284 // Instead of setting the color, we can suggest one. In that case,
285 // we have to test later whether it received the suggested color.
286 // In that case, a LR has to be created at the start of method.
287 // It has to be done as follows (remove the setRegVal above):
289 // MachineOperand & MO = RetMI->getOperand(0);
290 // const Value *RetAddrVal = MO.getVRegValue();
291 // assert( RetAddrVal && "LR for ret address must be created at start");
292 // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
293 // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
294 // SparcIntRegOrdr::i7) );
298 //---------------------------------------------------------------------------
299 // Suggests a register for the ret address in the JMPL/CALL machine instr.
300 // Sparc ABI dictates that %o7 be used for this purpose.
301 //---------------------------------------------------------------------------
302 void UltraSparcRegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
304 std::vector<RegClass *> RCList) const {
305 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
306 const Value *RetAddrVal = argDesc->getReturnAddrReg();
307 assert(RetAddrVal && "Return address value is required");
309 // create a new LR for the return address and color it
310 LiveRange * RetAddrLR = new LiveRange();
311 RetAddrLR->insert( RetAddrVal );
312 unsigned RegClassID = getRegClassIDOfValue( RetAddrVal );
313 RetAddrLR->setRegClass( RCList[RegClassID] );
314 RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o7));
315 LRI.addLRToMap( RetAddrVal, RetAddrLR);
322 //---------------------------------------------------------------------------
323 // This method will suggest colors to incoming args to a method.
324 // According to the Sparc ABI, the first 6 incoming args are in
325 // %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float).
326 // If the arg is passed on stack due to the lack of regs, NOTHING will be
327 // done - it will be colored (or spilled) as a normal live range.
328 //---------------------------------------------------------------------------
329 void UltraSparcRegInfo::suggestRegs4MethodArgs(const Function *Meth,
330 LiveRangeInfo& LRI) const
332 // check if this is a varArgs function. needed for choosing regs.
333 bool isVarArgs = isVarArgsFunction(Meth->getType());
335 // for each argument. count INT and FP arguments separately.
336 unsigned argNo=0, intArgNo=0, fpArgNo=0;
337 for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend();
338 I != E; ++I, ++argNo) {
340 LiveRange *LR = LRI.getLiveRangeForValue(I);
341 assert(LR && "No live range found for method arg");
343 unsigned regType = getRegType(LR);
344 unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg (unused)
346 int regNum = (regType == IntRegType)
347 ? regNumForIntArg(/*inCallee*/ true, isVarArgs,
348 argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
349 : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs,
350 argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
352 if(regNum != InvalidRegNum)
353 LR->setSuggestedColor(regNum);
358 //---------------------------------------------------------------------------
359 // This method is called after graph coloring to move incoming args to
360 // the correct hardware registers if they did not receive the correct
361 // (suggested) color through graph coloring.
362 //---------------------------------------------------------------------------
363 void UltraSparcRegInfo::colorMethodArgs(const Function *Meth,
365 AddedInstrns *FirstAI) const {
367 // check if this is a varArgs function. needed for choosing regs.
368 bool isVarArgs = isVarArgsFunction(Meth->getType());
372 // for each argument. count INT and FP arguments separately.
373 unsigned argNo=0, intArgNo=0, fpArgNo=0;
374 for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend();
375 I != E; ++I, ++argNo) {
377 LiveRange *LR = LRI.getLiveRangeForValue(I);
378 assert( LR && "No live range found for method arg");
380 unsigned regType = getRegType( LR );
381 unsigned RegClassID = (LR->getRegClass())->getID();
383 // Find whether this argument is coming in a register (if not, on stack)
384 // Also find the correct register the argument must use (UniArgReg)
386 bool isArgInReg = false;
387 unsigned UniArgReg = InvalidRegNum; // reg that LR MUST be colored with
388 unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg
390 int regNum = (regType == IntRegType)
391 ? regNumForIntArg(/*inCallee*/ true, isVarArgs,
392 argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
393 : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs,
394 argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
396 if(regNum != InvalidRegNum) {
398 UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum);
401 if( LR->hasColor() ) { // if this arg received a register
403 unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
405 // if LR received the correct color, nothing to do
407 if( UniLRReg == UniArgReg )
410 // We are here because the LR did not receive the suggested
411 // but LR received another register.
412 // Now we have to copy the %i reg (or stack pos of arg)
413 // to the register the LR was colored with.
415 // if the arg is coming in UniArgReg register, it MUST go into
416 // the UniLRReg register
419 if( regClassIDOfArgReg != RegClassID ) {
420 assert(0 && "This could should work but it is not tested yet");
422 // It is a variable argument call: the float reg must go in a %o reg.
423 // We have to move an int reg to a float reg via memory.
426 RegClassID == FloatRegClassID &&
427 regClassIDOfArgReg == IntRegClassID &&
428 "This should only be an Int register for an FP argument");
430 int TmpOff = MachineCodeForMethod::get(Meth).pushTempValue(target,
431 getSpilledRegSize(regType));
432 cpReg2MemMI(FirstAI->InstrnsBefore,
433 UniArgReg, getFramePointer(), TmpOff, IntRegType);
435 cpMem2RegMI(FirstAI->InstrnsBefore,
436 getFramePointer(), TmpOff, UniLRReg, regType);
439 cpReg2RegMI(FirstAI->InstrnsBefore, UniArgReg, UniLRReg, regType);
444 // Now the arg is coming on stack. Since the LR recieved a register,
445 // we just have to load the arg on stack into that register
447 const MachineFrameInfo& frameInfo = target.getFrameInfo();
449 frameInfo.getIncomingArgOffset(MachineCodeForMethod::get(Meth),
452 cpMem2RegMI(FirstAI->InstrnsBefore,
453 getFramePointer(), offsetFromFP, UniLRReg, regType);
456 } // if LR received a color
460 // Now, the LR did not receive a color. But it has a stack offset for
462 // So, if the arg is coming in UniArgReg register, we can just move
463 // that on to the stack pos of LR
467 if( regClassIDOfArgReg != RegClassID ) {
469 "FP arguments to a varargs function should be explicitly "
470 "copied to/from int registers by instruction selection!");
472 // It must be a float arg for a variable argument call, which
473 // must come in a %o reg. Move the int reg to the stack.
475 assert(isVarArgs && regClassIDOfArgReg == IntRegClassID &&
476 "This should only be an Int register for an FP argument");
478 cpReg2MemMI(FirstAI->InstrnsBefore, UniArgReg,
479 getFramePointer(), LR->getSpillOffFromFP(), IntRegType);
482 cpReg2MemMI(FirstAI->InstrnsBefore, UniArgReg,
483 getFramePointer(), LR->getSpillOffFromFP(), regType);
489 // Now the arg is coming on stack. Since the LR did NOT
490 // recieved a register as well, it is allocated a stack position. We
491 // can simply change the stack position of the LR. We can do this,
492 // since this method is called before any other method that makes
493 // uses of the stack pos of the LR (e.g., updateMachineInstr)
495 const MachineFrameInfo& frameInfo = target.getFrameInfo();
497 frameInfo.getIncomingArgOffset(MachineCodeForMethod::get(Meth),
500 LR->modifySpillOffFromFP( offsetFromFP );
505 } // for each incoming argument
511 //---------------------------------------------------------------------------
512 // This method is called before graph coloring to suggest colors to the
513 // outgoing call args and the return value of the call.
514 //---------------------------------------------------------------------------
515 void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
517 std::vector<RegClass *> RCList) const {
518 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
520 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
522 suggestReg4CallAddr(CallMI, LRI, RCList);
524 // First color the return value of the call instruction. The return value
525 // will be in %o0 if the value is an integer type, or in %f0 if the
526 // value is a float type.
528 // the return value cannot have a LR in machine instruction since it is
529 // only defined by the call instruction
531 // if type is not void, create a new live range and set its
532 // register class and add to LRI
534 const Value *RetVal = argDesc->getReturnValue();
537 assert ((!LRI.getLiveRangeForValue(RetVal)) &&
538 "LR for ret Value of call already definded!");
540 // create a new LR for the return value
541 LiveRange *RetValLR = new LiveRange();
542 RetValLR->insert(RetVal);
543 unsigned RegClassID = getRegClassIDOfValue(RetVal);
544 RetValLR->setRegClass(RCList[RegClassID]);
545 LRI.addLRToMap(RetVal, RetValLR);
547 // now suggest a register depending on the register class of ret arg
549 if( RegClassID == IntRegClassID )
550 RetValLR->setSuggestedColor(SparcIntRegOrder::o0);
551 else if (RegClassID == FloatRegClassID )
552 RetValLR->setSuggestedColor(SparcFloatRegOrder::f0 );
553 else assert( 0 && "Unknown reg class for return value of call\n");
557 // Now suggest colors for arguments (operands) of the call instruction.
558 // Colors are suggested only if the arg number is smaller than the
559 // the number of registers allocated for argument passing.
560 // Now, go thru call args - implicit operands of the call MI
562 unsigned NumOfCallArgs = argDesc->getNumArgs();
564 for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0;
565 i < NumOfCallArgs; ++i, ++argNo) {
567 const Value *CallArg = argDesc->getArgInfo(i).getArgVal();
569 // get the LR of call operand (parameter)
570 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
572 // not possible to have a null LR since all args (even consts)
573 // must be defined before
575 cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) << "\n";
576 assert(0 && "NO LR for call arg");
579 unsigned regType = getRegType( LR );
580 unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg (unused)
582 // Choose a register for this arg depending on whether it is
583 // an INT or FP value. Here we ignore whether or not it is a
584 // varargs calls, because FP arguments will be explicitly copied
585 // to an integer Value and handled under (argCopy != NULL) below.
586 int regNum = (regType == IntRegType)
587 ? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false,
588 argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
589 : regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false,
590 argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
592 // If a register could be allocated, use it.
593 // If not, do NOTHING as this will be colored as a normal value.
594 if(regNum != InvalidRegNum)
595 LR->setSuggestedColor(regNum);
597 // Repeat for the second copy of the argument, which would be
598 // an FP argument being passed to a function with no prototype
599 const Value *argCopy = argDesc->getArgInfo(i).getArgCopy();
602 assert(regType != IntRegType && argCopy->getType()->isIntegral()
603 && "Must be passing copy of FP argument in int register");
604 int copyRegNum = regNumForIntArg(/*inCallee*/false, /*isVarArgs*/false,
605 argNo, intArgNo, fpArgNo-1,
607 assert(copyRegNum != InvalidRegNum);
608 LiveRange *const copyLR = LRI.getLiveRangeForValue(argCopy);
609 copyLR->setSuggestedColor(copyRegNum);
612 } // for all call arguments
617 //---------------------------------------------------------------------------
618 // Helper method for UltraSparcRegInfo::colorCallArgs().
619 //---------------------------------------------------------------------------
622 UltraSparcRegInfo::InitializeOutgoingArg(MachineInstr* CallMI,
623 AddedInstrns *CallAI,
624 PhyRegAlloc &PRA, LiveRange* LR,
625 unsigned regType, unsigned RegClassID,
626 int UniArgRegOrNone, unsigned int argNo,
627 std::vector<MachineInstr *>& AddedInstrnsBefore)
631 bool isArgInReg = false;
632 unsigned UniArgReg = MAXINT; // unused unless initialized below
633 if (UniArgRegOrNone != InvalidRegNum)
636 UniArgReg = (unsigned) UniArgRegOrNone;
637 CallMI->getRegsUsed().insert(UniArgReg); // mark the reg as used
640 if (LR->hasColor()) {
641 unsigned UniLRReg = getUnifiedRegNum(RegClassID, LR->getColor());
643 // if LR received the correct color, nothing to do
644 if( isArgInReg && UniArgReg == UniLRReg )
647 // The LR is allocated to a register UniLRReg and must be copied
648 // to UniArgReg or to the stack slot.
651 // Copy UniLRReg to UniArgReg
652 cpReg2RegMI(AddedInstrnsBefore, UniLRReg, UniArgReg, regType);
655 // Copy UniLRReg to the stack to pass the arg on stack.
656 const MachineFrameInfo& frameInfo = target.getFrameInfo();
657 int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo);
658 cpReg2MemMI(CallAI->InstrnsBefore,
659 UniLRReg, getStackPointer(), argOffset, regType);
662 } else { // LR is not colored (i.e., spilled)
665 // Insert a load instruction to load the LR to UniArgReg
666 cpMem2RegMI(AddedInstrnsBefore, getFramePointer(),
667 LR->getSpillOffFromFP(), UniArgReg, regType);
668 // Now add the instruction
672 // Now, we have to pass the arg on stack. Since LR also did NOT
673 // receive a register we have to move an argument in memory to
674 // outgoing parameter on stack.
675 // Use TReg to load and store the value.
676 // Use TmpOff to save TReg, since that may have a live value.
678 int TReg = PRA.getUniRegNotUsedByThisInst( LR->getRegClass(), CallMI );
679 int TmpOff = PRA.mcInfo.pushTempValue(target,
680 getSpilledRegSize(getRegType(LR)));
681 const MachineFrameInfo& frameInfo = target.getFrameInfo();
682 int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo);
684 MachineInstr *Ad1, *Ad2, *Ad3, *Ad4;
687 // (1) Save TReg on stack
688 // (2) Load LR value into TReg from stack pos of LR
689 // (3) Store Treg on outgoing Arg pos on stack
690 // (4) Load the old value of TReg from stack to TReg (restore it)
693 // When reverse pointers in MahineInstr are introduced:
694 // Call PRA.getUnusedRegAtMI(....) to get an unused reg. Step 1 is
695 // needed only if this fails. Currently, we cannot call the
696 // above method since we cannot find LVSetBefore without the BB
698 // NOTE: We directly add to CallAI->InstrnsBefore instead of adding to
699 // AddedInstrnsBefore since these instructions must not be reordered.
700 cpReg2MemMI(CallAI->InstrnsBefore,
701 TReg, getFramePointer(), TmpOff, regType);
702 cpMem2RegMI(CallAI->InstrnsBefore,
703 getFramePointer(), LR->getSpillOffFromFP(), TReg, regType);
704 cpReg2MemMI(CallAI->InstrnsBefore,
705 TReg, getStackPointer(), argOffset, regType);
706 cpMem2RegMI(CallAI->InstrnsBefore,
707 getFramePointer(), TmpOff, TReg, regType);
712 //---------------------------------------------------------------------------
713 // After graph coloring, we have call this method to see whehter the return
714 // value and the call args received the correct colors. If not, we have
715 // to instert copy instructions.
716 //---------------------------------------------------------------------------
718 void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI,
720 AddedInstrns *CallAI,
722 const BasicBlock *BB) const {
724 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
726 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
728 // First color the return value of the call.
729 // If there is a LR for the return value, it means this
730 // method returns a value
734 const Value *RetVal = argDesc->getReturnValue();
737 LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal );
740 cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
741 assert(RetValLR && "ERR:No LR for non-void return value");
744 unsigned RegClassID = (RetValLR->getRegClass())->getID();
745 bool recvCorrectColor;
746 unsigned CorrectCol; // correct color for ret value
747 unsigned UniRetReg; // unified number for CorrectCol
749 if(RegClassID == IntRegClassID)
750 CorrectCol = SparcIntRegOrder::o0;
751 else if(RegClassID == FloatRegClassID)
752 CorrectCol = SparcFloatRegOrder::f0;
754 assert( 0 && "Unknown RegClass");
758 // convert to unified number
759 UniRetReg = this->getUnifiedRegNum( RegClassID, CorrectCol);
761 // Mark the register as used by this instruction
762 CallMI->getRegsUsed().insert(UniRetReg);
764 // if the LR received the correct color, NOTHING to do
765 recvCorrectColor = RetValLR->hasColor()? RetValLR->getColor() == CorrectCol
768 // if we didn't receive the correct color for some reason,
769 // put copy instruction
770 if( !recvCorrectColor ) {
772 unsigned regType = getRegType( RetValLR );
774 if( RetValLR->hasColor() ) {
776 unsigned UniRetLRReg=getUnifiedRegNum(RegClassID,RetValLR->getColor());
778 // the return value is coming in UniRetReg but has to go into
781 cpReg2RegMI(CallAI->InstrnsAfter, UniRetReg, UniRetLRReg, regType);
786 // if the LR did NOT receive a color, we have to move the return
787 // value coming in UniRetReg to the stack pos of spilled LR
789 cpReg2MemMI(CallAI->InstrnsAfter, UniRetReg,
790 getFramePointer(),RetValLR->getSpillOffFromFP(), regType);
793 } // the LR didn't receive the suggested color
795 } // if there a return value
798 //-------------------------------------------
799 // Now color all args of the call instruction
800 //-------------------------------------------
802 std::vector<MachineInstr *> AddedInstrnsBefore;
804 unsigned NumOfCallArgs = argDesc->getNumArgs();
806 for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0;
807 i < NumOfCallArgs; ++i, ++argNo) {
809 const Value *CallArg = argDesc->getArgInfo(i).getArgVal();
811 // get the LR of call operand (parameter)
812 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
814 unsigned RegClassID = getRegClassIDOfValue( CallArg);
815 unsigned regType = getRegType( RegClassID, CallArg->getType() );
817 // Find whether this argument is coming in a register (if not, on stack)
818 // Also find the correct register the argument must use (UniArgReg)
820 bool isArgInReg = false;
821 unsigned UniArgReg = InvalidRegNum; // reg that LR MUST be colored with
822 unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg
824 // Find the register that must be used for this arg, depending on
825 // whether it is an INT or FP value. Here we ignore whether or not it
826 // is a varargs calls, because FP arguments will be explicitly copied
827 // to an integer Value and handled under (argCopy != NULL) below.
828 int regNum = (regType == IntRegType)
829 ? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false,
830 argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
831 : regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false,
832 argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
834 if(regNum != InvalidRegNum) {
836 UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum);
837 assert(regClassIDOfArgReg == RegClassID &&
838 "Moving values between reg classes must happen during selection");
841 // not possible to have a null LR since all args (even consts)
842 // must be defined before
844 cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) <<"\n";
845 assert(LR && "NO LR for call arg");
848 InitializeOutgoingArg(CallMI, CallAI, PRA, LR, regType, RegClassID,
849 UniArgReg, argNo, AddedInstrnsBefore);
851 // Repeat for the second copy of the argument, which would be
852 // an FP argument being passed to a function with no prototype.
853 // It may either be passed as a copy in an integer register
854 // (in argCopy), or on the stack (useStackSlot).
855 const Value *argCopy = argDesc->getArgInfo(i).getArgCopy();
858 assert(regType != IntRegType && argCopy->getType()->isIntegral()
859 && "Must be passing copy of FP argument in int register");
861 unsigned copyRegClassID = getRegClassIDOfValue(argCopy);
862 unsigned copyRegType = getRegType(copyRegClassID, argCopy->getType());
864 int copyRegNum = regNumForIntArg(/*inCallee*/false, /*isVarArgs*/false,
865 argNo, intArgNo, fpArgNo-1,
867 assert(copyRegNum != InvalidRegNum);
868 assert(regClassIDOfArgReg == copyRegClassID &&
869 "Moving values between reg classes must happen during selection");
871 InitializeOutgoingArg(CallMI, CallAI, PRA,
872 LRI.getLiveRangeForValue(argCopy), copyRegType,
873 copyRegClassID, copyRegNum, argNo,
877 if (regNum != InvalidRegNum &&
878 argDesc->getArgInfo(i).usesStackSlot())
880 // Pass the argument via the stack in addition to regNum
881 assert(regType != IntRegType && "Passing an integer arg. twice?");
882 assert(!argCopy && "Passing FP arg in FP reg, INT reg, and stack?");
883 InitializeOutgoingArg(CallMI, CallAI, PRA, LR, regType, RegClassID,
884 InvalidRegNum, argNo, AddedInstrnsBefore);
886 } // for each parameter in call instruction
888 // If we added any instruction before the call instruction, verify
889 // that they are in the proper order and if not, reorder them
891 std::vector<MachineInstr *> ReorderedVec;
892 if (!AddedInstrnsBefore.empty()) {
895 cerr << "\nCalling reorder with instrns: \n";
896 for(unsigned i=0; i < AddedInstrnsBefore.size(); i++)
897 cerr << *(AddedInstrnsBefore[i]);
900 OrderAddedInstrns(AddedInstrnsBefore, ReorderedVec, PRA);
901 assert(ReorderedVec.size() >= AddedInstrnsBefore.size()
902 && "Dropped some instructions when reordering!");
905 cerr << "\nAfter reordering instrns: \n";
906 for(unsigned i = 0; i < ReorderedVec.size(); i++)
907 cerr << *ReorderedVec[i];
911 // Now insert caller saving code for this call instruction
913 insertCallerSavingCode(CallAI->InstrnsBefore, CallAI->InstrnsAfter,
916 // Then insert the final reordered code for the call arguments.
918 for(unsigned i=0; i < ReorderedVec.size(); i++)
919 CallAI->InstrnsBefore.push_back( ReorderedVec[i] );
922 //---------------------------------------------------------------------------
923 // This method is called for an LLVM return instruction to identify which
924 // values will be returned from this method and to suggest colors.
925 //---------------------------------------------------------------------------
926 void UltraSparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI,
927 LiveRangeInfo &LRI) const {
929 assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) );
931 suggestReg4RetAddr(RetMI, LRI);
933 // if there is an implicit ref, that has to be the ret value
934 if( RetMI->getNumImplicitRefs() > 0 ) {
936 // The first implicit operand is the return value of a return instr
937 const Value *RetVal = RetMI->getImplicitRef(0);
939 LiveRange *const LR = LRI.getLiveRangeForValue( RetVal );
942 cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
943 assert(0 && "No LR for return value of non-void method");
946 unsigned RegClassID = (LR->getRegClass())->getID();
948 if (RegClassID == IntRegClassID)
949 LR->setSuggestedColor(SparcIntRegOrder::i0);
950 else if (RegClassID == FloatRegClassID)
951 LR->setSuggestedColor(SparcFloatRegOrder::f0);
957 //---------------------------------------------------------------------------
958 // Colors the return value of a method to %i0 or %f0, if possible. If it is
959 // not possilbe to directly color the LR, insert a copy instruction to move
960 // the LR to %i0 or %f0. When the LR is spilled, instead of the copy, we
961 // have to put a load instruction.
962 //---------------------------------------------------------------------------
963 void UltraSparcRegInfo::colorRetValue(MachineInstr *RetMI,
965 AddedInstrns *RetAI) const {
967 assert((UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode()));
969 // if there is an implicit ref, that has to be the ret value
970 if(RetMI->getNumImplicitRefs() > 0) {
972 // The first implicit operand is the return value of a return instr
973 const Value *RetVal = RetMI->getImplicitRef(0);
975 LiveRange *LR = LRI.getLiveRangeForValue(RetVal);
978 cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
979 // assert( LR && "No LR for return value of non-void method");
983 unsigned RegClassID = getRegClassIDOfValue(RetVal);
984 unsigned regType = getRegType( RetVal );
987 if(RegClassID == IntRegClassID)
988 CorrectCol = SparcIntRegOrder::i0;
989 else if(RegClassID == FloatRegClassID)
990 CorrectCol = SparcFloatRegOrder::f0;
992 assert (0 && "Unknown RegClass");
996 // convert to unified number
997 unsigned UniRetReg = this->getUnifiedRegNum(RegClassID, CorrectCol);
999 // Mark the register as used by this instruction
1000 RetMI->getRegsUsed().insert(UniRetReg);
1002 // if the LR received the correct color, NOTHING to do
1004 if (LR->hasColor() && LR->getColor() == CorrectCol)
1007 if (LR->hasColor()) {
1009 // We are here because the LR was allocted a regiter
1010 // It may be the suggested register or not
1012 // copy the LR of retun value to i0 or f0
1014 unsigned UniLRReg =getUnifiedRegNum( RegClassID, LR->getColor());
1016 // the LR received UniLRReg but must be colored with UniRetReg
1017 // to pass as the return value
1018 cpReg2RegMI(RetAI->InstrnsBefore, UniLRReg, UniRetReg, regType);
1020 else { // if the LR is spilled
1021 cpMem2RegMI(RetAI->InstrnsBefore, getFramePointer(),
1022 LR->getSpillOffFromFP(), UniRetReg, regType);
1023 cerr << "\nCopied the return value from stack\n";
1026 } // if there is a return value
1030 //---------------------------------------------------------------------------
1031 // Check if a specified register type needs a scratch register to be
1032 // copied to/from memory. If it does, the reg. type that must be used
1033 // for scratch registers is returned in scratchRegType.
1035 // Only the int CC register needs such a scratch register.
1036 // The FP CC registers can (and must) be copied directly to/from memory.
1037 //---------------------------------------------------------------------------
1040 UltraSparcRegInfo::regTypeNeedsScratchReg(int RegType,
1041 int& scratchRegType) const
1043 if (RegType == IntCCRegType)
1045 scratchRegType = IntRegType;
1051 //---------------------------------------------------------------------------
1052 // Copy from a register to register. Register number must be the unified
1054 //---------------------------------------------------------------------------
1057 UltraSparcRegInfo::cpReg2RegMI(vector<MachineInstr*>& mvec,
1060 int RegType) const {
1061 assert( ((int)SrcReg != InvalidRegNum) && ((int)DestReg != InvalidRegNum) &&
1062 "Invalid Register");
1064 MachineInstr * MI = NULL;
1069 if (this->getRegType(DestReg) == IntRegType)
1070 { // copy intCC reg to int reg
1071 // Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR
1072 MI = Create2OperandInstr_Reg(RDCCR, SrcReg+1, DestReg);
1075 { // copy int reg to intCC reg
1076 // Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
1077 assert(this->getRegType(SrcReg) == IntRegType
1078 && "Can only copy CC reg to/from integer reg");
1079 MI = Create2OperandInstr_Reg(WRCCR, SrcReg, DestReg+1);
1083 case FloatCCRegType:
1084 assert(0 && "Cannot copy FPCC register to any other register");
1088 MI = Create3OperandInstr_Reg(ADD, SrcReg, this->getZeroRegNum(), DestReg);
1091 case FPSingleRegType:
1092 MI = Create2OperandInstr_Reg(FMOVS, SrcReg, DestReg);
1095 case FPDoubleRegType:
1096 MI = Create2OperandInstr_Reg(FMOVD, SrcReg, DestReg);
1100 assert(0 && "Unknown RegType");
1108 //---------------------------------------------------------------------------
1109 // Copy from a register to memory (i.e., Store). Register number must
1110 // be the unified register number
1111 //---------------------------------------------------------------------------
1115 UltraSparcRegInfo::cpReg2MemMI(vector<MachineInstr*>& mvec,
1117 unsigned DestPtrReg,
1118 int Offset, int RegType,
1119 int scratchReg = -1) const {
1120 MachineInstr * MI = NULL;
1123 MI = new MachineInstr(STX, 3);
1124 MI->SetMachineOperandReg(0, SrcReg, false);
1125 MI->SetMachineOperandReg(1, DestPtrReg, false);
1126 MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
1131 case FPSingleRegType:
1132 MI = new MachineInstr(ST, 3);
1133 MI->SetMachineOperandReg(0, SrcReg, false);
1134 MI->SetMachineOperandReg(1, DestPtrReg, false);
1135 MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
1140 case FPDoubleRegType:
1141 MI = new MachineInstr(STD, 3);
1142 MI->SetMachineOperandReg(0, SrcReg, false);
1143 MI->SetMachineOperandReg(1, DestPtrReg, false);
1144 MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
1150 assert(scratchReg >= 0 && "Need scratch reg to store %ccr to memory");
1151 assert(this->getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
1153 // Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR
1154 MI = Create2OperandInstr_Reg(RDCCR, SrcReg+1, scratchReg);
1157 this->cpReg2MemMI(mvec, scratchReg, DestPtrReg, Offset, IntRegType);
1160 case FloatCCRegType:
1161 assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here");
1162 MI = new MachineInstr(STXFSR, 3);
1163 MI->SetMachineOperandReg(0, SrcReg, false);
1164 MI->SetMachineOperandReg(1, DestPtrReg, false);
1165 MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
1171 assert(0 && "Unknown RegType in cpReg2MemMI");
1176 //---------------------------------------------------------------------------
1177 // Copy from memory to a reg (i.e., Load) Register number must be the unified
1179 //---------------------------------------------------------------------------
1183 UltraSparcRegInfo::cpMem2RegMI(vector<MachineInstr*>& mvec,
1188 int scratchReg = -1) const {
1189 MachineInstr * MI = NULL;
1192 MI = new MachineInstr(LDX, 3);
1193 MI->SetMachineOperandReg(0, SrcPtrReg, false);
1194 MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
1196 MI->SetMachineOperandReg(2, DestReg, true);
1200 case FPSingleRegType:
1201 MI = new MachineInstr(LD, 3);
1202 MI->SetMachineOperandReg(0, SrcPtrReg, false);
1203 MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
1205 MI->SetMachineOperandReg(2, DestReg, true);
1209 case FPDoubleRegType:
1210 MI = new MachineInstr(LDD, 3);
1211 MI->SetMachineOperandReg(0, SrcPtrReg, false);
1212 MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
1214 MI->SetMachineOperandReg(2, DestReg, true);
1219 assert(scratchReg >= 0 && "Need scratch reg to load %ccr from memory");
1220 assert(this->getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
1221 this->cpMem2RegMI(mvec, SrcPtrReg, Offset, scratchReg, IntRegType);
1223 // Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
1224 MI = Create2OperandInstr_Reg(WRCCR, scratchReg, DestReg+1);
1229 case FloatCCRegType:
1230 assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here");
1231 MI = new MachineInstr(LDXFSR, 3);
1232 MI->SetMachineOperandReg(0, SrcPtrReg, false);
1233 MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
1235 MI->SetMachineOperandReg(2, DestReg, true);
1240 assert(0 && "Unknown RegType in cpMem2RegMI");
1245 //---------------------------------------------------------------------------
1246 // Generate a copy instruction to copy a value to another. Temporarily
1247 // used by PhiElimination code.
1248 //---------------------------------------------------------------------------
1252 UltraSparcRegInfo::cpValue2Value(Value *Src,
1254 vector<MachineInstr*>& mvec) const {
1255 int RegType = getRegType( Src );
1257 assert( (RegType==getRegType(Src)) && "Src & Dest are diff types");
1259 MachineInstr * MI = NULL;
1263 MI = new MachineInstr(ADD, 3);
1264 MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
1265 MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
1266 MI->SetMachineOperandVal(2, MachineOperand:: MO_VirtualRegister, Dest, true);
1269 case FPSingleRegType:
1270 MI = new MachineInstr(FMOVS, 2);
1271 MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
1272 MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true);
1276 case FPDoubleRegType:
1277 MI = new MachineInstr(FMOVD, 2);
1278 MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
1279 MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true);
1283 assert(0 && "Unknow RegType in CpValu2Value");
1295 //----------------------------------------------------------------------------
1296 // This method inserts caller saving/restoring instructons before/after
1297 // a call machine instruction. The caller saving/restoring instructions are
1300 // ** caller saving instructions
1301 // other instructions inserted for the call by ColorCallArg
1303 // other instructions inserted for the call ColorCallArg
1304 // ** caller restoring instructions
1306 //----------------------------------------------------------------------------
1310 UltraSparcRegInfo::insertCallerSavingCode(vector<MachineInstr*>& instrnsBefore,
1311 vector<MachineInstr*>& instrnsAfter,
1312 MachineInstr *CallMI,
1313 const BasicBlock *BB,
1314 PhyRegAlloc &PRA) const
1316 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
1318 // has set to record which registers were saved/restored
1320 hash_set<unsigned> PushedRegSet;
1322 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
1324 // Now find the LR of the return value of the call
1325 // The last *implicit operand* is the return value of a call
1326 // Insert it to to he PushedRegSet since we must not save that register
1327 // and restore it after the call.
1328 // We do this because, we look at the LV set *after* the instruction
1329 // to determine, which LRs must be saved across calls. The return value
1330 // of the call is live in this set - but we must not save/restore it.
1332 const Value *RetVal = argDesc->getReturnValue();
1335 LiveRange *RetValLR = PRA.LRI.getLiveRangeForValue( RetVal );
1336 assert(RetValLR && "No LR for RetValue of call");
1338 if (RetValLR->hasColor())
1339 PushedRegSet.insert(
1340 getUnifiedRegNum((RetValLR->getRegClass())->getID(),
1341 RetValLR->getColor() ) );
1344 const ValueSet &LVSetAft = PRA.LVI->getLiveVarSetAfterMInst(CallMI, BB);
1345 ValueSet::const_iterator LIt = LVSetAft.begin();
1347 // for each live var in live variable set after machine inst
1348 for( ; LIt != LVSetAft.end(); ++LIt) {
1350 // get the live range corresponding to live var
1351 LiveRange *const LR = PRA.LRI.getLiveRangeForValue(*LIt );
1353 // LR can be null if it is a const since a const
1354 // doesn't have a dominating def - see Assumptions above
1357 if( LR->hasColor() ) {
1359 unsigned RCID = (LR->getRegClass())->getID();
1360 unsigned Color = LR->getColor();
1362 if ( isRegVolatile(RCID, Color) ) {
1364 // if the value is in both LV sets (i.e., live before and after
1365 // the call machine instruction)
1367 unsigned Reg = getUnifiedRegNum(RCID, Color);
1369 if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
1371 // if we haven't already pushed that register
1373 unsigned RegType = getRegType( LR );
1375 // Now get two instructions - to push on stack and pop from stack
1376 // and add them to InstrnsBefore and InstrnsAfter of the
1379 int StackOff = PRA.mcInfo.pushTempValue(target,
1380 getSpilledRegSize(RegType));
1382 vector<MachineInstr*> AdIBef, AdIAft;
1384 //---- Insert code for pushing the reg on stack ----------
1386 // We may need a scratch register to copy the saved value
1387 // to/from memory. This may itself have to insert code to
1388 // free up a scratch register. Any such code should go before
1390 int scratchRegType = -1;
1391 int scratchReg = -1;
1392 if (this->regTypeNeedsScratchReg(RegType, scratchRegType))
1393 { // Find a register not live in the LVSet before CallMI
1394 const ValueSet &LVSetBef =
1395 PRA.LVI->getLiveVarSetBeforeMInst(CallMI, BB);
1396 scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetBef,
1397 CallMI, AdIBef, AdIAft);
1398 assert(scratchReg != this->getInvalidRegNum());
1399 CallMI->getRegsUsed().insert(scratchReg);
1402 if (AdIBef.size() > 0)
1403 instrnsBefore.insert(instrnsBefore.end(),
1404 AdIBef.begin(), AdIBef.end());
1406 cpReg2MemMI(instrnsBefore, Reg,getFramePointer(),StackOff,RegType,
1409 if (AdIAft.size() > 0)
1410 instrnsBefore.insert(instrnsBefore.end(),
1411 AdIAft.begin(), AdIAft.end());
1413 //---- Insert code for popping the reg from the stack ----------
1415 // We may need a scratch register to copy the saved value
1416 // from memory. This may itself have to insert code to
1417 // free up a scratch register. Any such code should go
1418 // after the save code.
1420 scratchRegType = -1;
1422 if (this->regTypeNeedsScratchReg(RegType, scratchRegType))
1423 { // Find a register not live in the LVSet after CallMI
1424 scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetAft,
1425 CallMI, AdIBef, AdIAft);
1426 assert(scratchReg != this->getInvalidRegNum());
1427 CallMI->getRegsUsed().insert(scratchReg);
1430 if (AdIBef.size() > 0)
1431 instrnsAfter.insert(instrnsAfter.end(),
1432 AdIBef.begin(), AdIBef.end());
1434 cpMem2RegMI(instrnsAfter, getFramePointer(), StackOff,Reg,RegType,
1437 if (AdIAft.size() > 0)
1438 instrnsAfter.insert(instrnsAfter.end(),
1439 AdIAft.begin(), AdIAft.end());
1441 PushedRegSet.insert(Reg);
1444 cerr << "\nFor call inst:" << *CallMI;
1445 cerr << " -inserted caller saving instrs: Before:\n\t ";
1446 for_each(instrnsBefore.begin(), instrnsBefore.end(),
1447 std::mem_fun(&MachineInstr::dump));
1448 cerr << " -and After:\n\t ";
1449 for_each(instrnsAfter.begin(), instrnsAfter.end(),
1450 std::mem_fun(&MachineInstr::dump));
1452 } // if not already pushed
1454 } // if LR has a volatile color
1456 } // if LR has color
1458 } // if there is a LR for Var
1460 } // for each value in the LV set after instruction
1464 //---------------------------------------------------------------------------
1465 // Print the register assigned to a LR
1466 //---------------------------------------------------------------------------
1468 void UltraSparcRegInfo::printReg(const LiveRange *LR) {
1469 unsigned RegClassID = (LR->getRegClass())->getID();
1470 cerr << " *Node " << (LR->getUserIGNode())->getIndex();
1472 if (!LR->hasColor()) {
1473 cerr << " - could not find a color\n";
1477 // if a color is found
1479 cerr << " colored with color "<< LR->getColor();
1481 if (RegClassID == IntRegClassID) {
1482 cerr<< " [" << SparcIntRegOrder::getRegName(LR->getColor()) << "]\n";
1484 } else if (RegClassID == FloatRegClassID) {
1485 cerr << "[" << SparcFloatRegOrder::getRegName(LR->getColor());
1486 if( LR->getType() == Type::DoubleTy)
1487 cerr << "+" << SparcFloatRegOrder::getRegName(LR->getColor()+1);
1492 //---------------------------------------------------------------------------
1493 // This method examines instructions inserted by RegAlloc code before a
1494 // machine instruction to detect invalid orders that destroy values before
1495 // they are used. If it detects such conditions, it reorders the instructions.
1497 // The unordered instructions come in the UnordVec. These instructions are
1498 // instructions inserted by RegAlloc. All such instruction MUST have
1499 // their USES BEFORE THE DEFS after reordering.
1501 // The UnordVec & OrdVec must be DISTINCT. The OrdVec must be empty when
1502 // this method is called.
1504 // This method uses two vectors for efficiency in accessing
1506 // Since instructions are inserted in RegAlloc, this assumes that the
1507 // first operand is the source reg and the last operand is the dest reg.
1508 // It also does not consider operands that are both use and def.
1510 // All the uses are before THE def to a register
1511 //---------------------------------------------------------------------------
1513 void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr*> &UnordVec,
1514 std::vector<MachineInstr*> &OrdVec,
1515 PhyRegAlloc &PRA) const{
1518 Problem: We can have instructions inserted by RegAlloc like
1520 2. add %oy %g0 %oz, where z!=x or z==x
1522 This is wrong since %oy used by 2 is overwritten by 1
1525 We re-order the instructions so that the uses are before the defs
1530 for each instruction 'DefInst' in the UnOrdVec
1531 for each instruction 'UseInst' that follows the DefInst
1532 if the reg defined by DefInst is used by UseInst
1533 mark DefInst as not movable in this iteration
1534 If DefInst is not marked as not-movable, move DefInst to OrdVec
1535 while all instructions in DefInst are moved to OrdVec
1537 For moving, we call the move2OrdVec(). It checks whether there is a def
1538 in it for the uses in the instruction to be added to OrdVec. If there
1539 are no preceding defs, it just appends the instruction. If there is a
1540 preceding def, it puts two instructions to save the reg on stack before
1541 the load and puts a restore at use.
1546 bool DebugPrint = false;
1549 CouldMoveAll = true;
1550 std::vector<MachineInstr *>::iterator DefIt = UnordVec.begin();
1552 for( ; DefIt != UnordVec.end(); ++DefIt ) {
1554 // for each instruction in the UnordVec do ...
1556 MachineInstr *DefInst = *DefIt;
1558 if( DefInst == NULL) continue;
1560 //cerr << "\nInst in UnordVec = " << *DefInst;
1562 // last operand is the def (unless for a store which has no def reg)
1563 MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
1565 if( DefOp.opIsDef() &&
1566 DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1568 // If the operand in DefInst is a def ...
1570 bool DefEqUse = false;
1572 std::vector<MachineInstr *>::iterator UseIt = DefIt;
1575 for( ; UseIt != UnordVec.end(); ++UseIt ) {
1577 MachineInstr *UseInst = *UseIt;
1578 if( UseInst == NULL) continue;
1580 // for each inst (UseInst) that is below the DefInst do ...
1581 MachineOperand& UseOp = UseInst->getOperand(0);
1583 if( ! UseOp.opIsDef() &&
1584 UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1586 // if use is a register ...
1588 if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
1590 // if Def and this use are the same, it means that this use
1591 // is destroyed by a def before it is used
1593 // cerr << "\nCouldn't move " << *DefInst;
1596 CouldMoveAll = false;
1599 } // if two registers are equal
1601 } // if use is a register
1603 }// for all use instructions
1607 // after examining all the instructions that follow the DefInst
1608 // if there are no dependencies, we can move it to the OrdVec
1610 // cerr << "Moved to Ord: " << *DefInst;
1612 moveInst2OrdVec(OrdVec, DefInst, PRA);
1614 //OrdVec.push_back(DefInst);
1616 // mark the pos of DefInst with NULL to indicate that it is
1621 } // if Def is a machine register
1623 } // for all instructions in the UnordVec
1626 } while(!CouldMoveAll);
1628 if (DebugPrint && DEBUG_RA) {
1629 cerr << "\nAdded instructions were reordered to:\n";
1630 for(unsigned int i=0; i < OrdVec.size(); i++)
1631 cerr << *(OrdVec[i]);
1639 void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
1640 MachineInstr *UnordInst,
1641 PhyRegAlloc &PRA) const {
1642 MachineOperand& UseOp = UnordInst->getOperand(0);
1644 if( ! UseOp.opIsDef() &&
1645 UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1647 // for the use of UnordInst, see whether there is a defining instr
1648 // before in the OrdVec
1649 bool DefEqUse = false;
1651 std::vector<MachineInstr *>::iterator OrdIt = OrdVec.begin();
1653 for( ; OrdIt != OrdVec.end(); ++OrdIt ) {
1655 MachineInstr *OrdInst = *OrdIt ;
1657 MachineOperand& DefOp =
1658 OrdInst->getOperand(OrdInst->getNumOperands()-1);
1660 if( DefOp.opIsDef() &&
1661 DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1663 //cerr << "\nDefining Ord Inst: " << *OrdInst;
1665 if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
1667 // we are here because there is a preceding def in the OrdVec
1668 // for the use in this intr we are going to insert. This
1669 // happened because the original code was like:
1670 // 1. add %ox %g0 %oy
1671 // 2. add %oy %g0 %ox
1672 // In Round1, we added 2 to OrdVec but 1 remained in UnordVec
1673 // Now we are processing %ox of 1.
1676 const int UReg = DefOp.getMachineRegNum();
1677 const int RegType = getRegType(UReg);
1678 MachineInstr *AdIBef, *AdIAft;
1680 const int StackOff = PRA.mcInfo.pushTempValue(target,
1681 getSpilledRegSize(RegType));
1683 // Save the UReg (%ox) on stack before it's destroyed
1684 vector<MachineInstr*> mvec;
1685 cpReg2MemMI(mvec, UReg, getFramePointer(), StackOff, RegType);
1686 for (vector<MachineInstr*>::iterator MI=mvec.begin(); MI != mvec.end(); ++MI) {
1687 OrdIt = OrdVec.insert(OrdIt, *MI);
1688 ++OrdIt; // OrdIt must still point to current instr we processed
1691 // Load directly into DReg (%oy)
1692 MachineOperand& DOp=
1693 (UnordInst->getOperand(UnordInst->getNumOperands()-1));
1694 assert(DOp.opIsDef() && "Last operand is not the def");
1695 const int DReg = DOp.getMachineRegNum();
1697 cpMem2RegMI(OrdVec, getFramePointer(), StackOff, DReg, RegType);
1699 cerr << "\nFixed CIRCULAR references by reordering";
1702 cerr << "\nBefore CIRCULAR Reordering:\n";
1706 cerr << "\nAfter CIRCULAR Reordering - All Inst so far:\n";
1707 for(unsigned i=0; i < OrdVec.size(); i++)
1708 cerr << *(OrdVec[i]);
1711 // Do not copy the UseInst to OrdVec
1715 }// if two registers are equal
1717 } // if Def is a register
1719 } // for each instr in OrdVec
1723 // We didn't find a def in the OrdVec, so just append this inst
1724 OrdVec.push_back( UnordInst );
1725 //cerr << "Reordered Inst (Moved Dn): " << *UnordInst;
1728 }// if the operand in UnordInst is a use