1 //===-- SparcV9RegInfo.cpp - SparcV9 Target Register Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains implementation of SparcV9 specific helper methods
11 // used for register allocation.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFunctionInfo.h"
17 #include "llvm/CodeGen/InstrSelection.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineCodeForInstruction.h"
20 #include "MachineInstrAnnot.h"
21 #include "RegAlloc/LiveRangeInfo.h"
22 #include "RegAlloc/LiveRange.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/iTerminators.h"
26 #include "llvm/iOther.h"
27 #include "SparcV9Internals.h"
28 #include "SparcV9RegClassInfo.h"
29 #include "SparcV9RegInfo.h"
30 #include "SparcV9TargetMachine.h"
38 SparcV9RegInfo::SparcV9RegInfo(const SparcV9TargetMachine &tgt)
39 : TargetRegInfo(tgt), NumOfIntArgRegs(6), NumOfFloatArgRegs(32)
41 MachineRegClassArr.push_back(new SparcV9IntRegClass(IntRegClassID));
42 MachineRegClassArr.push_back(new SparcV9FloatRegClass(FloatRegClassID));
43 MachineRegClassArr.push_back(new SparcV9IntCCRegClass(IntCCRegClassID));
44 MachineRegClassArr.push_back(new SparcV9FloatCCRegClass(FloatCCRegClassID));
45 MachineRegClassArr.push_back(new SparcV9SpecialRegClass(SpecialRegClassID));
47 assert(SparcV9FloatRegClass::StartOfNonVolatileRegs == 32 &&
48 "32 Float regs are used for float arg passing");
52 // getZeroRegNum - returns the register that contains always zero.
53 // this is the unified register number
55 unsigned SparcV9RegInfo::getZeroRegNum() const {
56 return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
57 SparcV9IntRegClass::g0);
60 // getCallAddressReg - returns the reg used for pushing the address when a
61 // method is called. This can be used for other purposes between calls
63 unsigned SparcV9RegInfo::getCallAddressReg() const {
64 return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
65 SparcV9IntRegClass::o7);
68 // Returns the register containing the return address.
69 // It should be made sure that this register contains the return
70 // value when a return instruction is reached.
72 unsigned SparcV9RegInfo::getReturnAddressReg() const {
73 return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
74 SparcV9IntRegClass::i7);
77 // Register get name implementations...
79 // Int register names in same order as enum in class SparcV9IntRegClass
80 static const char * const IntRegNames[] = {
81 "o0", "o1", "o2", "o3", "o4", "o5", "o7",
82 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
83 "i0", "i1", "i2", "i3", "i4", "i5",
85 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
89 const char * const SparcV9IntRegClass::getRegName(unsigned reg) const {
90 assert(reg < NumOfAllRegs);
91 return IntRegNames[reg];
94 static const char * const FloatRegNames[] = {
95 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
96 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
97 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
98 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
99 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
100 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
101 "f60", "f61", "f62", "f63"
104 const char * const SparcV9FloatRegClass::getRegName(unsigned reg) const {
105 assert (reg < NumOfAllRegs);
106 return FloatRegNames[reg];
109 static const char * const IntCCRegNames[] = {
113 const char * const SparcV9IntCCRegClass::getRegName(unsigned reg) const {
115 return IntCCRegNames[reg];
118 static const char * const FloatCCRegNames[] = {
119 "fcc0", "fcc1", "fcc2", "fcc3"
122 const char * const SparcV9FloatCCRegClass::getRegName(unsigned reg) const {
124 return FloatCCRegNames[reg];
127 static const char * const SpecialRegNames[] = {
131 const char * const SparcV9SpecialRegClass::getRegName(unsigned reg) const {
133 return SpecialRegNames[reg];
136 // Get unified reg number for frame pointer
137 unsigned SparcV9RegInfo::getFramePointer() const {
138 return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
139 SparcV9IntRegClass::i6);
142 // Get unified reg number for stack pointer
143 unsigned SparcV9RegInfo::getStackPointer() const {
144 return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
145 SparcV9IntRegClass::o6);
149 //---------------------------------------------------------------------------
150 // Finds whether a call is an indirect call
151 //---------------------------------------------------------------------------
154 isVarArgsFunction(const Type *funcType) {
155 return cast<FunctionType>(cast<PointerType>(funcType)
156 ->getElementType())->isVarArg();
160 isVarArgsCall(const MachineInstr *CallMI) {
161 Value* callee = CallMI->getOperand(0).getVRegValue();
162 // const Type* funcType = isa<Function>(callee)? callee->getType()
163 // : cast<PointerType>(callee->getType())->getElementType();
164 const Type* funcType = callee->getType();
165 return isVarArgsFunction(funcType);
169 // Get the register number for the specified argument #argNo,
172 // getInvalidRegNum(), if there is no int register available for the arg.
173 // regNum, otherwise (this is NOT the unified reg. num).
174 // regClassId is set to the register class ID.
177 SparcV9RegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall,
178 unsigned argNo, unsigned& regClassId) const
180 regClassId = IntRegClassID;
181 if (argNo >= NumOfIntArgRegs)
182 return getInvalidRegNum();
184 return argNo + (inCallee? SparcV9IntRegClass::i0 : SparcV9IntRegClass::o0);
187 // Get the register number for the specified FP argument #argNo,
188 // Use INT regs for FP args if this is a varargs call.
191 // getInvalidRegNum(), if there is no int register available for the arg.
192 // regNum, otherwise (this is NOT the unified reg. num).
193 // regClassId is set to the register class ID.
196 SparcV9RegInfo::regNumForFPArg(unsigned regType,
197 bool inCallee, bool isVarArgsCall,
198 unsigned argNo, unsigned& regClassId) const
201 return regNumForIntArg(inCallee, isVarArgsCall, argNo, regClassId);
204 regClassId = FloatRegClassID;
205 if (regType == FPSingleRegType)
206 return (argNo*2+1 >= NumOfFloatArgRegs)?
207 getInvalidRegNum() : SparcV9FloatRegClass::f0 + (argNo * 2 + 1);
208 else if (regType == FPDoubleRegType)
209 return (argNo*2 >= NumOfFloatArgRegs)?
210 getInvalidRegNum() : SparcV9FloatRegClass::f0 + (argNo * 2);
212 assert(0 && "Illegal FP register type");
218 //---------------------------------------------------------------------------
219 // Finds the return address of a call sparc specific call instruction
220 //---------------------------------------------------------------------------
222 // The following 4 methods are used to find the RegType (SparcV9Internals.h)
223 // of a LiveRange, a Value, and for a given register unified reg number.
225 int SparcV9RegInfo::getRegTypeForClassAndType(unsigned regClassID,
226 const Type* type) const
228 switch (regClassID) {
229 case IntRegClassID: return IntRegType;
230 case FloatRegClassID:
231 if (type == Type::FloatTy) return FPSingleRegType;
232 else if (type == Type::DoubleTy) return FPDoubleRegType;
233 assert(0 && "Unknown type in FloatRegClass"); return 0;
234 case IntCCRegClassID: return IntCCRegType;
235 case FloatCCRegClassID: return FloatCCRegType;
236 case SpecialRegClassID: return SpecialRegType;
237 default: assert( 0 && "Unknown reg class ID"); return 0;
241 int SparcV9RegInfo::getRegTypeForDataType(const Type* type) const
243 return getRegTypeForClassAndType(getRegClassIDOfType(type), type);
246 int SparcV9RegInfo::getRegTypeForLR(const LiveRange *LR) const
248 return getRegTypeForClassAndType(LR->getRegClassID(), LR->getType());
251 int SparcV9RegInfo::getRegType(int unifiedRegNum) const
253 if (unifiedRegNum < 32)
255 else if (unifiedRegNum < (32 + 32))
256 return FPSingleRegType;
257 else if (unifiedRegNum < (64 + 32))
258 return FPDoubleRegType;
259 else if (unifiedRegNum < (64+32+4))
260 return FloatCCRegType;
261 else if (unifiedRegNum < (64+32+4+2))
264 assert(0 && "Invalid unified register number in getRegType");
269 // To find the register class used for a specified Type
271 unsigned SparcV9RegInfo::getRegClassIDOfType(const Type *type,
272 bool isCCReg) const {
273 Type::PrimitiveID ty = type->getPrimitiveID();
276 // FIXME: Comparing types like this isn't very safe...
277 if ((ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
278 (ty == Type::FunctionTyID) || (ty == Type::PointerTyID) )
279 res = IntRegClassID; // sparc int reg (ty=0: void)
280 else if (ty <= Type::DoubleTyID)
281 res = FloatRegClassID; // sparc float reg class
283 //std::cerr << "TypeID: " << ty << "\n";
284 assert(0 && "Cannot resolve register class for type");
289 return res + 2; // corresponding condition code register
294 unsigned SparcV9RegInfo::getRegClassIDOfRegType(int regType) const {
296 case IntRegType: return IntRegClassID;
297 case FPSingleRegType:
298 case FPDoubleRegType: return FloatRegClassID;
299 case IntCCRegType: return IntCCRegClassID;
300 case FloatCCRegType: return FloatCCRegClassID;
302 assert(0 && "Invalid register type in getRegClassIDOfRegType");
307 //---------------------------------------------------------------------------
308 // Suggests a register for the ret address in the RET machine instruction.
309 // We always suggest %i7 by convention.
310 //---------------------------------------------------------------------------
311 void SparcV9RegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
312 LiveRangeInfo& LRI) const {
314 assert(target.getInstrInfo().isReturn(RetMI->getOpcode()));
316 // return address is always mapped to i7 so set it immediately
317 RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID,
318 SparcV9IntRegClass::i7));
320 // Possible Optimization:
321 // Instead of setting the color, we can suggest one. In that case,
322 // we have to test later whether it received the suggested color.
323 // In that case, a LR has to be created at the start of method.
324 // It has to be done as follows (remove the setRegVal above):
326 // MachineOperand & MO = RetMI->getOperand(0);
327 // const Value *RetAddrVal = MO.getVRegValue();
328 // assert( RetAddrVal && "LR for ret address must be created at start");
329 // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
330 // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
331 // SparcV9IntRegOrdr::i7) );
335 //---------------------------------------------------------------------------
336 // Suggests a register for the ret address in the JMPL/CALL machine instr.
337 // SparcV9 ABI dictates that %o7 be used for this purpose.
338 //---------------------------------------------------------------------------
340 SparcV9RegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
341 LiveRangeInfo& LRI) const
343 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
344 const Value *RetAddrVal = argDesc->getReturnAddrReg();
345 assert(RetAddrVal && "INTERNAL ERROR: Return address value is required");
347 // A LR must already exist for the return address.
348 LiveRange *RetAddrLR = LRI.getLiveRangeForValue(RetAddrVal);
349 assert(RetAddrLR && "INTERNAL ERROR: No LR for return address of call!");
351 unsigned RegClassID = RetAddrLR->getRegClassID();
352 RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID, SparcV9IntRegClass::o7));
357 //---------------------------------------------------------------------------
358 // This method will suggest colors to incoming args to a method.
359 // According to the SparcV9 ABI, the first 6 incoming args are in
360 // %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float).
361 // If the arg is passed on stack due to the lack of regs, NOTHING will be
362 // done - it will be colored (or spilled) as a normal live range.
363 //---------------------------------------------------------------------------
364 void SparcV9RegInfo::suggestRegs4MethodArgs(const Function *Meth,
365 LiveRangeInfo& LRI) const
367 // Check if this is a varArgs function. needed for choosing regs.
368 bool isVarArgs = isVarArgsFunction(Meth->getType());
370 // Count the arguments, *ignoring* whether they are int or FP args.
371 // Use this common arg numbering to pick the right int or fp register.
373 for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend();
374 I != E; ++I, ++argNo) {
375 LiveRange *LR = LRI.getLiveRangeForValue(I);
376 assert(LR && "No live range found for method arg");
378 unsigned regType = getRegTypeForLR(LR);
379 unsigned regClassIDOfArgReg = BadRegClass; // for chosen reg (unused)
381 int regNum = (regType == IntRegType)
382 ? regNumForIntArg(/*inCallee*/ true, isVarArgs, argNo, regClassIDOfArgReg)
383 : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs, argNo,
386 if (regNum != getInvalidRegNum())
387 LR->setSuggestedColor(regNum);
392 //---------------------------------------------------------------------------
393 // This method is called after graph coloring to move incoming args to
394 // the correct hardware registers if they did not receive the correct
395 // (suggested) color through graph coloring.
396 //---------------------------------------------------------------------------
397 void SparcV9RegInfo::colorMethodArgs(const Function *Meth,
399 std::vector<MachineInstr*>& InstrnsBefore,
400 std::vector<MachineInstr*>& InstrnsAfter) const {
402 // check if this is a varArgs function. needed for choosing regs.
403 bool isVarArgs = isVarArgsFunction(Meth->getType());
407 // for each argument. count INT and FP arguments separately.
408 unsigned argNo=0, intArgNo=0, fpArgNo=0;
409 for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend();
410 I != E; ++I, ++argNo) {
412 LiveRange *LR = LRI.getLiveRangeForValue(I);
413 assert( LR && "No live range found for method arg");
415 unsigned regType = getRegTypeForLR(LR);
416 unsigned RegClassID = LR->getRegClassID();
418 // Find whether this argument is coming in a register (if not, on stack)
419 // Also find the correct register the argument must use (UniArgReg)
421 bool isArgInReg = false;
422 unsigned UniArgReg = getInvalidRegNum(); // reg that LR MUST be colored with
423 unsigned regClassIDOfArgReg = BadRegClass; // reg class of chosen reg
425 int regNum = (regType == IntRegType)
426 ? regNumForIntArg(/*inCallee*/ true, isVarArgs,
427 argNo, regClassIDOfArgReg)
428 : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs,
429 argNo, regClassIDOfArgReg);
431 if(regNum != getInvalidRegNum()) {
433 UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum);
436 if( ! LR->isMarkedForSpill() ) { // if this arg received a register
438 unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
440 // if LR received the correct color, nothing to do
442 if( UniLRReg == UniArgReg )
445 // We are here because the LR did not receive the suggested
446 // but LR received another register.
447 // Now we have to copy the %i reg (or stack pos of arg)
448 // to the register the LR was colored with.
450 // if the arg is coming in UniArgReg register, it MUST go into
451 // the UniLRReg register
454 if( regClassIDOfArgReg != RegClassID ) {
455 assert(0 && "This could should work but it is not tested yet");
457 // It is a variable argument call: the float reg must go in a %o reg.
458 // We have to move an int reg to a float reg via memory.
461 RegClassID == FloatRegClassID &&
462 regClassIDOfArgReg == IntRegClassID &&
463 "This should only be an Int register for an FP argument");
465 int TmpOff = MachineFunction::get(Meth).getInfo()->pushTempValue(
466 getSpilledRegSize(regType));
467 cpReg2MemMI(InstrnsBefore,
468 UniArgReg, getFramePointer(), TmpOff, IntRegType);
470 cpMem2RegMI(InstrnsBefore,
471 getFramePointer(), TmpOff, UniLRReg, regType);
474 cpReg2RegMI(InstrnsBefore, UniArgReg, UniLRReg, regType);
479 // Now the arg is coming on stack. Since the LR received a register,
480 // we just have to load the arg on stack into that register
482 const TargetFrameInfo& frameInfo = target.getFrameInfo();
484 frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
487 // float arguments on stack are right justified so adjust the offset!
488 // int arguments are also right justified but they are always loaded as
489 // a full double-word so the offset does not need to be adjusted.
490 if (regType == FPSingleRegType) {
491 unsigned argSize = target.getTargetData().getTypeSize(LR->getType());
492 unsigned slotSize = frameInfo.getSizeOfEachArgOnStack();
493 assert(argSize <= slotSize && "Insufficient slot size!");
494 offsetFromFP += slotSize - argSize;
497 cpMem2RegMI(InstrnsBefore,
498 getFramePointer(), offsetFromFP, UniLRReg, regType);
501 } // if LR received a color
505 // Now, the LR did not receive a color. But it has a stack offset for
507 // So, if the arg is coming in UniArgReg register, we can just move
508 // that on to the stack pos of LR
512 if( regClassIDOfArgReg != RegClassID ) {
514 "FP arguments to a varargs function should be explicitly "
515 "copied to/from int registers by instruction selection!");
517 // It must be a float arg for a variable argument call, which
518 // must come in a %o reg. Move the int reg to the stack.
520 assert(isVarArgs && regClassIDOfArgReg == IntRegClassID &&
521 "This should only be an Int register for an FP argument");
523 cpReg2MemMI(InstrnsBefore, UniArgReg,
524 getFramePointer(), LR->getSpillOffFromFP(), IntRegType);
527 cpReg2MemMI(InstrnsBefore, UniArgReg,
528 getFramePointer(), LR->getSpillOffFromFP(), regType);
534 // Now the arg is coming on stack. Since the LR did NOT
535 // received a register as well, it is allocated a stack position. We
536 // can simply change the stack position of the LR. We can do this,
537 // since this method is called before any other method that makes
538 // uses of the stack pos of the LR (e.g., updateMachineInstr)
540 const TargetFrameInfo& frameInfo = target.getFrameInfo();
542 frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
545 // FP arguments on stack are right justified so adjust offset!
546 // int arguments are also right justified but they are always loaded as
547 // a full double-word so the offset does not need to be adjusted.
548 if (regType == FPSingleRegType) {
549 unsigned argSize = target.getTargetData().getTypeSize(LR->getType());
550 unsigned slotSize = frameInfo.getSizeOfEachArgOnStack();
551 assert(argSize <= slotSize && "Insufficient slot size!");
552 offsetFromFP += slotSize - argSize;
555 LR->modifySpillOffFromFP( offsetFromFP );
560 } // for each incoming argument
566 //---------------------------------------------------------------------------
567 // This method is called before graph coloring to suggest colors to the
568 // outgoing call args and the return value of the call.
569 //---------------------------------------------------------------------------
570 void SparcV9RegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
571 LiveRangeInfo& LRI) const {
572 assert ( (target.getInstrInfo()).isCall(CallMI->getOpcode()) );
574 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
576 suggestReg4CallAddr(CallMI, LRI);
578 // First color the return value of the call instruction, if any.
579 // The return value will be in %o0 if the value is an integer type,
580 // or in %f0 if the value is a float type.
582 if (const Value *RetVal = argDesc->getReturnValue()) {
583 LiveRange *RetValLR = LRI.getLiveRangeForValue(RetVal);
584 assert(RetValLR && "No LR for return Value of call!");
586 unsigned RegClassID = RetValLR->getRegClassID();
588 // now suggest a register depending on the register class of ret arg
589 if( RegClassID == IntRegClassID )
590 RetValLR->setSuggestedColor(SparcV9IntRegClass::o0);
591 else if (RegClassID == FloatRegClassID )
592 RetValLR->setSuggestedColor(SparcV9FloatRegClass::f0 );
593 else assert( 0 && "Unknown reg class for return value of call\n");
596 // Now suggest colors for arguments (operands) of the call instruction.
597 // Colors are suggested only if the arg number is smaller than the
598 // the number of registers allocated for argument passing.
599 // Now, go thru call args - implicit operands of the call MI
601 unsigned NumOfCallArgs = argDesc->getNumArgs();
603 for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0;
604 i < NumOfCallArgs; ++i, ++argNo) {
606 const Value *CallArg = argDesc->getArgInfo(i).getArgVal();
608 // get the LR of call operand (parameter)
609 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
611 continue; // no live ranges for constants and labels
613 unsigned regType = getRegTypeForLR(LR);
614 unsigned regClassIDOfArgReg = BadRegClass; // chosen reg class (unused)
616 // Choose a register for this arg depending on whether it is
617 // an INT or FP value. Here we ignore whether or not it is a
618 // varargs calls, because FP arguments will be explicitly copied
619 // to an integer Value and handled under (argCopy != NULL) below.
620 int regNum = (regType == IntRegType)
621 ? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false,
622 argNo, regClassIDOfArgReg)
623 : regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false,
624 argNo, regClassIDOfArgReg);
626 // If a register could be allocated, use it.
627 // If not, do NOTHING as this will be colored as a normal value.
628 if(regNum != getInvalidRegNum())
629 LR->setSuggestedColor(regNum);
630 } // for all call arguments
634 //---------------------------------------------------------------------------
635 // this method is called for an LLVM return instruction to identify which
636 // values will be returned from this method and to suggest colors.
637 //---------------------------------------------------------------------------
638 void SparcV9RegInfo::suggestReg4RetValue(MachineInstr *RetMI,
639 LiveRangeInfo& LRI) const {
641 assert( (target.getInstrInfo()).isReturn( RetMI->getOpcode() ) );
643 suggestReg4RetAddr(RetMI, LRI);
645 // To find the return value (if any), we can get the LLVM return instr.
646 // from the return address register, which is the first operand
647 Value* tmpI = RetMI->getOperand(0).getVRegValue();
648 ReturnInst* retI=cast<ReturnInst>(cast<TmpInstruction>(tmpI)->getOperand(0));
649 if (const Value *RetVal = retI->getReturnValue())
650 if (LiveRange *const LR = LRI.getLiveRangeForValue(RetVal))
651 LR->setSuggestedColor(LR->getRegClassID() == IntRegClassID
652 ? (unsigned) SparcV9IntRegClass::i0
653 : (unsigned) SparcV9FloatRegClass::f0);
656 //---------------------------------------------------------------------------
657 // Check if a specified register type needs a scratch register to be
658 // copied to/from memory. If it does, the reg. type that must be used
659 // for scratch registers is returned in scratchRegType.
661 // Only the int CC register needs such a scratch register.
662 // The FP CC registers can (and must) be copied directly to/from memory.
663 //---------------------------------------------------------------------------
666 SparcV9RegInfo::regTypeNeedsScratchReg(int RegType,
667 int& scratchRegType) const
669 if (RegType == IntCCRegType)
671 scratchRegType = IntRegType;
677 //---------------------------------------------------------------------------
678 // Copy from a register to register. Register number must be the unified
680 //---------------------------------------------------------------------------
683 SparcV9RegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
687 assert( ((int)SrcReg != getInvalidRegNum()) &&
688 ((int)DestReg != getInvalidRegNum()) &&
691 MachineInstr * MI = NULL;
696 if (getRegType(DestReg) == IntRegType) {
697 // copy intCC reg to int reg
698 MI = (BuildMI(V9::RDCCR, 2)
699 .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
700 SparcV9IntCCRegClass::ccr))
701 .addMReg(DestReg,MachineOperand::Def));
703 // copy int reg to intCC reg
704 assert(getRegType(SrcReg) == IntRegType
705 && "Can only copy CC reg to/from integer reg");
706 MI = (BuildMI(V9::WRCCRr, 3)
708 .addMReg(SparcV9IntRegClass::g0)
709 .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
710 SparcV9IntCCRegClass::ccr),
711 MachineOperand::Def));
716 assert(0 && "Cannot copy FPCC register to any other register");
720 MI = BuildMI(V9::ADDr, 3).addMReg(SrcReg).addMReg(getZeroRegNum())
721 .addMReg(DestReg, MachineOperand::Def);
724 case FPSingleRegType:
725 MI = BuildMI(V9::FMOVS, 2).addMReg(SrcReg)
726 .addMReg(DestReg, MachineOperand::Def);
729 case FPDoubleRegType:
730 MI = BuildMI(V9::FMOVD, 2).addMReg(SrcReg)
731 .addMReg(DestReg, MachineOperand::Def);
735 assert(0 && "Unknown RegType");
743 //---------------------------------------------------------------------------
744 // Copy from a register to memory (i.e., Store). Register number must
745 // be the unified register number
746 //---------------------------------------------------------------------------
750 SparcV9RegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
753 int Offset, int RegType,
754 int scratchReg) const {
755 MachineInstr * MI = NULL;
758 // If the Offset will not fit in the signed-immediate field, find an
759 // unused register to hold the offset value. This takes advantage of
760 // the fact that all the opcodes used below have the same size immed. field.
761 // Use the register allocator, PRA, to find an unused reg. at this MI.
763 if (RegType != IntCCRegType) // does not use offset below
764 if (! target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset)) {
765 #ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY
766 RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
767 OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
769 // Default to using register g4 for holding large offsets
770 OffReg = getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
771 SparcV9IntRegClass::g4);
773 assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg.");
774 mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg));
779 if (target.getInstrInfo().constantFitsInImmedField(V9::STXi, Offset))
780 MI = BuildMI(V9::STXi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
782 MI = BuildMI(V9::STXr,3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg);
785 case FPSingleRegType:
786 if (target.getInstrInfo().constantFitsInImmedField(V9::STFi, Offset))
787 MI = BuildMI(V9::STFi, 3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
789 MI = BuildMI(V9::STFr, 3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg);
792 case FPDoubleRegType:
793 if (target.getInstrInfo().constantFitsInImmedField(V9::STDFi, Offset))
794 MI = BuildMI(V9::STDFi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
796 MI = BuildMI(V9::STDFr,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(OffReg);
800 assert(scratchReg >= 0 && "Need scratch reg to store %ccr to memory");
801 assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
802 MI = (BuildMI(V9::RDCCR, 2)
803 .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
804 SparcV9IntCCRegClass::ccr))
805 .addMReg(scratchReg, MachineOperand::Def));
808 cpReg2MemMI(mvec, scratchReg, PtrReg, Offset, IntRegType);
811 case SpecialRegType: // used only for %fsr itself.
812 case FloatCCRegType: {
813 unsigned fsrReg = getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID,
814 SparcV9SpecialRegClass::fsr);
815 if (target.getInstrInfo().constantFitsInImmedField(V9::STXFSRi, Offset))
816 MI=BuildMI(V9::STXFSRi,3).addMReg(fsrReg).addMReg(PtrReg).addSImm(Offset);
818 MI=BuildMI(V9::STXFSRr,3).addMReg(fsrReg).addMReg(PtrReg).addMReg(OffReg);
822 assert(0 && "Unknown RegType in cpReg2MemMI");
828 //---------------------------------------------------------------------------
829 // Copy from memory to a reg (i.e., Load) Register number must be the unified
831 //---------------------------------------------------------------------------
835 SparcV9RegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
840 int scratchReg) const {
841 MachineInstr * MI = NULL;
844 // If the Offset will not fit in the signed-immediate field, find an
845 // unused register to hold the offset value. This takes advantage of
846 // the fact that all the opcodes used below have the same size immed. field.
847 // Use the register allocator, PRA, to find an unused reg. at this MI.
849 if (RegType != IntCCRegType) // does not use offset below
850 if (! target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset)) {
851 #ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY
852 RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
853 OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
855 // Default to using register g4 for holding large offsets
856 OffReg = getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
857 SparcV9IntRegClass::g4);
859 assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg.");
860 mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg));
865 if (target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset))
866 MI = BuildMI(V9::LDXi, 3).addMReg(PtrReg).addSImm(Offset)
867 .addMReg(DestReg, MachineOperand::Def);
869 MI = BuildMI(V9::LDXr, 3).addMReg(PtrReg).addMReg(OffReg)
870 .addMReg(DestReg, MachineOperand::Def);
873 case FPSingleRegType:
874 if (target.getInstrInfo().constantFitsInImmedField(V9::LDFi, Offset))
875 MI = BuildMI(V9::LDFi, 3).addMReg(PtrReg).addSImm(Offset)
876 .addMReg(DestReg, MachineOperand::Def);
878 MI = BuildMI(V9::LDFr, 3).addMReg(PtrReg).addMReg(OffReg)
879 .addMReg(DestReg, MachineOperand::Def);
882 case FPDoubleRegType:
883 if (target.getInstrInfo().constantFitsInImmedField(V9::LDDFi, Offset))
884 MI= BuildMI(V9::LDDFi, 3).addMReg(PtrReg).addSImm(Offset)
885 .addMReg(DestReg, MachineOperand::Def);
887 MI= BuildMI(V9::LDDFr, 3).addMReg(PtrReg).addMReg(OffReg)
888 .addMReg(DestReg, MachineOperand::Def);
892 assert(scratchReg >= 0 && "Need scratch reg to load %ccr from memory");
893 assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
894 cpMem2RegMI(mvec, PtrReg, Offset, scratchReg, IntRegType);
895 MI = (BuildMI(V9::WRCCRr, 3)
897 .addMReg(SparcV9IntRegClass::g0)
898 .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
899 SparcV9IntCCRegClass::ccr), MachineOperand::Def));
902 case SpecialRegType: // used only for %fsr itself
903 case FloatCCRegType: {
904 unsigned fsrRegNum = getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID,
905 SparcV9SpecialRegClass::fsr);
906 if (target.getInstrInfo().constantFitsInImmedField(V9::LDXFSRi, Offset))
907 MI = BuildMI(V9::LDXFSRi, 3).addMReg(PtrReg).addSImm(Offset)
908 .addMReg(fsrRegNum, MachineOperand::UseAndDef);
910 MI = BuildMI(V9::LDXFSRr, 3).addMReg(PtrReg).addMReg(OffReg)
911 .addMReg(fsrRegNum, MachineOperand::UseAndDef);
915 assert(0 && "Unknown RegType in cpMem2RegMI");
921 //---------------------------------------------------------------------------
922 // Generate a copy instruction to copy a value to another. Temporarily
923 // used by PhiElimination code.
924 //---------------------------------------------------------------------------
928 SparcV9RegInfo::cpValue2Value(Value *Src, Value *Dest,
929 std::vector<MachineInstr*>& mvec) const {
930 int RegType = getRegTypeForDataType(Src->getType());
931 MachineInstr * MI = NULL;
935 MI = BuildMI(V9::ADDr, 3).addReg(Src).addMReg(getZeroRegNum())
938 case FPSingleRegType:
939 MI = BuildMI(V9::FMOVS, 2).addReg(Src).addRegDef(Dest);
941 case FPDoubleRegType:
942 MI = BuildMI(V9::FMOVD, 2).addReg(Src).addRegDef(Dest);
945 assert(0 && "Unknow RegType in CpValu2Value");
953 //---------------------------------------------------------------------------
954 // Print the register assigned to a LR
955 //---------------------------------------------------------------------------
957 void SparcV9RegInfo::printReg(const LiveRange *LR) const {
958 unsigned RegClassID = LR->getRegClassID();
959 std::cerr << " Node ";
961 if (!LR->hasColor()) {
962 std::cerr << " - could not find a color\n";
966 // if a color is found
968 std::cerr << " colored with color "<< LR->getColor();
970 unsigned uRegName = getUnifiedRegNum(RegClassID, LR->getColor());
973 std::cerr<< getUnifiedRegName(uRegName);
974 if (RegClassID == FloatRegClassID && LR->getType() == Type::DoubleTy)
975 std::cerr << "+" << getUnifiedRegName(uRegName+1);
979 } // End llvm namespace