1 //===-- SparcRegInfo.cpp - Sparc Target Register Information --------------===//
3 // This file contains implementation of Sparc specific helper methods
4 // used for register allocation.
6 //===----------------------------------------------------------------------===//
8 #include "SparcInternals.h"
9 #include "SparcRegClassInfo.h"
10 #include "llvm/CodeGen/MachineFunction.h"
11 #include "llvm/CodeGen/MachineFunctionInfo.h"
12 #include "llvm/CodeGen/InstrSelection.h"
13 #include "llvm/CodeGen/MachineInstrBuilder.h"
14 #include "llvm/CodeGen/MachineCodeForInstruction.h"
15 #include "llvm/CodeGen/MachineInstrAnnot.h"
16 #include "llvm/CodeGen/LiveRangeInfo.h"
17 #include "llvm/iTerminators.h"
18 #include "llvm/iOther.h"
19 #include "llvm/Function.h"
20 #include "llvm/DerivedTypes.h"
26 UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
27 : TargetRegInfo(tgt), NumOfIntArgRegs(6), NumOfFloatArgRegs(32)
29 MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID));
30 MachineRegClassArr.push_back(new SparcFloatRegClass(FloatRegClassID));
31 MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID));
32 MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID));
33 MachineRegClassArr.push_back(new SparcSpecialRegClass(SpecialRegClassID));
35 assert(SparcFloatRegClass::StartOfNonVolatileRegs == 32 &&
36 "32 Float regs are used for float arg passing");
40 // getZeroRegNum - returns the register that contains always zero.
41 // this is the unified register number
43 int UltraSparcRegInfo::getZeroRegNum() const {
44 return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
45 SparcIntRegClass::g0);
48 // getCallAddressReg - returns the reg used for pushing the address when a
49 // method is called. This can be used for other purposes between calls
51 unsigned UltraSparcRegInfo::getCallAddressReg() const {
52 return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
53 SparcIntRegClass::o7);
56 // Returns the register containing the return address.
57 // It should be made sure that this register contains the return
58 // value when a return instruction is reached.
60 unsigned UltraSparcRegInfo::getReturnAddressReg() const {
61 return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
62 SparcIntRegClass::i7);
65 // Register get name implementations...
67 // Int register names in same order as enum in class SparcIntRegClass
68 static const char * const IntRegNames[] = {
69 "o0", "o1", "o2", "o3", "o4", "o5", "o7",
70 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
71 "i0", "i1", "i2", "i3", "i4", "i5",
73 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
77 const char * const SparcIntRegClass::getRegName(unsigned reg) const {
78 assert(reg < NumOfAllRegs);
79 return IntRegNames[reg];
82 static const char * const FloatRegNames[] = {
83 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
84 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
85 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
86 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
87 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
88 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
89 "f60", "f61", "f62", "f63"
92 const char * const SparcFloatRegClass::getRegName(unsigned reg) const {
93 assert (reg < NumOfAllRegs);
94 return FloatRegNames[reg];
98 static const char * const IntCCRegNames[] = {
102 const char * const SparcIntCCRegClass::getRegName(unsigned reg) const {
104 return IntCCRegNames[reg];
107 static const char * const FloatCCRegNames[] = {
108 "fcc0", "fcc1", "fcc2", "fcc3"
111 const char * const SparcFloatCCRegClass::getRegName(unsigned reg) const {
113 return FloatCCRegNames[reg];
116 static const char * const SpecialRegNames[] = {
120 const char * const SparcSpecialRegClass::getRegName(unsigned reg) const {
122 return SpecialRegNames[reg];
125 // Get unified reg number for frame pointer
126 unsigned UltraSparcRegInfo::getFramePointer() const {
127 return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
128 SparcIntRegClass::i6);
131 // Get unified reg number for stack pointer
132 unsigned UltraSparcRegInfo::getStackPointer() const {
133 return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
134 SparcIntRegClass::o6);
138 //---------------------------------------------------------------------------
139 // Finds whether a call is an indirect call
140 //---------------------------------------------------------------------------
143 isVarArgsFunction(const Type *funcType) {
144 return cast<FunctionType>(cast<PointerType>(funcType)
145 ->getElementType())->isVarArg();
149 isVarArgsCall(const MachineInstr *CallMI) {
150 Value* callee = CallMI->getOperand(0).getVRegValue();
151 // const Type* funcType = isa<Function>(callee)? callee->getType()
152 // : cast<PointerType>(callee->getType())->getElementType();
153 const Type* funcType = callee->getType();
154 return isVarArgsFunction(funcType);
158 // Get the register number for the specified argument #argNo,
161 // getInvalidRegNum(), if there is no int register available for the arg.
162 // regNum, otherwise (this is NOT the unified reg. num).
163 // regClassId is set to the register class ID.
166 UltraSparcRegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall,
167 unsigned argNo, unsigned& regClassId) const
169 regClassId = IntRegClassID;
170 if (argNo >= NumOfIntArgRegs)
171 return getInvalidRegNum();
173 return argNo + (inCallee? SparcIntRegClass::i0 : SparcIntRegClass::o0);
176 // Get the register number for the specified FP argument #argNo,
177 // Use INT regs for FP args if this is a varargs call.
180 // getInvalidRegNum(), if there is no int register available for the arg.
181 // regNum, otherwise (this is NOT the unified reg. num).
182 // regClassId is set to the register class ID.
185 UltraSparcRegInfo::regNumForFPArg(unsigned regType,
186 bool inCallee, bool isVarArgsCall,
187 unsigned argNo, unsigned& regClassId) const
190 return regNumForIntArg(inCallee, isVarArgsCall, argNo, regClassId);
193 regClassId = FloatRegClassID;
194 if (regType == FPSingleRegType)
195 return (argNo*2+1 >= NumOfFloatArgRegs)?
196 getInvalidRegNum() : SparcFloatRegClass::f0 + (argNo * 2 + 1);
197 else if (regType == FPDoubleRegType)
198 return (argNo*2 >= NumOfFloatArgRegs)?
199 getInvalidRegNum() : SparcFloatRegClass::f0 + (argNo * 2);
201 assert(0 && "Illegal FP register type");
207 //---------------------------------------------------------------------------
208 // Finds the return address of a call sparc specific call instruction
209 //---------------------------------------------------------------------------
211 // The following 4 methods are used to find the RegType (SparcInternals.h)
212 // of a LiveRange, a Value, and for a given register unified reg number.
214 int UltraSparcRegInfo::getRegTypeForClassAndType(unsigned regClassID,
215 const Type* type) const
217 switch (regClassID) {
218 case IntRegClassID: return IntRegType;
219 case FloatRegClassID:
220 if (type == Type::FloatTy) return FPSingleRegType;
221 else if (type == Type::DoubleTy) return FPDoubleRegType;
222 assert(0 && "Unknown type in FloatRegClass"); return 0;
223 case IntCCRegClassID: return IntCCRegType;
224 case FloatCCRegClassID: return FloatCCRegType;
225 case SpecialRegClassID: return SpecialRegType;
226 default: assert( 0 && "Unknown reg class ID"); return 0;
230 int UltraSparcRegInfo::getRegTypeForDataType(const Type* type) const
232 return getRegTypeForClassAndType(getRegClassIDOfType(type), type);
235 int UltraSparcRegInfo::getRegTypeForLR(const LiveRange *LR) const
237 return getRegTypeForClassAndType(LR->getRegClassID(), LR->getType());
240 int UltraSparcRegInfo::getRegType(int unifiedRegNum) const
242 if (unifiedRegNum < 32)
244 else if (unifiedRegNum < (32 + 32))
245 return FPSingleRegType;
246 else if (unifiedRegNum < (64 + 32))
247 return FPDoubleRegType;
248 else if (unifiedRegNum < (64+32+4))
249 return FloatCCRegType;
250 else if (unifiedRegNum < (64+32+4+2))
253 assert(0 && "Invalid unified register number in getRegType");
258 // To find the register class used for a specified Type
260 unsigned UltraSparcRegInfo::getRegClassIDOfType(const Type *type,
261 bool isCCReg) const {
262 Type::PrimitiveID ty = type->getPrimitiveID();
265 // FIXME: Comparing types like this isn't very safe...
266 if ((ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
267 (ty == Type::FunctionTyID) || (ty == Type::PointerTyID) )
268 res = IntRegClassID; // sparc int reg (ty=0: void)
269 else if (ty <= Type::DoubleTyID)
270 res = FloatRegClassID; // sparc float reg class
272 //std::cerr << "TypeID: " << ty << "\n";
273 assert(0 && "Cannot resolve register class for type");
278 return res + 2; // corresponding condition code register
283 unsigned UltraSparcRegInfo::getRegClassIDOfRegType(int regType) const {
285 case IntRegType: return IntRegClassID;
286 case FPSingleRegType:
287 case FPDoubleRegType: return FloatRegClassID;
288 case IntCCRegType: return IntCCRegClassID;
289 case FloatCCRegType: return FloatCCRegClassID;
291 assert(0 && "Invalid register type in getRegClassIDOfRegType");
296 //---------------------------------------------------------------------------
297 // Suggests a register for the ret address in the RET machine instruction.
298 // We always suggest %i7 by convention.
299 //---------------------------------------------------------------------------
300 void UltraSparcRegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
301 LiveRangeInfo& LRI) const {
303 assert(target.getInstrInfo().isReturn(RetMI->getOpCode()));
305 // return address is always mapped to i7 so set it immediately
306 RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID,
307 SparcIntRegClass::i7));
309 // Possible Optimization:
310 // Instead of setting the color, we can suggest one. In that case,
311 // we have to test later whether it received the suggested color.
312 // In that case, a LR has to be created at the start of method.
313 // It has to be done as follows (remove the setRegVal above):
315 // MachineOperand & MO = RetMI->getOperand(0);
316 // const Value *RetAddrVal = MO.getVRegValue();
317 // assert( RetAddrVal && "LR for ret address must be created at start");
318 // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
319 // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
320 // SparcIntRegOrdr::i7) );
324 //---------------------------------------------------------------------------
325 // Suggests a register for the ret address in the JMPL/CALL machine instr.
326 // Sparc ABI dictates that %o7 be used for this purpose.
327 //---------------------------------------------------------------------------
329 UltraSparcRegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
330 LiveRangeInfo& LRI) const
332 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
333 const Value *RetAddrVal = argDesc->getReturnAddrReg();
334 assert(RetAddrVal && "INTERNAL ERROR: Return address value is required");
336 // A LR must already exist for the return address.
337 LiveRange *RetAddrLR = LRI.getLiveRangeForValue(RetAddrVal);
338 assert(RetAddrLR && "INTERNAL ERROR: No LR for return address of call!");
340 unsigned RegClassID = RetAddrLR->getRegClassID();
341 RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID, SparcIntRegClass::o7));
346 //---------------------------------------------------------------------------
347 // This method will suggest colors to incoming args to a method.
348 // According to the Sparc ABI, the first 6 incoming args are in
349 // %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float).
350 // If the arg is passed on stack due to the lack of regs, NOTHING will be
351 // done - it will be colored (or spilled) as a normal live range.
352 //---------------------------------------------------------------------------
353 void UltraSparcRegInfo::suggestRegs4MethodArgs(const Function *Meth,
354 LiveRangeInfo& LRI) const
356 // Check if this is a varArgs function. needed for choosing regs.
357 bool isVarArgs = isVarArgsFunction(Meth->getType());
359 // Count the arguments, *ignoring* whether they are int or FP args.
360 // Use this common arg numbering to pick the right int or fp register.
362 for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend();
363 I != E; ++I, ++argNo) {
364 LiveRange *LR = LRI.getLiveRangeForValue(I);
365 assert(LR && "No live range found for method arg");
367 unsigned regType = getRegTypeForLR(LR);
368 unsigned regClassIDOfArgReg = BadRegClass; // for chosen reg (unused)
370 int regNum = (regType == IntRegType)
371 ? regNumForIntArg(/*inCallee*/ true, isVarArgs, argNo, regClassIDOfArgReg)
372 : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs, argNo,
375 if (regNum != getInvalidRegNum())
376 LR->setSuggestedColor(regNum);
381 //---------------------------------------------------------------------------
382 // This method is called after graph coloring to move incoming args to
383 // the correct hardware registers if they did not receive the correct
384 // (suggested) color through graph coloring.
385 //---------------------------------------------------------------------------
386 void UltraSparcRegInfo::colorMethodArgs(const Function *Meth,
388 std::vector<MachineInstr*>& InstrnsBefore,
389 std::vector<MachineInstr*>& InstrnsAfter) const {
391 // check if this is a varArgs function. needed for choosing regs.
392 bool isVarArgs = isVarArgsFunction(Meth->getType());
396 // for each argument. count INT and FP arguments separately.
397 unsigned argNo=0, intArgNo=0, fpArgNo=0;
398 for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend();
399 I != E; ++I, ++argNo) {
401 LiveRange *LR = LRI.getLiveRangeForValue(I);
402 assert( LR && "No live range found for method arg");
404 unsigned regType = getRegTypeForLR(LR);
405 unsigned RegClassID = LR->getRegClassID();
407 // Find whether this argument is coming in a register (if not, on stack)
408 // Also find the correct register the argument must use (UniArgReg)
410 bool isArgInReg = false;
411 unsigned UniArgReg = getInvalidRegNum(); // reg that LR MUST be colored with
412 unsigned regClassIDOfArgReg = BadRegClass; // reg class of chosen reg
414 int regNum = (regType == IntRegType)
415 ? regNumForIntArg(/*inCallee*/ true, isVarArgs,
416 argNo, regClassIDOfArgReg)
417 : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs,
418 argNo, regClassIDOfArgReg);
420 if(regNum != getInvalidRegNum()) {
422 UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum);
425 if( ! LR->isMarkedForSpill() ) { // if this arg received a register
427 unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
429 // if LR received the correct color, nothing to do
431 if( UniLRReg == UniArgReg )
434 // We are here because the LR did not receive the suggested
435 // but LR received another register.
436 // Now we have to copy the %i reg (or stack pos of arg)
437 // to the register the LR was colored with.
439 // if the arg is coming in UniArgReg register, it MUST go into
440 // the UniLRReg register
443 if( regClassIDOfArgReg != RegClassID ) {
444 assert(0 && "This could should work but it is not tested yet");
446 // It is a variable argument call: the float reg must go in a %o reg.
447 // We have to move an int reg to a float reg via memory.
450 RegClassID == FloatRegClassID &&
451 regClassIDOfArgReg == IntRegClassID &&
452 "This should only be an Int register for an FP argument");
454 int TmpOff = MachineFunction::get(Meth).getInfo()->pushTempValue(
455 getSpilledRegSize(regType));
456 cpReg2MemMI(InstrnsBefore,
457 UniArgReg, getFramePointer(), TmpOff, IntRegType);
459 cpMem2RegMI(InstrnsBefore,
460 getFramePointer(), TmpOff, UniLRReg, regType);
463 cpReg2RegMI(InstrnsBefore, UniArgReg, UniLRReg, regType);
468 // Now the arg is coming on stack. Since the LR recieved a register,
469 // we just have to load the arg on stack into that register
471 const TargetFrameInfo& frameInfo = target.getFrameInfo();
473 frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
476 // float arguments on stack are right justified so adjust the offset!
477 // int arguments are also right justified but they are always loaded as
478 // a full double-word so the offset does not need to be adjusted.
479 if (regType == FPSingleRegType) {
480 unsigned argSize = target.getTargetData().getTypeSize(LR->getType());
481 unsigned slotSize = frameInfo.getSizeOfEachArgOnStack();
482 assert(argSize <= slotSize && "Insufficient slot size!");
483 offsetFromFP += slotSize - argSize;
486 cpMem2RegMI(InstrnsBefore,
487 getFramePointer(), offsetFromFP, UniLRReg, regType);
490 } // if LR received a color
494 // Now, the LR did not receive a color. But it has a stack offset for
496 // So, if the arg is coming in UniArgReg register, we can just move
497 // that on to the stack pos of LR
501 if( regClassIDOfArgReg != RegClassID ) {
503 "FP arguments to a varargs function should be explicitly "
504 "copied to/from int registers by instruction selection!");
506 // It must be a float arg for a variable argument call, which
507 // must come in a %o reg. Move the int reg to the stack.
509 assert(isVarArgs && regClassIDOfArgReg == IntRegClassID &&
510 "This should only be an Int register for an FP argument");
512 cpReg2MemMI(InstrnsBefore, UniArgReg,
513 getFramePointer(), LR->getSpillOffFromFP(), IntRegType);
516 cpReg2MemMI(InstrnsBefore, UniArgReg,
517 getFramePointer(), LR->getSpillOffFromFP(), regType);
523 // Now the arg is coming on stack. Since the LR did NOT
524 // recieved a register as well, it is allocated a stack position. We
525 // can simply change the stack position of the LR. We can do this,
526 // since this method is called before any other method that makes
527 // uses of the stack pos of the LR (e.g., updateMachineInstr)
529 const TargetFrameInfo& frameInfo = target.getFrameInfo();
531 frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
534 // FP arguments on stack are right justified so adjust offset!
535 // int arguments are also right justified but they are always loaded as
536 // a full double-word so the offset does not need to be adjusted.
537 if (regType == FPSingleRegType) {
538 unsigned argSize = target.getTargetData().getTypeSize(LR->getType());
539 unsigned slotSize = frameInfo.getSizeOfEachArgOnStack();
540 assert(argSize <= slotSize && "Insufficient slot size!");
541 offsetFromFP += slotSize - argSize;
544 LR->modifySpillOffFromFP( offsetFromFP );
549 } // for each incoming argument
555 //---------------------------------------------------------------------------
556 // This method is called before graph coloring to suggest colors to the
557 // outgoing call args and the return value of the call.
558 //---------------------------------------------------------------------------
559 void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
560 LiveRangeInfo& LRI) const {
561 assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
563 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
565 suggestReg4CallAddr(CallMI, LRI);
567 // First color the return value of the call instruction, if any.
568 // The return value will be in %o0 if the value is an integer type,
569 // or in %f0 if the value is a float type.
571 if (const Value *RetVal = argDesc->getReturnValue()) {
572 LiveRange *RetValLR = LRI.getLiveRangeForValue(RetVal);
573 assert(RetValLR && "No LR for return Value of call!");
575 unsigned RegClassID = RetValLR->getRegClassID();
577 // now suggest a register depending on the register class of ret arg
578 if( RegClassID == IntRegClassID )
579 RetValLR->setSuggestedColor(SparcIntRegClass::o0);
580 else if (RegClassID == FloatRegClassID )
581 RetValLR->setSuggestedColor(SparcFloatRegClass::f0 );
582 else assert( 0 && "Unknown reg class for return value of call\n");
585 // Now suggest colors for arguments (operands) of the call instruction.
586 // Colors are suggested only if the arg number is smaller than the
587 // the number of registers allocated for argument passing.
588 // Now, go thru call args - implicit operands of the call MI
590 unsigned NumOfCallArgs = argDesc->getNumArgs();
592 for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0;
593 i < NumOfCallArgs; ++i, ++argNo) {
595 const Value *CallArg = argDesc->getArgInfo(i).getArgVal();
597 // get the LR of call operand (parameter)
598 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
600 continue; // no live ranges for constants and labels
602 unsigned regType = getRegTypeForLR(LR);
603 unsigned regClassIDOfArgReg = BadRegClass; // chosen reg class (unused)
605 // Choose a register for this arg depending on whether it is
606 // an INT or FP value. Here we ignore whether or not it is a
607 // varargs calls, because FP arguments will be explicitly copied
608 // to an integer Value and handled under (argCopy != NULL) below.
609 int regNum = (regType == IntRegType)
610 ? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false,
611 argNo, regClassIDOfArgReg)
612 : regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false,
613 argNo, regClassIDOfArgReg);
615 // If a register could be allocated, use it.
616 // If not, do NOTHING as this will be colored as a normal value.
617 if(regNum != getInvalidRegNum())
618 LR->setSuggestedColor(regNum);
619 } // for all call arguments
623 //---------------------------------------------------------------------------
624 // this method is called for an LLVM return instruction to identify which
625 // values will be returned from this method and to suggest colors.
626 //---------------------------------------------------------------------------
627 void UltraSparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI,
628 LiveRangeInfo& LRI) const {
630 assert( (target.getInstrInfo()).isReturn( RetMI->getOpCode() ) );
632 suggestReg4RetAddr(RetMI, LRI);
634 // To find the return value (if any), we can get the LLVM return instr.
635 // from the return address register, which is the first operand
636 Value* tmpI = RetMI->getOperand(0).getVRegValue();
637 ReturnInst* retI=cast<ReturnInst>(cast<TmpInstruction>(tmpI)->getOperand(0));
638 if (const Value *RetVal = retI->getReturnValue())
639 if (LiveRange *const LR = LRI.getLiveRangeForValue(RetVal))
640 LR->setSuggestedColor(LR->getRegClassID() == IntRegClassID
641 ? (unsigned) SparcIntRegClass::i0
642 : (unsigned) SparcFloatRegClass::f0);
645 //---------------------------------------------------------------------------
646 // Check if a specified register type needs a scratch register to be
647 // copied to/from memory. If it does, the reg. type that must be used
648 // for scratch registers is returned in scratchRegType.
650 // Only the int CC register needs such a scratch register.
651 // The FP CC registers can (and must) be copied directly to/from memory.
652 //---------------------------------------------------------------------------
655 UltraSparcRegInfo::regTypeNeedsScratchReg(int RegType,
656 int& scratchRegType) const
658 if (RegType == IntCCRegType)
660 scratchRegType = IntRegType;
666 //---------------------------------------------------------------------------
667 // Copy from a register to register. Register number must be the unified
669 //---------------------------------------------------------------------------
672 UltraSparcRegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
676 assert( ((int)SrcReg != getInvalidRegNum()) &&
677 ((int)DestReg != getInvalidRegNum()) &&
680 MachineInstr * MI = NULL;
685 if (getRegType(DestReg) == IntRegType) {
686 // copy intCC reg to int reg
687 MI = (BuildMI(V9::RDCCR, 2)
688 .addMReg(getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID,
689 SparcIntCCRegClass::ccr))
690 .addMReg(DestReg,MOTy::Def));
692 // copy int reg to intCC reg
693 assert(getRegType(SrcReg) == IntRegType
694 && "Can only copy CC reg to/from integer reg");
695 MI = (BuildMI(V9::WRCCRr, 3)
697 .addMReg(SparcIntRegClass::g0)
698 .addMReg(getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID,
699 SparcIntCCRegClass::ccr), MOTy::Def));
704 assert(0 && "Cannot copy FPCC register to any other register");
708 MI = BuildMI(V9::ADDr, 3).addMReg(SrcReg).addMReg(getZeroRegNum())
709 .addMReg(DestReg, MOTy::Def);
712 case FPSingleRegType:
713 MI = BuildMI(V9::FMOVS, 2).addMReg(SrcReg).addMReg(DestReg, MOTy::Def);
716 case FPDoubleRegType:
717 MI = BuildMI(V9::FMOVD, 2).addMReg(SrcReg).addMReg(DestReg, MOTy::Def);
721 assert(0 && "Unknown RegType");
729 //---------------------------------------------------------------------------
730 // Copy from a register to memory (i.e., Store). Register number must
731 // be the unified register number
732 //---------------------------------------------------------------------------
736 UltraSparcRegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
739 int Offset, int RegType,
740 int scratchReg) const {
741 MachineInstr * MI = NULL;
744 // If the Offset will not fit in the signed-immediate field, find an
745 // unused register to hold the offset value. This takes advantage of
746 // the fact that all the opcodes used below have the same size immed. field.
747 // Use the register allocator, PRA, to find an unused reg. at this MI.
749 if (RegType != IntCCRegType) // does not use offset below
750 if (! target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset)) {
751 #ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY
752 RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
753 OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
755 // Default to using register g2 for holding large offsets
756 OffReg = getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
757 SparcIntRegClass::g4);
759 assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg.");
760 mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg));
765 if (target.getInstrInfo().constantFitsInImmedField(V9::STXi, Offset))
766 MI = BuildMI(V9::STXi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
768 MI = BuildMI(V9::STXr,3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg);
771 case FPSingleRegType:
772 if (target.getInstrInfo().constantFitsInImmedField(V9::STFi, Offset))
773 MI = BuildMI(V9::STFi, 3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
775 MI = BuildMI(V9::STFr, 3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg);
778 case FPDoubleRegType:
779 if (target.getInstrInfo().constantFitsInImmedField(V9::STDFi, Offset))
780 MI = BuildMI(V9::STDFi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
782 MI = BuildMI(V9::STDFr,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(OffReg);
786 assert(scratchReg >= 0 && "Need scratch reg to store %ccr to memory");
787 assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
788 MI = (BuildMI(V9::RDCCR, 2)
789 .addMReg(getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID,
790 SparcIntCCRegClass::ccr))
791 .addMReg(scratchReg, MOTy::Def));
794 cpReg2MemMI(mvec, scratchReg, PtrReg, Offset, IntRegType);
797 case FloatCCRegType: {
798 unsigned fsrReg = getUnifiedRegNum(UltraSparcRegInfo::SpecialRegClassID,
799 SparcSpecialRegClass::fsr);
800 if (target.getInstrInfo().constantFitsInImmedField(V9::STXFSRi, Offset))
801 MI=BuildMI(V9::STXFSRi,3).addMReg(fsrReg).addMReg(PtrReg).addSImm(Offset);
803 MI=BuildMI(V9::STXFSRr,3).addMReg(fsrReg).addMReg(PtrReg).addMReg(OffReg);
807 assert(0 && "Unknown RegType in cpReg2MemMI");
813 //---------------------------------------------------------------------------
814 // Copy from memory to a reg (i.e., Load) Register number must be the unified
816 //---------------------------------------------------------------------------
820 UltraSparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
825 int scratchReg) const {
826 MachineInstr * MI = NULL;
829 // If the Offset will not fit in the signed-immediate field, find an
830 // unused register to hold the offset value. This takes advantage of
831 // the fact that all the opcodes used below have the same size immed. field.
832 // Use the register allocator, PRA, to find an unused reg. at this MI.
834 if (RegType != IntCCRegType) // does not use offset below
835 if (! target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset)) {
836 #ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY
837 RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
838 OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
840 // Default to using register g2 for holding large offsets
841 OffReg = getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
842 SparcIntRegClass::g4);
844 assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg.");
845 mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg));
850 if (target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset))
851 MI = BuildMI(V9::LDXi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg,
854 MI = BuildMI(V9::LDXr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg,
858 case FPSingleRegType:
859 if (target.getInstrInfo().constantFitsInImmedField(V9::LDFi, Offset))
860 MI = BuildMI(V9::LDFi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg,
863 MI = BuildMI(V9::LDFr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg,
867 case FPDoubleRegType:
868 if (target.getInstrInfo().constantFitsInImmedField(V9::LDDFi, Offset))
869 MI= BuildMI(V9::LDDFi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg,
872 MI= BuildMI(V9::LDDFr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg,
877 assert(scratchReg >= 0 && "Need scratch reg to load %ccr from memory");
878 assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
879 cpMem2RegMI(mvec, PtrReg, Offset, scratchReg, IntRegType);
880 MI = (BuildMI(V9::WRCCRr, 3)
882 .addMReg(SparcIntRegClass::g0)
883 .addMReg(getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID,
884 SparcIntCCRegClass::ccr), MOTy::Def));
887 case FloatCCRegType: {
888 unsigned fsrRegNum = getUnifiedRegNum(UltraSparcRegInfo::SpecialRegClassID,
889 SparcSpecialRegClass::fsr);
890 if (target.getInstrInfo().constantFitsInImmedField(V9::LDXFSRi, Offset))
891 MI = BuildMI(V9::LDXFSRi, 3).addMReg(PtrReg).addSImm(Offset)
892 .addMReg(fsrRegNum, MOTy::UseAndDef);
894 MI = BuildMI(V9::LDXFSRr, 3).addMReg(PtrReg).addMReg(OffReg)
895 .addMReg(fsrRegNum, MOTy::UseAndDef);
899 assert(0 && "Unknown RegType in cpMem2RegMI");
905 //---------------------------------------------------------------------------
906 // Generate a copy instruction to copy a value to another. Temporarily
907 // used by PhiElimination code.
908 //---------------------------------------------------------------------------
912 UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest,
913 std::vector<MachineInstr*>& mvec) const {
914 int RegType = getRegTypeForDataType(Src->getType());
915 MachineInstr * MI = NULL;
919 MI = BuildMI(V9::ADDr, 3).addReg(Src).addMReg(getZeroRegNum())
922 case FPSingleRegType:
923 MI = BuildMI(V9::FMOVS, 2).addReg(Src).addRegDef(Dest);
925 case FPDoubleRegType:
926 MI = BuildMI(V9::FMOVD, 2).addReg(Src).addRegDef(Dest);
929 assert(0 && "Unknow RegType in CpValu2Value");
937 //---------------------------------------------------------------------------
938 // Print the register assigned to a LR
939 //---------------------------------------------------------------------------
941 void UltraSparcRegInfo::printReg(const LiveRange *LR) const {
942 unsigned RegClassID = LR->getRegClassID();
943 std::cerr << " *Node " << (LR->getUserIGNode())->getIndex();
945 if (!LR->hasColor()) {
946 std::cerr << " - could not find a color\n";
950 // if a color is found
952 std::cerr << " colored with color "<< LR->getColor();
954 unsigned uRegName = getUnifiedRegNum(RegClassID, LR->getColor());
957 std::cerr<< getUnifiedRegName(uRegName);
958 if (RegClassID == FloatRegClassID && LR->getType() == Type::DoubleTy)
959 std::cerr << "+" << getUnifiedRegName(uRegName+1);