1 //===- SparcV9RegisterInfo.cpp - SparcV9 Register Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SparcV9 implementation of the MRegisterInfo class.
11 // It also contains stuff needed to instantiate that class, which would
12 // ordinarily be provided by TableGen.
14 // This is NOT used by the SparcV9 backend to do register allocation, yet.
16 //===----------------------------------------------------------------------===//
18 // The first section of this file (immediately following) is what
19 // you would find in SparcV9GenRegisterInfo.inc, if we were using
20 // TableGen to generate the register file description automatically.
21 // It consists of register classes and register class instances
22 // for the SparcV9 target.
24 // FIXME: the alignments listed here are wild guesses.
26 //===----------------------------------------------------------------------===//
28 #include "SparcV9RegisterInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
35 // IR Register Class...
36 const unsigned IR[] = {
37 SparcV9::o0, SparcV9::o1, SparcV9::o2, SparcV9::o3, SparcV9::o4,
38 SparcV9::o5, SparcV9::o7, SparcV9::l0, SparcV9::l1, SparcV9::l2,
39 SparcV9::l3, SparcV9::l4, SparcV9::l5, SparcV9::l6, SparcV9::l7,
40 SparcV9::i0, SparcV9::i1, SparcV9::i2, SparcV9::i3, SparcV9::i4,
41 SparcV9::i5, SparcV9::i6, SparcV9::i7, SparcV9::g0, SparcV9::g1,
42 SparcV9::g2, SparcV9::g3, SparcV9::g4, SparcV9::g5, SparcV9::g6,
43 SparcV9::g7, SparcV9::o6
45 struct IRClass : public TargetRegisterClass {
46 IRClass() : TargetRegisterClass(8, 8, IR, IR + 32) {}
50 // FR Register Class...
51 const unsigned FR[] = {
52 SparcV9::f0, SparcV9::f1, SparcV9::f2, SparcV9::f3, SparcV9::f4,
53 SparcV9::f5, SparcV9::f6, SparcV9::f7, SparcV9::f8, SparcV9::f9,
54 SparcV9::f10, SparcV9::f11, SparcV9::f12, SparcV9::f13,
55 SparcV9::f14, SparcV9::f15, SparcV9::f16, SparcV9::f17,
56 SparcV9::f18, SparcV9::f19, SparcV9::f20, SparcV9::f21,
57 SparcV9::f22, SparcV9::f23, SparcV9::f24, SparcV9::f25,
58 SparcV9::f26, SparcV9::f27, SparcV9::f28, SparcV9::f29,
59 SparcV9::f30, SparcV9::f31, SparcV9::f32, SparcV9::f33,
60 SparcV9::f34, SparcV9::f35, SparcV9::f36, SparcV9::f37,
61 SparcV9::f38, SparcV9::f39, SparcV9::f40, SparcV9::f41,
62 SparcV9::f42, SparcV9::f43, SparcV9::f44, SparcV9::f45,
63 SparcV9::f46, SparcV9::f47, SparcV9::f48, SparcV9::f49,
64 SparcV9::f50, SparcV9::f51, SparcV9::f52, SparcV9::f53,
65 SparcV9::f54, SparcV9::f55, SparcV9::f56, SparcV9::f57,
66 SparcV9::f58, SparcV9::f59, SparcV9::f60, SparcV9::f61,
67 SparcV9::f62, SparcV9::f63
69 // FIXME: The size is correct for the first 32 registers. The
70 // latter 32 do not all really exist; you can only access every other
71 // one (32, 34, ...), and they must contain double-fp or quad-fp
72 // values... see below about the aliasing problems.
73 struct FRClass : public TargetRegisterClass {
74 FRClass() : TargetRegisterClass(4, 8, FR, FR + 64) {}
78 // ICCR Register Class...
79 const unsigned ICCR[] = {
80 SparcV9::xcc, SparcV9::icc, SparcV9::ccr
82 struct ICCRClass : public TargetRegisterClass {
83 ICCRClass() : TargetRegisterClass(1, 8, ICCR, ICCR + 3) {}
87 // FCCR Register Class...
88 const unsigned FCCR[] = {
89 SparcV9::fcc0, SparcV9::fcc1, SparcV9::fcc2, SparcV9::fcc3
91 struct FCCRClass : public TargetRegisterClass {
92 FCCRClass() : TargetRegisterClass(1, 8, FCCR, FCCR + 4) {}
96 // SR Register Class...
97 const unsigned SR[] = {
100 struct SRClass : public TargetRegisterClass {
101 SRClass() : TargetRegisterClass(8, 8, SR, SR + 1) {}
105 // Register Classes...
106 const TargetRegisterClass* const RegisterClasses[] = {
115 // Register Alias Sets...
116 // FIXME: Note that the SparcV9 backend does not currently abstract
117 // very well over the way that double-fp and quad-fp values may alias
118 // single-fp values in registers. Therefore those aliases are NOT
120 const unsigned Empty_AliasSet[] = { 0 };
121 const unsigned fcc3_AliasSet[] = { SparcV9::fsr, 0 };
122 const unsigned fcc2_AliasSet[] = { SparcV9::fsr, 0 };
123 const unsigned fcc1_AliasSet[] = { SparcV9::fsr, 0 };
124 const unsigned fcc0_AliasSet[] = { SparcV9::fsr, 0 };
125 const unsigned fsr_AliasSet[] = { SparcV9::fcc3, SparcV9::fcc2,
126 SparcV9::fcc1, SparcV9::fcc0, 0 };
127 const unsigned xcc_AliasSet[] = { SparcV9::ccr, 0 };
128 const unsigned icc_AliasSet[] = { SparcV9::ccr, 0 };
129 const unsigned ccr_AliasSet[] = { SparcV9::xcc, SparcV9::icc, 0 };
131 const MRegisterDesc RegisterDescriptors[] = { // Descriptors
132 { "o0", Empty_AliasSet, 0, 0 },
133 { "o1", Empty_AliasSet, 0, 0 },
134 { "o2", Empty_AliasSet, 0, 0 },
135 { "o3", Empty_AliasSet, 0, 0 },
136 { "o4", Empty_AliasSet, 0, 0 },
137 { "o5", Empty_AliasSet, 0, 0 },
138 { "o7", Empty_AliasSet, 0, 0 },
139 { "l0", Empty_AliasSet, 0, 0 },
140 { "l1", Empty_AliasSet, 0, 0 },
141 { "l2", Empty_AliasSet, 0, 0 },
142 { "l3", Empty_AliasSet, 0, 0 },
143 { "l4", Empty_AliasSet, 0, 0 },
144 { "l5", Empty_AliasSet, 0, 0 },
145 { "l6", Empty_AliasSet, 0, 0 },
146 { "l7", Empty_AliasSet, 0, 0 },
147 { "i0", Empty_AliasSet, 0, 0 },
148 { "i1", Empty_AliasSet, 0, 0 },
149 { "i2", Empty_AliasSet, 0, 0 },
150 { "i3", Empty_AliasSet, 0, 0 },
151 { "i4", Empty_AliasSet, 0, 0 },
152 { "i5", Empty_AliasSet, 0, 0 },
153 { "i6", Empty_AliasSet, 0, 0 },
154 { "i7", Empty_AliasSet, 0, 0 },
155 { "g0", Empty_AliasSet, 0, 0 },
156 { "g1", Empty_AliasSet, 0, 0 },
157 { "g2", Empty_AliasSet, 0, 0 },
158 { "g3", Empty_AliasSet, 0, 0 },
159 { "g4", Empty_AliasSet, 0, 0 },
160 { "g5", Empty_AliasSet, 0, 0 },
161 { "g6", Empty_AliasSet, 0, 0 },
162 { "g7", Empty_AliasSet, 0, 0 },
163 { "o6", Empty_AliasSet, 0, 0 },
164 { "f0", Empty_AliasSet, 0, 0 },
165 { "f1", Empty_AliasSet, 0, 0 },
166 { "f2", Empty_AliasSet, 0, 0 },
167 { "f3", Empty_AliasSet, 0, 0 },
168 { "f4", Empty_AliasSet, 0, 0 },
169 { "f5", Empty_AliasSet, 0, 0 },
170 { "f6", Empty_AliasSet, 0, 0 },
171 { "f7", Empty_AliasSet, 0, 0 },
172 { "f8", Empty_AliasSet, 0, 0 },
173 { "f9", Empty_AliasSet, 0, 0 },
174 { "f10", Empty_AliasSet, 0, 0 },
175 { "f11", Empty_AliasSet, 0, 0 },
176 { "f12", Empty_AliasSet, 0, 0 },
177 { "f13", Empty_AliasSet, 0, 0 },
178 { "f14", Empty_AliasSet, 0, 0 },
179 { "f15", Empty_AliasSet, 0, 0 },
180 { "f16", Empty_AliasSet, 0, 0 },
181 { "f17", Empty_AliasSet, 0, 0 },
182 { "f18", Empty_AliasSet, 0, 0 },
183 { "f19", Empty_AliasSet, 0, 0 },
184 { "f20", Empty_AliasSet, 0, 0 },
185 { "f21", Empty_AliasSet, 0, 0 },
186 { "f22", Empty_AliasSet, 0, 0 },
187 { "f23", Empty_AliasSet, 0, 0 },
188 { "f24", Empty_AliasSet, 0, 0 },
189 { "f25", Empty_AliasSet, 0, 0 },
190 { "f26", Empty_AliasSet, 0, 0 },
191 { "f27", Empty_AliasSet, 0, 0 },
192 { "f28", Empty_AliasSet, 0, 0 },
193 { "f29", Empty_AliasSet, 0, 0 },
194 { "f30", Empty_AliasSet, 0, 0 },
195 { "f31", Empty_AliasSet, 0, 0 },
196 { "f32", Empty_AliasSet, 0, 0 },
197 { "f33", Empty_AliasSet, 0, 0 },
198 { "f34", Empty_AliasSet, 0, 0 },
199 { "f35", Empty_AliasSet, 0, 0 },
200 { "f36", Empty_AliasSet, 0, 0 },
201 { "f37", Empty_AliasSet, 0, 0 },
202 { "f38", Empty_AliasSet, 0, 0 },
203 { "f39", Empty_AliasSet, 0, 0 },
204 { "f40", Empty_AliasSet, 0, 0 },
205 { "f41", Empty_AliasSet, 0, 0 },
206 { "f42", Empty_AliasSet, 0, 0 },
207 { "f43", Empty_AliasSet, 0, 0 },
208 { "f44", Empty_AliasSet, 0, 0 },
209 { "f45", Empty_AliasSet, 0, 0 },
210 { "f46", Empty_AliasSet, 0, 0 },
211 { "f47", Empty_AliasSet, 0, 0 },
212 { "f48", Empty_AliasSet, 0, 0 },
213 { "f49", Empty_AliasSet, 0, 0 },
214 { "f50", Empty_AliasSet, 0, 0 },
215 { "f51", Empty_AliasSet, 0, 0 },
216 { "f52", Empty_AliasSet, 0, 0 },
217 { "f53", Empty_AliasSet, 0, 0 },
218 { "f54", Empty_AliasSet, 0, 0 },
219 { "f55", Empty_AliasSet, 0, 0 },
220 { "f56", Empty_AliasSet, 0, 0 },
221 { "f57", Empty_AliasSet, 0, 0 },
222 { "f58", Empty_AliasSet, 0, 0 },
223 { "f59", Empty_AliasSet, 0, 0 },
224 { "f60", Empty_AliasSet, 0, 0 },
225 { "f61", Empty_AliasSet, 0, 0 },
226 { "f62", Empty_AliasSet, 0, 0 },
227 { "f63", Empty_AliasSet, 0, 0 },
228 { "xcc", xcc_AliasSet, 0, 0 },
229 { "icc", icc_AliasSet, 0, 0 },
230 { "ccr", ccr_AliasSet, 0, 0 },
231 { "fcc0", fcc0_AliasSet, 0, 0 },
232 { "fcc1", fcc1_AliasSet, 0, 0 },
233 { "fcc2", fcc2_AliasSet, 0, 0 },
234 { "fcc3", fcc3_AliasSet, 0, 0 },
235 { "fsr", fsr_AliasSet, 0, 0 },
238 } // end anonymous namespace
240 namespace SparcV9 { // Register classes
241 TargetRegisterClass *IRRegisterClass = &IRInstance;
242 TargetRegisterClass *FRRegisterClass = &FRInstance;
243 TargetRegisterClass *ICCRRegisterClass = &ICCRInstance;
244 TargetRegisterClass *FCCRRegisterClass = &FCCRInstance;
245 TargetRegisterClass *SRRegisterClass = &SRInstance;
246 } // end namespace SparcV9
248 const unsigned *SparcV9RegisterInfo::getCalleeSaveRegs() const {
249 // FIXME: This should be verified against the SparcV9 ABI at some point.
250 // These are the registers which the SparcV9 backend considers
252 static const unsigned CalleeSaveRegs[] = {
253 SparcV9::l0, SparcV9::l1, SparcV9::l2, SparcV9::l3, SparcV9::l4,
254 SparcV9::l5, SparcV9::l6, SparcV9::l7, SparcV9::i0, SparcV9::i1,
255 SparcV9::i2, SparcV9::i3, SparcV9::i4, SparcV9::i5, SparcV9::i6,
256 SparcV9::i7, SparcV9::g0, SparcV9::g1, SparcV9::g2, SparcV9::g3,
257 SparcV9::g4, SparcV9::g5, SparcV9::g6, SparcV9::g7, SparcV9::o6,
260 return CalleeSaveRegs;
263 } // end namespace llvm
265 //===----------------------------------------------------------------------===//
267 // The second section of this file (immediately following) contains the
268 // SparcV9 implementation of the MRegisterInfo class. It currently consists
269 // entirely of stub functions, because the SparcV9 target does not use the
270 // same register allocator that the X86 target uses.
272 //===----------------------------------------------------------------------===//
274 SparcV9RegisterInfo::SparcV9RegisterInfo ()
275 : MRegisterInfo (RegisterDescriptors, 104, RegisterClasses,
276 RegisterClasses + 5) {
279 void SparcV9RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
280 MachineBasicBlock::iterator MI,
281 unsigned SrcReg, int FrameIndex) const{
285 void SparcV9RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
286 MachineBasicBlock::iterator MI,
287 unsigned DestReg, int FrameIndex) const {
291 void SparcV9RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
292 MachineBasicBlock::iterator MI,
293 unsigned DestReg, unsigned SrcReg,
294 const TargetRegisterClass *RC) const {
298 void SparcV9RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI)
303 void SparcV9RegisterInfo::emitPrologue(MachineFunction &MF) const {
307 void SparcV9RegisterInfo::emitEpilogue(MachineFunction &MF,
308 MachineBasicBlock &MBB) const {