1 //===- SparcV9RegisterInfo.h - SparcV9 Register Information Impl -*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SparcV9 implementation of the MRegisterInfo class.
11 // It also contains stuff needed to instantiate that class, which would
12 // ordinarily be provided by TableGen.
14 //===----------------------------------------------------------------------===//
16 #ifndef SPARCV9REGISTERINFO_H
17 #define SPARCV9REGISTERINFO_H
19 #include "llvm/Target/MRegisterInfo.h"
23 struct SparcV9RegisterInfo : public MRegisterInfo {
24 SparcV9RegisterInfo ();
25 const unsigned *getCalleeSaveRegs() const;
27 // The rest of these are stubs... for now.
28 void storeRegToStackSlot(MachineBasicBlock &MBB,
29 MachineBasicBlock::iterator MI,
30 unsigned SrcReg, int FrameIndex) const;
31 void loadRegFromStackSlot(MachineBasicBlock &MBB,
32 MachineBasicBlock::iterator MI,
33 unsigned DestReg, int FrameIndex) const;
34 void copyRegToReg(MachineBasicBlock &MBB,
35 MachineBasicBlock::iterator MI,
36 unsigned DestReg, unsigned SrcReg,
37 const TargetRegisterClass *RC) const;
38 void eliminateFrameIndex (MachineBasicBlock::iterator MI) const;
39 void emitPrologue (MachineFunction &MF) const;
40 void emitEpilogue (MachineFunction &MF, MachineBasicBlock &MBB) const;
43 } // End llvm namespace
45 //===----------------------------------------------------------------------===//
47 // The second section of this file (immediately following) contains
48 // a *handwritten* SparcV9 unified register number enumeration, which
49 // provides a flat namespace containing all the SparcV9 unified
52 // It would ordinarily be contained in the file SparcV9GenRegisterNames.inc
53 // if we were using TableGen to generate the register file description
56 //===----------------------------------------------------------------------===//
61 // FIXME - Register 0 is not a "non-register" like it is on other targets!!
63 // SparcV9IntRegClass(IntRegClassID)
64 // - unified register numbers 0 ... 31 (32 regs)
65 /* 0 */ o0, o1, o2, o3, o4,
66 /* 5 */ o5, o7, l0, l1, l2,
67 /* 10 */ l3, l4, l5, l6, l7,
68 /* 15 */ i0, i1, i2, i3, i4,
69 /* 20 */ i5, i6, i7, g0, g1, // i6 is frame ptr, i7 is ret addr, g0 is zero
70 /* 25 */ g2, g3, g4, g5, g6,
71 /* 30 */ g7, o6, // o6 is stack ptr
73 // SparcV9FloatRegClass(FloatRegClassID)
74 // - regs 32 .. 63 are FPSingleRegType, 64 .. 95 are FPDoubleRegType
75 // - unified register numbers 32 ... 95 (64 regs)
77 /* 35 */ f3, f4, f5, f6, f7,
78 /* 40 */ f8, f9, f10, f11, f12,
79 /* 45 */ f13, f14, f15, f16, f17,
80 /* 50 */ f18, f19, f20, f21, f22,
81 /* 55 */ f23, f24, f25, f26, f27,
82 /* 60 */ f28, f29, f30, f31, f32,
83 /* 65 */ f33, f34, f35, f36, f37,
84 /* 70 */ f38, f39, f40, f41, f42,
85 /* 75 */ f43, f44, f45, f46, f47,
86 /* 80 */ f48, f49, f50, f51, f52,
87 /* 85 */ f53, f54, f55, f56, f57,
88 /* 90 */ f58, f59, f60, f61, f62,
91 // SparcV9IntCCRegClass(IntCCRegClassID)
92 // - unified register numbers 96 ... 98 (3 regs)
93 /* 96 */ xcc, icc, ccr,
95 // SparcV9FloatCCRegClass(FloatCCRegClassID)
96 // - unified register numbers 99 ... 102 (4 regs)
97 /* 99 */ fcc0, fcc1, fcc2, fcc3,
99 // SparcV9SpecialRegClass(SpecialRegClassID)
100 // - unified register number 103 (1 reg)
103 } // end namespace SparcV9
104 } // end namespace llvm
106 #endif // SPARCV9REGISTERINFO_H