1 //===-- SparcV9SchedInfo.cpp ----------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Describe the scheduling characteristics of the UltraSparc IIi.
12 //===----------------------------------------------------------------------===//
14 #include "SparcV9Internals.h"
18 /*---------------------------------------------------------------------------
19 Scheduling guidelines for SPARC IIi:
21 I-Cache alignment rules (pg 326)
22 -- Align a branch target instruction so that it's entire group is within
23 the same cache line (may be 1-4 instructions).
24 ** Don't let a branch that is predicted taken be the last instruction
25 on an I-cache line: delay slot will need an entire line to be fetched
26 -- Make a FP instruction or a branch be the 4th instruction in a group.
27 For branches, there are tradeoffs in reordering to make this happen
29 ** Don't put a branch in a group that crosses a 32-byte boundary!
30 An artificial branch is inserted after every 32 bytes, and having
31 another branch will force the group to be broken into 2 groups.
34 -- Don't let a loop span two memory pages, if possible
36 Branch prediction performance:
37 -- Don't make the branch in a delay slot the target of a branch
38 -- Try not to have 2 predicted branches within a group of 4 instructions
39 (because each such group has a single branch target field).
40 -- Try to align branches in slots 0, 2, 4 or 6 of a cache line (to avoid
41 the wrong prediction bits being used in some cases).
43 D-Cache timing constraints:
44 -- Signed int loads of less than 64 bits have 3 cycle latency, not 2
45 -- All other loads that hit in D-Cache have 2 cycle latency
46 -- All loads are returned IN ORDER, so a D-Cache miss will delay a later hit
47 -- Mis-aligned loads or stores cause a trap. In particular, replace
48 mis-aligned FP double precision l/s with 2 single-precision l/s.
49 -- Simulations of integer codes show increase in avg. group size of
50 33% when code (including esp. non-faulting loads) is moved across
51 one branch, and 50% across 2 branches.
53 E-Cache timing constraints:
54 -- Scheduling for E-cache (D-Cache misses) is effective (due to load buffering)
56 Store buffer timing constraints:
57 -- Stores can be executed in same cycle as instruction producing the value
58 -- Stores are buffered and have lower priority for E-cache until
59 highwater mark is reached in the store buffer (5 stores)
62 -- Shifts can only use IEU0.
63 -- CC setting instructions can only use IEU1.
64 -- Several other instructions must only use IEU1:
65 EDGE(?), ARRAY(?), CALL, JMPL, BPr, PST, and FCMP.
66 -- Two instructions cannot store to the same register file in a single cycle
67 (single write port per file).
69 Issue and grouping constraints:
70 -- FP and branch instructions must use slot 4.
71 -- Shift instructions cannot be grouped with other IEU0-specific instructions.
72 -- CC setting instructions cannot be grouped with other IEU1-specific instrs.
73 -- Several instructions must be issued in a single-instruction group:
74 MOVcc or MOVr, MULs/x and DIVs/x, SAVE/RESTORE, many others
75 -- A CALL or JMPL breaks a group, ie, is not combined with subsequent instrs.
79 Branch delay slot scheduling rules:
80 -- A CTI couple (two back-to-back CTI instructions in the dynamic stream)
81 has a 9-instruction penalty: the entire pipeline is flushed when the
82 second instruction reaches stage 9 (W-Writeback).
83 -- Avoid putting multicycle instructions, and instructions that may cause
84 load misses, in the delay slot of an annulling branch.
85 -- Avoid putting WR, SAVE..., RESTORE and RETURN instructions in the
86 delay slot of an annulling branch.
88 *--------------------------------------------------------------------------- */
90 //---------------------------------------------------------------------------
91 // List of CPUResources for UltraSPARC IIi.
92 //---------------------------------------------------------------------------
94 static const CPUResource AllIssueSlots( "All Instr Slots", 4);
95 static const CPUResource IntIssueSlots( "Int Instr Slots", 3);
96 static const CPUResource First3IssueSlots("Instr Slots 0-3", 3);
97 static const CPUResource LSIssueSlots( "Load-Store Instr Slot", 1);
98 static const CPUResource CTIIssueSlots( "Ctrl Transfer Instr Slot", 1);
99 static const CPUResource FPAIssueSlots( "FP Instr Slot 1", 1);
100 static const CPUResource FPMIssueSlots( "FP Instr Slot 2", 1);
102 // IEUN instructions can use either Alu and should use IAluN.
103 // IEU0 instructions must use Alu 1 and should use both IAluN and IAlu0.
104 // IEU1 instructions must use Alu 2 and should use both IAluN and IAlu1.
105 static const CPUResource IAluN("Int ALU 1or2", 2);
106 static const CPUResource IAlu0("Int ALU 1", 1);
107 static const CPUResource IAlu1("Int ALU 2", 1);
109 static const CPUResource LSAluC1("Load/Store Unit Addr Cycle", 1);
110 static const CPUResource LSAluC2("Load/Store Unit Issue Cycle", 1);
111 static const CPUResource LdReturn("Load Return Unit", 1);
113 static const CPUResource FPMAluC1("FP Mul/Div Alu Cycle 1", 1);
114 static const CPUResource FPMAluC2("FP Mul/Div Alu Cycle 2", 1);
115 static const CPUResource FPMAluC3("FP Mul/Div Alu Cycle 3", 1);
117 static const CPUResource FPAAluC1("FP Other Alu Cycle 1", 1);
118 static const CPUResource FPAAluC2("FP Other Alu Cycle 2", 1);
119 static const CPUResource FPAAluC3("FP Other Alu Cycle 3", 1);
121 static const CPUResource IRegReadPorts("Int Reg ReadPorts", INT_MAX); // CHECK
122 static const CPUResource IRegWritePorts("Int Reg WritePorts", 2); // CHECK
123 static const CPUResource FPRegReadPorts("FP Reg Read Ports", INT_MAX);// CHECK
124 static const CPUResource FPRegWritePorts("FP Reg Write Ports", 1); // CHECK
126 static const CPUResource CTIDelayCycle( "CTI delay cycle", 1);
127 static const CPUResource FCMPDelayCycle("FCMP delay cycle", 1);
131 //---------------------------------------------------------------------------
132 // const InstrClassRUsage SparcV9RUsageDesc[]
135 // Resource usage information for instruction in each scheduling class.
136 // The InstrRUsage Objects for individual classes are specified first.
137 // Note that fetch and decode are decoupled from the execution pipelines
138 // via an instr buffer, so they are not included in the cycles below.
139 //---------------------------------------------------------------------------
141 static const InstrClassRUsage NoneClassRUsage = {
146 /* isSingleIssue */ false,
147 /* breaksGroup */ false,
151 /* feasibleSlots[] */ { 0, 1, 2, 3 },
165 static const InstrClassRUsage IEUNClassRUsage = {
170 /* isSingleIssue */ false,
171 /* breaksGroup */ false,
175 /* feasibleSlots[] */ { 0, 1, 2 },
179 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
180 { IntIssueSlots.rid, 0, 1 },
181 /*Cycle E */ { IAluN.rid, 1, 1 },
186 /*Cycle W */ { IRegWritePorts.rid, 6, 1 }
190 static const InstrClassRUsage IEU0ClassRUsage = {
195 /* isSingleIssue */ false,
196 /* breaksGroup */ false,
200 /* feasibleSlots[] */ { 0, 1, 2 },
204 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
205 { IntIssueSlots.rid, 0, 1 },
206 /*Cycle E */ { IAluN.rid, 1, 1 },
212 /*Cycle W */ { IRegWritePorts.rid, 6, 1 }
216 static const InstrClassRUsage IEU1ClassRUsage = {
221 /* isSingleIssue */ false,
222 /* breaksGroup */ false,
226 /* feasibleSlots[] */ { 0, 1, 2 },
230 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
231 { IntIssueSlots.rid, 0, 1 },
232 /*Cycle E */ { IAluN.rid, 1, 1 },
238 /*Cycle W */ { IRegWritePorts.rid, 6, 1 }
242 static const InstrClassRUsage FPMClassRUsage = {
247 /* isSingleIssue */ false,
248 /* breaksGroup */ false,
252 /* feasibleSlots[] */ { 0, 1, 2, 3 },
256 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
257 { FPMIssueSlots.rid, 0, 1 },
258 /*Cycle E */ { FPRegReadPorts.rid, 1, 1 },
259 /*Cycle C */ { FPMAluC1.rid, 2, 1 },
260 /*Cycle N1*/ { FPMAluC2.rid, 3, 1 },
261 /*Cycle N1*/ { FPMAluC3.rid, 4, 1 },
263 /*Cycle W */ { FPRegWritePorts.rid, 6, 1 }
267 static const InstrClassRUsage FPAClassRUsage = {
272 /* isSingleIssue */ false,
273 /* breaksGroup */ false,
277 /* feasibleSlots[] */ { 0, 1, 2, 3 },
281 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
282 { FPAIssueSlots.rid, 0, 1 },
283 /*Cycle E */ { FPRegReadPorts.rid, 1, 1 },
284 /*Cycle C */ { FPAAluC1.rid, 2, 1 },
285 /*Cycle N1*/ { FPAAluC2.rid, 3, 1 },
286 /*Cycle N1*/ { FPAAluC3.rid, 4, 1 },
288 /*Cycle W */ { FPRegWritePorts.rid, 6, 1 }
292 static const InstrClassRUsage LDClassRUsage = {
297 /* isSingleIssue */ false,
298 /* breaksGroup */ false,
302 /* feasibleSlots[] */ { 0, 1, 2, },
306 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
307 { First3IssueSlots.rid, 0, 1 },
308 { LSIssueSlots.rid, 0, 1 },
309 /*Cycle E */ { LSAluC1.rid, 1, 1 },
310 /*Cycle C */ { LSAluC2.rid, 2, 1 },
311 { LdReturn.rid, 2, 1 },
315 /*Cycle W */ { IRegWritePorts.rid, 6, 1 }
319 static const InstrClassRUsage STClassRUsage = {
324 /* isSingleIssue */ false,
325 /* breaksGroup */ false,
329 /* feasibleSlots[] */ { 0, 1, 2 },
333 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
334 { First3IssueSlots.rid, 0, 1 },
335 { LSIssueSlots.rid, 0, 1 },
336 /*Cycle E */ { LSAluC1.rid, 1, 1 },
337 /*Cycle C */ { LSAluC2.rid, 2, 1 }
345 static const InstrClassRUsage CTIClassRUsage = {
350 /* isSingleIssue */ false,
351 /* breaksGroup */ false,
355 /* feasibleSlots[] */ { 0, 1, 2, 3 },
359 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
360 { CTIIssueSlots.rid, 0, 1 },
361 /*Cycle E */ { IAlu0.rid, 1, 1 },
362 /*Cycles E-C */ { CTIDelayCycle.rid, 1, 2 }
371 static const InstrClassRUsage SingleClassRUsage = {
376 /* isSingleIssue */ true,
377 /* breaksGroup */ false,
381 /* feasibleSlots[] */ { 0 },
385 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
386 { AllIssueSlots.rid, 0, 1 },
387 { AllIssueSlots.rid, 0, 1 },
388 { AllIssueSlots.rid, 0, 1 },
389 /*Cycle E */ { IAlu0.rid, 1, 1 }
399 static const InstrClassRUsage SparcV9RUsageDesc[] = {
414 //---------------------------------------------------------------------------
415 // const InstrIssueDelta SparcV9InstrIssueDeltas[]
418 // Changes to issue restrictions information in InstrClassRUsage for
419 // instructions that differ from other instructions in their class.
420 //---------------------------------------------------------------------------
422 static const InstrIssueDelta SparcV9InstrIssueDeltas[] = {
424 // opCode, isSingleIssue, breaksGroup, numBubbles
426 // Special cases for single-issue only
427 // Other single issue cases are below.
428 //{ V9::LDDA, true, true, 0 },
429 //{ V9::STDA, true, true, 0 },
430 //{ V9::LDDF, true, true, 0 },
431 //{ V9::LDDFA, true, true, 0 },
432 { V9::ADDCr, true, true, 0 },
433 { V9::ADDCi, true, true, 0 },
434 { V9::ADDCccr, true, true, 0 },
435 { V9::ADDCcci, true, true, 0 },
436 { V9::SUBCr, true, true, 0 },
437 { V9::SUBCi, true, true, 0 },
438 { V9::SUBCccr, true, true, 0 },
439 { V9::SUBCcci, true, true, 0 },
440 //{ V9::LDSTUB, true, true, 0 },
441 //{ V9::SWAP, true, true, 0 },
442 //{ V9::SWAPA, true, true, 0 },
443 //{ V9::CAS, true, true, 0 },
444 //{ V9::CASA, true, true, 0 },
445 //{ V9::CASX, true, true, 0 },
446 //{ V9::CASXA, true, true, 0 },
447 //{ V9::LDFSR, true, true, 0 },
448 //{ V9::LDFSRA, true, true, 0 },
449 //{ V9::LDXFSR, true, true, 0 },
450 //{ V9::LDXFSRA, true, true, 0 },
451 //{ V9::STFSR, true, true, 0 },
452 //{ V9::STFSRA, true, true, 0 },
453 //{ V9::STXFSR, true, true, 0 },
454 //{ V9::STXFSRA, true, true, 0 },
455 //{ V9::SAVED, true, true, 0 },
456 //{ V9::RESTORED, true, true, 0 },
457 //{ V9::FLUSH, true, true, 9 },
458 //{ V9::FLUSHW, true, true, 9 },
459 //{ V9::ALIGNADDR, true, true, 0 },
460 //{ V9::DONE, true, true, 0 },
461 //{ V9::RETRY, true, true, 0 },
462 //{ V9::TCC, true, true, 0 },
463 //{ V9::SHUTDOWN, true, true, 0 },
465 // Special cases for breaking group *before*
466 // CURRENTLY NOT SUPPORTED!
467 { V9::CALL, false, false, 0 },
468 { V9::JMPLCALLr, false, false, 0 },
469 { V9::JMPLCALLi, false, false, 0 },
470 { V9::JMPLRETr, false, false, 0 },
471 { V9::JMPLRETi, false, false, 0 },
473 // Special cases for breaking the group *after*
474 { V9::MULXr, true, true, (4+34)/2 },
475 { V9::MULXi, true, true, (4+34)/2 },
476 { V9::FDIVS, false, true, 0 },
477 { V9::FDIVD, false, true, 0 },
478 { V9::FDIVQ, false, true, 0 },
479 { V9::FSQRTS, false, true, 0 },
480 { V9::FSQRTD, false, true, 0 },
481 { V9::FSQRTQ, false, true, 0 },
482 //{ V9::FCMP{LE,GT,NE,EQ}, false, true, 0 },
484 // Instructions that introduce bubbles
485 //{ V9::MULScc, true, true, 2 },
486 //{ V9::SMULcc, true, true, (4+18)/2 },
487 //{ V9::UMULcc, true, true, (4+19)/2 },
488 { V9::SDIVXr, true, true, 68 },
489 { V9::SDIVXi, true, true, 68 },
490 { V9::UDIVXr, true, true, 68 },
491 { V9::UDIVXi, true, true, 68 },
492 //{ V9::SDIVcc, true, true, 36 },
493 //{ V9::UDIVcc, true, true, 37 },
494 { V9::WRCCRr, true, true, 4 },
495 { V9::WRCCRi, true, true, 4 },
496 //{ V9::WRPR, true, true, 4 },
497 //{ V9::RDCCR, true, true, 0 }, // no bubbles after, but see below
498 //{ V9::RDPR, true, true, 0 },
504 //---------------------------------------------------------------------------
505 // const InstrRUsageDelta SparcV9InstrUsageDeltas[]
508 // Changes to resource usage information in InstrClassRUsage for
509 // instructions that differ from other instructions in their class.
510 //---------------------------------------------------------------------------
512 static const InstrRUsageDelta SparcV9InstrUsageDeltas[] = {
514 // MachineOpCode, Resource, Start cycle, Num cycles
517 // JMPL counts as a load/store instruction for issue!
519 { V9::JMPLCALLr, LSIssueSlots.rid, 0, 1 },
520 { V9::JMPLCALLi, LSIssueSlots.rid, 0, 1 },
521 { V9::JMPLRETr, LSIssueSlots.rid, 0, 1 },
522 { V9::JMPLRETi, LSIssueSlots.rid, 0, 1 },
525 // Many instructions cannot issue for the next 2 cycles after an FCMP
526 // We model that with a fake resource FCMPDelayCycle.
528 { V9::FCMPS, FCMPDelayCycle.rid, 1, 3 },
529 { V9::FCMPD, FCMPDelayCycle.rid, 1, 3 },
530 { V9::FCMPQ, FCMPDelayCycle.rid, 1, 3 },
532 { V9::MULXr, FCMPDelayCycle.rid, 1, 1 },
533 { V9::MULXi, FCMPDelayCycle.rid, 1, 1 },
534 { V9::SDIVXr, FCMPDelayCycle.rid, 1, 1 },
535 { V9::SDIVXi, FCMPDelayCycle.rid, 1, 1 },
536 { V9::UDIVXr, FCMPDelayCycle.rid, 1, 1 },
537 { V9::UDIVXi, FCMPDelayCycle.rid, 1, 1 },
538 //{ V9::SMULcc, FCMPDelayCycle.rid, 1, 1 },
539 //{ V9::UMULcc, FCMPDelayCycle.rid, 1, 1 },
540 //{ V9::SDIVcc, FCMPDelayCycle.rid, 1, 1 },
541 //{ V9::UDIVcc, FCMPDelayCycle.rid, 1, 1 },
542 { V9::STDFr, FCMPDelayCycle.rid, 1, 1 },
543 { V9::STDFi, FCMPDelayCycle.rid, 1, 1 },
544 { V9::FMOVRSZ, FCMPDelayCycle.rid, 1, 1 },
545 { V9::FMOVRSLEZ,FCMPDelayCycle.rid, 1, 1 },
546 { V9::FMOVRSLZ, FCMPDelayCycle.rid, 1, 1 },
547 { V9::FMOVRSNZ, FCMPDelayCycle.rid, 1, 1 },
548 { V9::FMOVRSGZ, FCMPDelayCycle.rid, 1, 1 },
549 { V9::FMOVRSGEZ,FCMPDelayCycle.rid, 1, 1 },
552 // Some instructions are stalled in the GROUP stage if a CTI is in
553 // the E or C stage. We model that with a fake resource CTIDelayCycle.
555 { V9::LDDFr, CTIDelayCycle.rid, 1, 1 },
556 { V9::LDDFi, CTIDelayCycle.rid, 1, 1 },
557 //{ V9::LDDA, CTIDelayCycle.rid, 1, 1 },
558 //{ V9::LDDSTUB, CTIDelayCycle.rid, 1, 1 },
559 //{ V9::LDDSTUBA, CTIDelayCycle.rid, 1, 1 },
560 //{ V9::SWAP, CTIDelayCycle.rid, 1, 1 },
561 //{ V9::SWAPA, CTIDelayCycle.rid, 1, 1 },
562 //{ V9::CAS, CTIDelayCycle.rid, 1, 1 },
563 //{ V9::CASA, CTIDelayCycle.rid, 1, 1 },
564 //{ V9::CASX, CTIDelayCycle.rid, 1, 1 },
565 //{ V9::CASXA, CTIDelayCycle.rid, 1, 1 },
568 // Signed int loads of less than dword size return data in cycle N1 (not C)
569 // and put all loads in consecutive cycles into delayed load return mode.
571 { V9::LDSBr, LdReturn.rid, 2, -1 },
572 { V9::LDSBr, LdReturn.rid, 3, 1 },
573 { V9::LDSBi, LdReturn.rid, 2, -1 },
574 { V9::LDSBi, LdReturn.rid, 3, 1 },
576 { V9::LDSHr, LdReturn.rid, 2, -1 },
577 { V9::LDSHr, LdReturn.rid, 3, 1 },
578 { V9::LDSHi, LdReturn.rid, 2, -1 },
579 { V9::LDSHi, LdReturn.rid, 3, 1 },
581 { V9::LDSWr, LdReturn.rid, 2, -1 },
582 { V9::LDSWr, LdReturn.rid, 3, 1 },
583 { V9::LDSWi, LdReturn.rid, 2, -1 },
584 { V9::LDSWi, LdReturn.rid, 3, 1 },
587 // RDPR from certain registers and RD from any register are not dispatchable
588 // until four clocks after they reach the head of the instr. buffer.
589 // Together with their single-issue requirement, this means all four issue
590 // slots are effectively blocked for those cycles, plus the issue cycle.
591 // This does not increase the latency of the instruction itself.
593 { V9::RDCCR, AllIssueSlots.rid, 0, 5 },
594 { V9::RDCCR, AllIssueSlots.rid, 0, 5 },
595 { V9::RDCCR, AllIssueSlots.rid, 0, 5 },
596 { V9::RDCCR, AllIssueSlots.rid, 0, 5 },
598 #undef EXPLICIT_BUBBLES_NEEDED
599 #ifdef EXPLICIT_BUBBLES_NEEDED
601 // MULScc inserts one bubble.
602 // This means it breaks the current group (captured in UltraSparcV9SchedInfo)
603 // *and occupies all issue slots for the next cycle
605 //{ V9::MULScc, AllIssueSlots.rid, 2, 2-1 },
606 //{ V9::MULScc, AllIssueSlots.rid, 2, 2-1 },
607 //{ V9::MULScc, AllIssueSlots.rid, 2, 2-1 },
608 //{ V9::MULScc, AllIssueSlots.rid, 2, 2-1 },
611 // SMULcc inserts between 4 and 18 bubbles, depending on #leading 0s in rs1.
612 // We just model this with a simple average.
614 //{ V9::SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
615 //{ V9::SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
616 //{ V9::SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
617 //{ V9::SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
619 // SMULcc inserts between 4 and 19 bubbles, depending on #leading 0s in rs1.
620 //{ V9::UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
621 //{ V9::UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
622 //{ V9::UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
623 //{ V9::UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
626 // MULX inserts between 4 and 34 bubbles, depending on #leading 0s in rs1.
628 { V9::MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
629 { V9::MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
630 { V9::MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
631 { V9::MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
634 // SDIVcc inserts 36 bubbles.
636 //{ V9::SDIVcc, AllIssueSlots.rid, 2, 36-1 },
637 //{ V9::SDIVcc, AllIssueSlots.rid, 2, 36-1 },
638 //{ V9::SDIVcc, AllIssueSlots.rid, 2, 36-1 },
639 //{ V9::SDIVcc, AllIssueSlots.rid, 2, 36-1 },
641 // UDIVcc inserts 37 bubbles.
642 //{ V9::UDIVcc, AllIssueSlots.rid, 2, 37-1 },
643 //{ V9::UDIVcc, AllIssueSlots.rid, 2, 37-1 },
644 //{ V9::UDIVcc, AllIssueSlots.rid, 2, 37-1 },
645 //{ V9::UDIVcc, AllIssueSlots.rid, 2, 37-1 },
648 // SDIVX inserts 68 bubbles.
650 { V9::SDIVX, AllIssueSlots.rid, 2, 68-1 },
651 { V9::SDIVX, AllIssueSlots.rid, 2, 68-1 },
652 { V9::SDIVX, AllIssueSlots.rid, 2, 68-1 },
653 { V9::SDIVX, AllIssueSlots.rid, 2, 68-1 },
656 // UDIVX inserts 68 bubbles.
658 { V9::UDIVX, AllIssueSlots.rid, 2, 68-1 },
659 { V9::UDIVX, AllIssueSlots.rid, 2, 68-1 },
660 { V9::UDIVX, AllIssueSlots.rid, 2, 68-1 },
661 { V9::UDIVX, AllIssueSlots.rid, 2, 68-1 },
664 // WR inserts 4 bubbles.
666 //{ V9::WR, AllIssueSlots.rid, 2, 68-1 },
667 //{ V9::WR, AllIssueSlots.rid, 2, 68-1 },
668 //{ V9::WR, AllIssueSlots.rid, 2, 68-1 },
669 //{ V9::WR, AllIssueSlots.rid, 2, 68-1 },
672 // WRPR inserts 4 bubbles.
674 //{ V9::WRPR, AllIssueSlots.rid, 2, 68-1 },
675 //{ V9::WRPR, AllIssueSlots.rid, 2, 68-1 },
676 //{ V9::WRPR, AllIssueSlots.rid, 2, 68-1 },
677 //{ V9::WRPR, AllIssueSlots.rid, 2, 68-1 },
680 // DONE inserts 9 bubbles.
682 //{ V9::DONE, AllIssueSlots.rid, 2, 9-1 },
683 //{ V9::DONE, AllIssueSlots.rid, 2, 9-1 },
684 //{ V9::DONE, AllIssueSlots.rid, 2, 9-1 },
685 //{ V9::DONE, AllIssueSlots.rid, 2, 9-1 },
688 // RETRY inserts 9 bubbles.
690 //{ V9::RETRY, AllIssueSlots.rid, 2, 9-1 },
691 //{ V9::RETRY, AllIssueSlots.rid, 2, 9-1 },
692 //{ V9::RETRY, AllIssueSlots.rid, 2, 9-1 },
693 //{ V9::RETRY, AllIssueSlots.rid, 2, 9-1 },
695 #endif /*EXPLICIT_BUBBLES_NEEDED */
698 // Additional delays to be captured in code:
699 // 1. RDPR from several state registers (page 349)
700 // 2. RD from *any* register (page 349)
701 // 3. Writes to TICK, PSTATE, TL registers and FLUSH{W} instr (page 349)
702 // 4. Integer store can be in same group as instr producing value to store.
703 // 5. BICC and BPICC can be in the same group as instr producing CC (pg 350)
704 // 6. FMOVr cannot be in the same or next group as an IEU instr (pg 351).
705 // 7. The second instr. of a CTI group inserts 9 bubbles (pg 351)
706 // 8. WR{PR}, SVAE, SAVED, RESTORE, RESTORED, RETURN, RETRY, and DONE that
707 // follow an annulling branch cannot be issued in the same group or in
708 // the 3 groups following the branch.
709 // 9. A predicted annulled load does not stall dependent instructions.
710 // Other annulled delay slot instructions *do* stall dependents, so
711 // nothing special needs to be done for them during scheduling.
712 //10. Do not put a load use that may be annulled in the same group as the
713 // branch. The group will stall until the load returns.
714 //11. Single-prec. FP loads lock 2 registers, for dependency checking.
717 // Additional delays we cannot or will not capture:
718 // 1. If DCTI is last word of cache line, it is delayed until next line can be
719 // fetched. Also, other DCTI alignment-related delays (pg 352)
720 // 2. Load-after-store is delayed by 7 extra cycles if load hits in D-Cache.
721 // Also, several other store-load and load-store conflicts (pg 358)
722 // 3. MEMBAR, LD{X}FSR, LDD{A} and a bunch of other load stalls (pg 358)
723 // 4. There can be at most 8 outstanding buffered store instructions
724 // (including some others like MEMBAR, LDSTUB, CAS{AX}, and FLUSH)
728 //---------------------------------------------------------------------------
729 // class SparcV9SchedInfo
732 // Scheduling information for the UltraSPARC.
733 // Primarily just initializes machine-dependent parameters in
734 // class TargetSchedInfo.
735 //---------------------------------------------------------------------------
738 SparcV9SchedInfo::SparcV9SchedInfo(const TargetMachine& tgt)
739 : TargetSchedInfo(tgt,
740 (unsigned int) SPARC_NUM_SCHED_CLASSES,
742 SparcV9InstrUsageDeltas,
743 SparcV9InstrIssueDeltas,
744 sizeof(SparcV9InstrUsageDeltas)/sizeof(InstrRUsageDelta),
745 sizeof(SparcV9InstrIssueDeltas)/sizeof(InstrIssueDelta))
747 maxNumIssueTotal = 4;
748 longestIssueConflict = 0; // computed from issuesGaps[]
750 // must be called after above parameters are initialized.
751 initializeResources();
755 SparcV9SchedInfo::initializeResources()
757 // Compute TargetSchedInfo::instrRUsages and TargetSchedInfo::issueGaps
758 TargetSchedInfo::initializeResources();
760 // Machine-dependent fixups go here. None for now.