1 //===-- SparcV9TargetMachine.cpp - SparcV9 Target Machine Implementation --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Primary interface to machine description for the UltraSPARC. Primarily just
11 // initializes machine-dependent parameters in class TargetMachine, and creates
12 // machine-dependent subclasses for classes such as TargetInstrInfo.
14 //===----------------------------------------------------------------------===//
16 #include "llvm/Function.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/Assembly/PrintModulePass.h"
19 #include "llvm/CodeGen/InstrScheduling.h"
20 #include "llvm/CodeGen/IntrinsicLowering.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/Target/TargetMachineRegistry.h"
25 #include "llvm/Transforms/Scalar.h"
26 #include "MappingInfo.h"
27 #include "MachineFunctionInfo.h"
28 #include "MachineCodeForInstruction.h"
29 #include "SparcV9Internals.h"
30 #include "SparcV9TargetMachine.h"
31 #include "SparcV9BurgISel.h"
32 #include "llvm/Support/CommandLine.h"
35 static const unsigned ImplicitRegUseList[] = { 0 }; /* not used yet */
36 // Build the MachineInstruction Description Array...
37 const TargetInstrDescriptor llvm::SparcV9MachineInstrDesc[] = {
38 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
39 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
40 { OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
41 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS, 0, \
42 ImplicitRegUseList, ImplicitRegUseList },
43 #include "SparcV9Instr.def"
46 //---------------------------------------------------------------------------
47 // Command line options to control choice of code generation passes.
48 //---------------------------------------------------------------------------
51 bool EmitMappingInfo = false;
55 cl::opt<bool> DisableSched("disable-sched",
56 cl::desc("Disable local scheduling pass"));
58 cl::opt<bool> DisablePeephole("disable-peephole",
59 cl::desc("Disable peephole optimization pass"));
61 cl::opt<bool, true> EmitMappingInfoOpt("enable-maps",
62 cl::location(EmitMappingInfo),
64 cl::desc("Emit LLVM-to-MachineCode mapping info to assembly"));
66 cl::opt<bool> DisableStrip("disable-strip",
67 cl::desc("Do not strip the LLVM bytecode in executable"));
70 cl::opt<bool> EnableModSched("enable-ModSched",
71 cl::desc("Enable modulo scheduling pass instead of local scheduling"));
73 // Register the target.
74 RegisterTarget<SparcV9TargetMachine> X("sparcv9", " SPARC V9");
77 unsigned SparcV9TargetMachine::getJITMatchQuality() {
78 #if defined(__sparcv9)
85 unsigned SparcV9TargetMachine::getModuleMatchQuality(const Module &M) {
86 if (M.getEndianness() == Module::BigEndian &&
87 M.getPointerSize() == Module::Pointer64)
88 return 10; // Direct match
89 else if (M.getEndianness() != Module::AnyEndianness ||
90 M.getPointerSize() != Module::AnyPointerSize)
91 return 0; // Match for some other target
93 return getJITMatchQuality()/2;
96 //===---------------------------------------------------------------------===//
97 // Code generation/destruction passes
98 //===---------------------------------------------------------------------===//
101 class ConstructMachineFunction : public FunctionPass {
102 TargetMachine &Target;
104 ConstructMachineFunction(TargetMachine &T) : Target(T) {}
106 const char *getPassName() const {
107 return "ConstructMachineFunction";
110 bool runOnFunction(Function &F) {
111 MachineFunction::construct(&F, Target).getInfo<SparcV9FunctionInfo>()->CalculateArgSize();
116 struct DestroyMachineFunction : public FunctionPass {
117 const char *getPassName() const { return "DestroyMachineFunction"; }
119 static void freeMachineCode(Instruction &I) {
120 MachineCodeForInstruction::destroy(&I);
123 bool runOnFunction(Function &F) {
124 for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
125 for (BasicBlock::iterator I = FI->begin(), E = FI->end(); I != E; ++I)
126 MachineCodeForInstruction::get(I).dropAllReferences();
128 for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
129 for_each(FI->begin(), FI->end(), freeMachineCode);
131 MachineFunction::destruct(&F);
136 FunctionPass *createMachineCodeConstructionPass(TargetMachine &Target) {
137 return new ConstructMachineFunction(Target);
141 FunctionPass *llvm::createSparcV9MachineCodeDestructionPass() {
142 return new DestroyMachineFunction();
146 SparcV9TargetMachine::SparcV9TargetMachine(const Module &M,
147 IntrinsicLowering *il)
148 : TargetMachine("UltraSparcV9-Native", il, false),
155 /// addPassesToEmitAssembly - This method controls the entire code generation
156 /// process for the ultra sparc.
159 SparcV9TargetMachine::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out)
161 // FIXME: Implement efficient support for garbage collection intrinsics.
162 PM.add(createLowerGCPass());
164 // Replace malloc and free instructions with library calls.
165 PM.add(createLowerAllocationsPass());
167 // FIXME: implement the switch instruction in the instruction selector.
168 PM.add(createLowerSwitchPass());
170 // FIXME: implement the invoke/unwind instructions!
171 PM.add(createLowerInvokePass());
173 // decompose multi-dimensional array references into single-dim refs
174 PM.add(createDecomposeMultiDimRefsPass());
176 // Lower LLVM code to the form expected by the SPARCv9 instruction selector.
177 PM.add(createPreSelectionPass(*this));
178 PM.add(createLowerSelectPass());
180 // Run basic LLVM dataflow optimizations, to clean up after pre-selection.
181 PM.add(createReassociatePass());
182 PM.add(createLICMPass());
183 PM.add(createGCSEPass());
185 // If the user's trying to read the generated code, they'll need to see the
186 // transformed input.
187 if (PrintMachineCode)
188 PM.add(new PrintModulePass());
190 // Construct and initialize the MachineFunction object for this fn.
191 PM.add(createMachineCodeConstructionPass(*this));
193 // Insert empty stackslots in the stack frame of each function
194 // so %fp+offset-8 and %fp+offset-16 are empty slots now!
195 PM.add(createStackSlotsPass(*this));
197 PM.add(createSparcV9BurgInstSelector(*this));
200 PM.add(createMachineFunctionPrinterPass(&std::cerr, "Before modulo scheduling:\n"));
202 //Use ModuloScheduling if enabled, otherwise use local scheduling if not disabled.
204 PM.add(createModuloSchedulingPass(*this));
207 PM.add(createInstructionSchedulingWithSSAPass(*this));
210 if (PrintMachineCode)
211 PM.add(createMachineFunctionPrinterPass(&std::cerr, "Before reg alloc:\n"));
213 PM.add(getRegisterAllocator(*this));
215 if (PrintMachineCode)
216 PM.add(createMachineFunctionPrinterPass(&std::cerr, "After reg alloc:\n"));
218 PM.add(createPrologEpilogInsertionPass());
220 if (!DisablePeephole)
221 PM.add(createPeepholeOptsPass(*this));
223 if (PrintMachineCode)
224 PM.add(createMachineFunctionPrinterPass(&std::cerr, "Final code:\n"));
226 if (EmitMappingInfo) {
227 PM.add(createInternalGlobalMapperPass());
228 PM.add(getMappingInfoAsmPrinterPass(Out));
231 // Output assembly language to the .s file. Assembly emission is split into
232 // two parts: Function output and Global value output. This is because
233 // function output is pipelined with all of the rest of code generation stuff,
234 // allowing machine code representations for functions to be free'd after the
235 // function has been emitted.
236 PM.add(createAsmPrinterPass(Out, *this));
238 // Free machine-code IR which is no longer needed:
239 PM.add(createSparcV9MachineCodeDestructionPass());
241 // Emit bytecode to the assembly file into its special section next
242 if (EmitMappingInfo) {
243 // Strip all of the symbols from the bytecode so that it will be smaller...
245 PM.add(createSymbolStrippingPass());
246 PM.add(createBytecodeAsmPrinterPass(Out));
252 /// addPassesToJITCompile - This method controls the JIT method of code
253 /// generation for the UltraSparcV9.
255 void SparcV9JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
256 // FIXME: Implement efficient support for garbage collection intrinsics.
257 PM.add(createLowerGCPass());
259 // Replace malloc and free instructions with library calls.
260 PM.add(createLowerAllocationsPass());
262 // FIXME: implement the switch instruction in the instruction selector.
263 PM.add(createLowerSwitchPass());
265 // FIXME: implement the invoke/unwind instructions!
266 PM.add(createLowerInvokePass());
268 // decompose multi-dimensional array references into single-dim refs
269 PM.add(createDecomposeMultiDimRefsPass());
271 // Lower LLVM code to the form expected by the SPARCv9 instruction selector.
272 PM.add(createPreSelectionPass(TM));
273 PM.add(createLowerSelectPass());
275 // Run basic LLVM dataflow optimizations, to clean up after pre-selection.
276 PM.add(createReassociatePass());
277 // FIXME: these passes crash the FunctionPassManager when being added...
278 //PM.add(createLICMPass());
279 //PM.add(createGCSEPass());
281 // If the user's trying to read the generated code, they'll need to see the
282 // transformed input.
283 if (PrintMachineCode)
284 PM.add(new PrintFunctionPass());
286 // Construct and initialize the MachineFunction object for this fn.
287 PM.add(createMachineCodeConstructionPass(TM));
289 PM.add(createSparcV9BurgInstSelector(TM));
291 if (PrintMachineCode)
292 PM.add(createMachineFunctionPrinterPass(&std::cerr, "Before reg alloc:\n"));
294 PM.add(getRegisterAllocator(TM));
296 if (PrintMachineCode)
297 PM.add(createMachineFunctionPrinterPass(&std::cerr, "After reg alloc:\n"));
299 PM.add(createPrologEpilogInsertionPass());
301 if (!DisablePeephole)
302 PM.add(createPeepholeOptsPass(TM));
304 if (PrintMachineCode)
305 PM.add(createMachineFunctionPrinterPass(&std::cerr, "Final code:\n"));