1 //===-- SparcV9TargetMachine.cpp - SparcV9 Target Machine Implementation --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Primary interface to machine description for the UltraSPARC. Primarily just
11 // initializes machine-dependent parameters in class TargetMachine, and creates
12 // machine-dependent subclasses for classes such as TargetInstrInfo.
14 //===----------------------------------------------------------------------===//
16 #include "llvm/Function.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/Assembly/PrintModulePass.h"
19 #include "llvm/CodeGen/InstrScheduling.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/Target/TargetMachineRegistry.h"
24 #include "llvm/Transforms/Scalar.h"
25 #include "MappingInfo.h"
26 #include "MachineFunctionInfo.h"
27 #include "MachineCodeForInstruction.h"
28 #include "SparcV9Internals.h"
29 #include "SparcV9TargetMachine.h"
30 #include "SparcV9BurgISel.h"
31 #include "llvm/Support/CommandLine.h"
34 static const unsigned ImplicitRegUseList[] = { 0 }; /* not used yet */
35 // Build the MachineInstruction Description Array...
36 const TargetInstrDescriptor llvm::SparcV9MachineInstrDesc[] = {
37 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
38 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
39 { OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
40 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS, 0, \
41 ImplicitRegUseList, ImplicitRegUseList, 0 },
42 #include "SparcV9Instr.def"
45 //---------------------------------------------------------------------------
46 // Command line options to control choice of code generation passes.
47 //---------------------------------------------------------------------------
50 bool EmitMappingInfo = false;
54 cl::opt<bool> DisableSched("disable-sched",
55 cl::desc("Disable sparcv9 local scheduling pass"));
57 cl::opt<bool> DisablePeephole("disable-peephole",
58 cl::desc("Disable sparcv9 peephole optimization pass"));
60 cl::opt<bool, true> EmitMappingInfoOpt("enable-maps", cl::ReallyHidden,
61 cl::location(EmitMappingInfo),
63 cl::desc("Emit LLVM-to-MachineCode mapping info to assembly"));
65 cl::opt<bool> EnableModSched("enable-modsched",
66 cl::desc("Enable modulo scheduling pass"), cl::Hidden);
68 cl::opt<bool> EnableSBModSched("enable-modschedSB",
69 cl::desc("Enable superblock modulo scheduling (experimental)"), cl::Hidden);
71 // Register the target.
72 RegisterTarget<SparcV9TargetMachine> X("sparcv9", " SPARC V9");
75 unsigned SparcV9TargetMachine::getJITMatchQuality() {
76 #if defined(__sparcv9)
83 unsigned SparcV9TargetMachine::getModuleMatchQuality(const Module &M) {
84 // We strongly match "sparcv9-*".
85 std::string TT = M.getTargetTriple();
86 if (TT.size() >= 8 && std::string(TT.begin(), TT.begin()+8) == "sparcv9-")
89 if (M.getEndianness() == Module::BigEndian &&
90 M.getPointerSize() == Module::Pointer64)
91 return 10; // Weak match
92 else if (M.getEndianness() != Module::AnyEndianness ||
93 M.getPointerSize() != Module::AnyPointerSize)
94 return 0; // Match for some other target
96 return getJITMatchQuality()/2;
99 //===---------------------------------------------------------------------===//
100 // Code generation/destruction passes
101 //===---------------------------------------------------------------------===//
104 class ConstructMachineFunction : public FunctionPass {
105 TargetMachine &Target;
107 ConstructMachineFunction(TargetMachine &T) : Target(T) {}
109 const char *getPassName() const {
110 return "ConstructMachineFunction";
113 bool runOnFunction(Function &F) {
114 MachineFunction::construct(&F, Target).getInfo<SparcV9FunctionInfo>()->CalculateArgSize();
119 struct DestroyMachineFunction : public FunctionPass {
120 const char *getPassName() const { return "DestroyMachineFunction"; }
122 static void freeMachineCode(Instruction &I) {
123 MachineCodeForInstruction::destroy(&I);
126 bool runOnFunction(Function &F) {
127 for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
128 for (BasicBlock::iterator I = FI->begin(), E = FI->end(); I != E; ++I)
129 MachineCodeForInstruction::get(I).dropAllReferences();
131 for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
132 for_each(FI->begin(), FI->end(), freeMachineCode);
134 MachineFunction::destruct(&F);
139 FunctionPass *createMachineCodeConstructionPass(TargetMachine &Target) {
140 return new ConstructMachineFunction(Target);
144 FunctionPass *llvm::createSparcV9MachineCodeDestructionPass() {
145 return new DestroyMachineFunction();
149 SparcV9TargetMachine::SparcV9TargetMachine(const Module &M,
150 const std::string &FS)
151 : TargetMachine("UltraSparcV9-Native", false),
158 /// addPassesToEmitFile - This method controls the entire code generation
159 /// process for the ultra sparc.
162 SparcV9TargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out,
163 CodeGenFileType FileType,
165 if (FileType != TargetMachine::AssemblyFile) return true;
167 // FIXME: Implement efficient support for garbage collection intrinsics.
168 PM.add(createLowerGCPass());
170 // Replace malloc and free instructions with library calls.
171 PM.add(createLowerAllocationsPass());
173 // FIXME: implement the invoke/unwind instructions!
174 PM.add(createLowerInvokePass());
176 // FIXME: implement the switch instruction in the instruction selector.
177 PM.add(createLowerSwitchPass());
179 // decompose multi-dimensional array references into single-dim refs
180 PM.add(createDecomposeMultiDimRefsPass());
182 // Lower LLVM code to the form expected by the SPARCv9 instruction selector.
183 PM.add(createPreSelectionPass(*this));
184 PM.add(createLowerSelectPass());
186 // If the user's trying to read the generated code, they'll need to see the
187 // transformed input.
188 if (PrintMachineCode)
189 PM.add(new PrintModulePass());
191 // Construct and initialize the MachineFunction object for this fn.
192 PM.add(createMachineCodeConstructionPass(*this));
194 // Insert empty stackslots in the stack frame of each function
195 // so %fp+offset-8 and %fp+offset-16 are empty slots now!
196 PM.add(createStackSlotsPass(*this));
198 PM.add(createSparcV9BurgInstSelector(*this));
200 if(!DisableSched && PrintMachineCode)
201 PM.add(createMachineFunctionPrinterPass(&std::cerr, "Before local scheduling:\n"));
204 PM.add(createInstructionSchedulingWithSSAPass(*this));
206 if(PrintMachineCode && EnableModSched)
207 PM.add(createMachineFunctionPrinterPass(&std::cerr, "Before modulo scheduling:\n"));
209 //Use ModuloScheduling if enabled, otherwise use local scheduling if not disabled.
211 PM.add(createModuloSchedulingPass(*this));
214 PM.add(createModuloSchedulingSBPass(*this));
216 if (PrintMachineCode)
217 PM.add(createMachineFunctionPrinterPass(&std::cerr, "Before reg alloc:\n"));
219 PM.add(getRegisterAllocator(*this));
221 if (PrintMachineCode)
222 PM.add(createMachineFunctionPrinterPass(&std::cerr, "After reg alloc:\n"));
224 PM.add(createPrologEpilogInsertionPass());
226 if (!DisablePeephole)
227 PM.add(createPeepholeOptsPass(*this));
229 if (PrintMachineCode)
230 PM.add(createMachineFunctionPrinterPass(&std::cerr, "Final code:\n"));
232 if (EmitMappingInfo) {
233 PM.add(createInternalGlobalMapperPass());
234 PM.add(getMappingInfoAsmPrinterPass(Out));
237 // Output assembly language to the .s file. Assembly emission is split into
238 // two parts: Function output and Global value output. This is because
239 // function output is pipelined with all of the rest of code generation stuff,
240 // allowing machine code representations for functions to be free'd after the
241 // function has been emitted.
242 PM.add(createAsmPrinterPass(Out, *this));
244 // Free machine-code IR which is no longer needed:
245 PM.add(createSparcV9MachineCodeDestructionPass());
247 // Emit bytecode to the assembly file into its special section next
249 PM.add(createBytecodeAsmPrinterPass(Out));
254 /// addPassesToJITCompile - This method controls the JIT method of code
255 /// generation for the UltraSparcV9.
257 void SparcV9JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
258 // FIXME: Implement efficient support for garbage collection intrinsics.
259 PM.add(createLowerGCPass());
261 // Replace malloc and free instructions with library calls.
262 PM.add(createLowerAllocationsPass());
264 // FIXME: implement the invoke/unwind instructions!
265 PM.add(createLowerInvokePass());
267 // FIXME: implement the switch instruction in the instruction selector.
268 PM.add(createLowerSwitchPass());
270 // decompose multi-dimensional array references into single-dim refs
271 PM.add(createDecomposeMultiDimRefsPass());
273 // Lower LLVM code to the form expected by the SPARCv9 instruction selector.
274 PM.add(createPreSelectionPass(TM));
275 PM.add(createLowerSelectPass());
277 // If the user's trying to read the generated code, they'll need to see the
278 // transformed input.
279 if (PrintMachineCode)
280 PM.add(new PrintFunctionPass());
282 // Construct and initialize the MachineFunction object for this fn.
283 PM.add(createMachineCodeConstructionPass(TM));
285 PM.add(createSparcV9BurgInstSelector(TM));
287 if (PrintMachineCode)
288 PM.add(createMachineFunctionPrinterPass(&std::cerr, "Before reg alloc:\n"));
290 PM.add(getRegisterAllocator(TM));
292 if (PrintMachineCode)
293 PM.add(createMachineFunctionPrinterPass(&std::cerr, "After reg alloc:\n"));
295 PM.add(createPrologEpilogInsertionPass());
297 if (!DisablePeephole)
298 PM.add(createPeepholeOptsPass(TM));
300 if (PrintMachineCode)
301 PM.add(createMachineFunctionPrinterPass(&std::cerr, "Final code:\n"));