1 //***************************************************************************
8 // 7/15/01 - Vikram Adve - Created
9 //**************************************************************************/
11 #include "llvm/CodeGen/Sparc.h"
12 #include "SparcInternals.h"
13 #include "llvm/Method.h"
14 #include "llvm/CodeGen/InstrScheduling.h"
15 #include "llvm/CodeGen/InstrSelection.h"
19 //---------------------------------------------------------------------------
20 // class UltraSparcInstrInfo
23 // Information about individual instructions.
24 // Most information is stored in the SparcMachineInstrDesc array above.
25 // Other information is computed on demand, and most such functions
26 // default to member functions in base class MachineInstrInfo.
27 //---------------------------------------------------------------------------
30 UltraSparcInstrInfo::UltraSparcInstrInfo()
31 : MachineInstrInfo(SparcMachineInstrDesc,
32 /*descSize = */ NUM_TOTAL_OPCODES,
33 /*numRealOpCodes = */ NUM_REAL_OPCODES)
38 //---------------------------------------------------------------------------
39 // class UltraSparcSchedInfo
42 // Scheduling information for the UltraSPARC.
43 // Primarily just initializes machine-dependent parameters in
44 // class MachineSchedInfo.
45 //---------------------------------------------------------------------------
48 UltraSparcSchedInfo::UltraSparcSchedInfo(const MachineInstrInfo* mii)
49 : MachineSchedInfo((unsigned int) SPARC_NUM_SCHED_CLASSES,
52 SparcInstrUsageDeltas,
53 SparcInstrIssueDeltas,
54 sizeof(SparcInstrUsageDeltas)/sizeof(InstrRUsageDelta),
55 sizeof(SparcInstrIssueDeltas)/sizeof(InstrIssueDelta))
58 longestIssueConflict = 0; // computed from issuesGaps[]
60 branchMispredictPenalty = 4; // 4 for SPARC IIi
61 branchTargetUnknownPenalty = 2; // 2 for SPARC IIi
62 l1DCacheMissPenalty = 8; // 7 or 9 for SPARC IIi
63 l1ICacheMissPenalty = 8; // ? for SPARC IIi
65 inOrderLoads = true; // true for SPARC IIi
66 inOrderIssue = true; // true for SPARC IIi
67 inOrderExec = false; // false for most architectures
68 inOrderRetire= true; // true for most architectures
70 // must be called after above parameters are initialized.
71 this->initializeResources();
75 UltraSparcSchedInfo::initializeResources()
77 // Compute MachineSchedInfo::instrRUsages and MachineSchedInfo::issueGaps
78 MachineSchedInfo::initializeResources();
80 // Machine-dependent fixups go here. None for now.
84 //---------------------------------------------------------------------------
85 // class UltraSparcMachine
88 // Primary interface to machine description for the UltraSPARC.
89 // Primarily just initializes machine-dependent parameters in
90 // class TargetMachine, and creates machine-dependent subclasses
91 // for classes such as MachineInstrInfo.
93 //---------------------------------------------------------------------------
95 UltraSparc::UltraSparc() : TargetMachine("UltraSparc-Native"),
96 InstSchedulingInfo(&InstInfo) {
97 optSizeForSubWordData = 4;
99 maxAtomicMemOpWordSize = 8;
100 zeroRegNum = 0; // %g0 always gives 0 on Sparc
103 bool UltraSparc::compileMethod(Method *M) {
104 if (SelectInstructionsForMethod(M, *this)) {
105 cerr << "Instruction selection failed for method " << M->getName()
110 if (ScheduleInstructionsWithSSA(M, *this, InstSchedulingInfo)) {
111 cerr << "Instruction scheduling before allocation failed for method "
112 << M->getName() << "\n\n";
118 // allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine
119 // that implements the Sparc backend.
121 TargetMachine *allocateSparcTargetMachine() { return new UltraSparc(); }