2 //***************************************************************************
9 // 7/15/01 - Vikram Adve - Created
10 //**************************************************************************/
12 #include "llvm/Target/Sparc.h"
13 #include "SparcInternals.h"
14 #include "llvm/Method.h"
15 #include "llvm/CodeGen/InstrScheduling.h"
16 #include "llvm/CodeGen/InstrSelection.h"
18 #include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h"
19 #include "llvm/CodeGen/PhyRegAlloc.h"
21 // Build the MachineInstruction Description Array...
22 const MachineInstrDescriptor SparcMachineInstrDesc[] = {
23 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
24 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
25 { OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
26 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS },
27 #include "SparcInstr.def"
30 //----------------------------------------------------------------------------
31 // allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine
32 // that implements the Sparc backend. (the llvm/CodeGen/Sparc.h interface)
33 //----------------------------------------------------------------------------
35 TargetMachine *allocateSparcTargetMachine() { return new UltraSparc(); }
39 //----------------------------------------------------------------------------
40 // Entry point for register allocation for a module
41 //----------------------------------------------------------------------------
43 void AllocateRegisters(Method *M, TargetMachine &TM)
46 if ( (M)->isExternal() ) // don't process prototypes
50 cout << endl << "******************** Method "<< (M)->getName();
51 cout << " ********************" <<endl;
54 MethodLiveVarInfo LVI(M ); // Analyze live varaibles
58 PhyRegAlloc PRA(M, TM , &LVI); // allocate registers
59 PRA.allocateRegisters();
62 if( DEBUG_RA ) cout << endl << "Register allocation complete!" << endl;
68 //---------------------------------------------------------------------------
69 // class UltraSparcInstrInfo
72 // Information about individual instructions.
73 // Most information is stored in the SparcMachineInstrDesc array above.
74 // Other information is computed on demand, and most such functions
75 // default to member functions in base class MachineInstrInfo.
76 //---------------------------------------------------------------------------
79 UltraSparcInstrInfo::UltraSparcInstrInfo()
80 : MachineInstrInfo(SparcMachineInstrDesc,
81 /*descSize = */ NUM_TOTAL_OPCODES,
82 /*numRealOpCodes = */ NUM_REAL_OPCODES)
87 //---------------------------------------------------------------------------
88 // class UltraSparcSchedInfo
91 // Scheduling information for the UltraSPARC.
92 // Primarily just initializes machine-dependent parameters in
93 // class MachineSchedInfo.
94 //---------------------------------------------------------------------------
97 UltraSparcSchedInfo::UltraSparcSchedInfo(const MachineInstrInfo* mii)
98 : MachineSchedInfo((unsigned int) SPARC_NUM_SCHED_CLASSES,
101 SparcInstrUsageDeltas,
102 SparcInstrIssueDeltas,
103 sizeof(SparcInstrUsageDeltas)/sizeof(InstrRUsageDelta),
104 sizeof(SparcInstrIssueDeltas)/sizeof(InstrIssueDelta))
106 maxNumIssueTotal = 4;
107 longestIssueConflict = 0; // computed from issuesGaps[]
109 branchMispredictPenalty = 4; // 4 for SPARC IIi
110 branchTargetUnknownPenalty = 2; // 2 for SPARC IIi
111 l1DCacheMissPenalty = 8; // 7 or 9 for SPARC IIi
112 l1ICacheMissPenalty = 8; // ? for SPARC IIi
114 inOrderLoads = true; // true for SPARC IIi
115 inOrderIssue = true; // true for SPARC IIi
116 inOrderExec = false; // false for most architectures
117 inOrderRetire= true; // true for most architectures
119 // must be called after above parameters are initialized.
120 this->initializeResources();
124 UltraSparcSchedInfo::initializeResources()
126 // Compute MachineSchedInfo::instrRUsages and MachineSchedInfo::issueGaps
127 MachineSchedInfo::initializeResources();
129 // Machine-dependent fixups go here. None for now.
135 //---------------------------------------------------------------------------
136 // class UltraSparcMachine
139 // Primary interface to machine description for the UltraSPARC.
140 // Primarily just initializes machine-dependent parameters in
141 // class TargetMachine, and creates machine-dependent subclasses
142 // for classes such as MachineInstrInfo.
144 //---------------------------------------------------------------------------
146 UltraSparc::UltraSparc()
147 : TargetMachine("UltraSparc-Native"),
149 schedInfo(&instrInfo),
152 optSizeForSubWordData = 4;
153 minMemOpWordSize = 8;
154 maxAtomicMemOpWordSize = 8;
161 bool UltraSparc::compileMethod(Method *M) {
163 if (SelectInstructionsForMethod(M, *this))
165 cerr << "Instruction selection failed for method " << M->getName()
170 if (ScheduleInstructionsWithSSA(M, *this))
172 cerr << "Instruction scheduling before allocation failed for method "
173 << M->getName() << "\n\n";
177 AllocateRegisters(M, *this); // allocate registers