1 //===-- SparcV9TargetMachine.cpp - SparcV9 Target Machine Implementation --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Primary interface to machine description for the UltraSPARC. Primarily just
11 // initializes machine-dependent parameters in class TargetMachine, and creates
12 // machine-dependent subclasses for classes such as TargetInstrInfo.
14 //===----------------------------------------------------------------------===//
16 #include "llvm/Function.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/Assembly/PrintModulePass.h"
19 #include "llvm/CodeGen/InstrScheduling.h"
20 #include "llvm/CodeGen/IntrinsicLowering.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/Target/TargetMachineRegistry.h"
25 #include "llvm/Transforms/Scalar.h"
26 #include "MappingInfo.h"
27 #include "MachineFunctionInfo.h"
28 #include "MachineCodeForInstruction.h"
29 #include "SparcV9Internals.h"
30 #include "SparcV9TargetMachine.h"
31 #include "SparcV9BurgISel.h"
32 #include "llvm/Support/CommandLine.h"
35 static const unsigned ImplicitRegUseList[] = { 0 }; /* not used yet */
36 // Build the MachineInstruction Description Array...
37 const TargetInstrDescriptor llvm::SparcV9MachineInstrDesc[] = {
38 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
39 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
40 { OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
41 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS, 0, \
42 ImplicitRegUseList, ImplicitRegUseList },
43 #include "SparcV9Instr.def"
46 //---------------------------------------------------------------------------
47 // Command line options to control choice of code generation passes.
48 //---------------------------------------------------------------------------
51 bool EmitMappingInfo = false;
55 cl::opt<bool> DisableSched("disable-sched",
56 cl::desc("Disable local scheduling pass"));
58 cl::opt<bool> DisablePeephole("disable-peephole",
59 cl::desc("Disable peephole optimization pass"));
61 cl::opt<bool, true> EmitMappingInfoOpt("enable-maps",
62 cl::location(EmitMappingInfo),
64 cl::desc("Emit LLVM-to-MachineCode mapping info to assembly"));
66 cl::opt<bool> EnableModSched("enable-modsched",
67 cl::desc("Enable modulo scheduling pass instead of local scheduling"), cl::Hidden);
69 // Register the target.
70 RegisterTarget<SparcV9TargetMachine> X("sparcv9", " SPARC V9");
73 unsigned SparcV9TargetMachine::getJITMatchQuality() {
74 #if defined(__sparcv9)
81 unsigned SparcV9TargetMachine::getModuleMatchQuality(const Module &M) {
82 // We strongly match "sparcv9-*".
83 std::string TT = M.getTargetTriple();
84 if (TT.size() >= 8 && std::string(TT.begin(), TT.begin()+8) == "sparcv9-")
87 if (M.getEndianness() == Module::BigEndian &&
88 M.getPointerSize() == Module::Pointer64)
89 return 10; // Weak match
90 else if (M.getEndianness() != Module::AnyEndianness ||
91 M.getPointerSize() != Module::AnyPointerSize)
92 return 0; // Match for some other target
94 return getJITMatchQuality()/2;
97 //===---------------------------------------------------------------------===//
98 // Code generation/destruction passes
99 //===---------------------------------------------------------------------===//
102 class ConstructMachineFunction : public FunctionPass {
103 TargetMachine &Target;
105 ConstructMachineFunction(TargetMachine &T) : Target(T) {}
107 const char *getPassName() const {
108 return "ConstructMachineFunction";
111 bool runOnFunction(Function &F) {
112 MachineFunction::construct(&F, Target).getInfo<SparcV9FunctionInfo>()->CalculateArgSize();
117 struct DestroyMachineFunction : public FunctionPass {
118 const char *getPassName() const { return "DestroyMachineFunction"; }
120 static void freeMachineCode(Instruction &I) {
121 MachineCodeForInstruction::destroy(&I);
124 bool runOnFunction(Function &F) {
125 for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
126 for (BasicBlock::iterator I = FI->begin(), E = FI->end(); I != E; ++I)
127 MachineCodeForInstruction::get(I).dropAllReferences();
129 for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
130 for_each(FI->begin(), FI->end(), freeMachineCode);
132 MachineFunction::destruct(&F);
137 FunctionPass *createMachineCodeConstructionPass(TargetMachine &Target) {
138 return new ConstructMachineFunction(Target);
142 FunctionPass *llvm::createSparcV9MachineCodeDestructionPass() {
143 return new DestroyMachineFunction();
147 SparcV9TargetMachine::SparcV9TargetMachine(const Module &M,
148 IntrinsicLowering *il)
149 : TargetMachine("UltraSparcV9-Native", il, false),
156 /// addPassesToEmitAssembly - This method controls the entire code generation
157 /// process for the ultra sparc.
160 SparcV9TargetMachine::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out)
162 // FIXME: Implement efficient support for garbage collection intrinsics.
163 PM.add(createLowerGCPass());
165 // Replace malloc and free instructions with library calls.
166 PM.add(createLowerAllocationsPass());
168 // FIXME: implement the switch instruction in the instruction selector.
169 PM.add(createLowerSwitchPass());
171 // FIXME: implement the invoke/unwind instructions!
172 PM.add(createLowerInvokePass());
174 // decompose multi-dimensional array references into single-dim refs
175 PM.add(createDecomposeMultiDimRefsPass());
177 // Lower LLVM code to the form expected by the SPARCv9 instruction selector.
178 PM.add(createPreSelectionPass(*this));
179 PM.add(createLowerSelectPass());
181 // If the user's trying to read the generated code, they'll need to see the
182 // transformed input.
183 if (PrintMachineCode)
184 PM.add(new PrintModulePass());
186 // Construct and initialize the MachineFunction object for this fn.
187 PM.add(createMachineCodeConstructionPass(*this));
189 // Insert empty stackslots in the stack frame of each function
190 // so %fp+offset-8 and %fp+offset-16 are empty slots now!
191 PM.add(createStackSlotsPass(*this));
193 PM.add(createSparcV9BurgInstSelector(*this));
196 PM.add(createMachineFunctionPrinterPass(&std::cerr, "Before modulo scheduling:\n"));
198 //Use ModuloScheduling if enabled, otherwise use local scheduling if not disabled.
200 PM.add(createModuloSchedulingPass(*this));
203 PM.add(createInstructionSchedulingWithSSAPass(*this));
206 if (PrintMachineCode)
207 PM.add(createMachineFunctionPrinterPass(&std::cerr, "Before reg alloc:\n"));
209 PM.add(getRegisterAllocator(*this));
211 if (PrintMachineCode)
212 PM.add(createMachineFunctionPrinterPass(&std::cerr, "After reg alloc:\n"));
214 PM.add(createPrologEpilogInsertionPass());
216 if (!DisablePeephole)
217 PM.add(createPeepholeOptsPass(*this));
219 if (PrintMachineCode)
220 PM.add(createMachineFunctionPrinterPass(&std::cerr, "Final code:\n"));
222 if (EmitMappingInfo) {
223 PM.add(createInternalGlobalMapperPass());
224 PM.add(getMappingInfoAsmPrinterPass(Out));
227 // Output assembly language to the .s file. Assembly emission is split into
228 // two parts: Function output and Global value output. This is because
229 // function output is pipelined with all of the rest of code generation stuff,
230 // allowing machine code representations for functions to be free'd after the
231 // function has been emitted.
232 PM.add(createAsmPrinterPass(Out, *this));
234 // Free machine-code IR which is no longer needed:
235 PM.add(createSparcV9MachineCodeDestructionPass());
237 // Emit bytecode to the assembly file into its special section next
239 PM.add(createBytecodeAsmPrinterPass(Out));
244 /// addPassesToJITCompile - This method controls the JIT method of code
245 /// generation for the UltraSparcV9.
247 void SparcV9JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
248 // FIXME: Implement efficient support for garbage collection intrinsics.
249 PM.add(createLowerGCPass());
251 // Replace malloc and free instructions with library calls.
252 PM.add(createLowerAllocationsPass());
254 // FIXME: implement the switch instruction in the instruction selector.
255 PM.add(createLowerSwitchPass());
257 // FIXME: implement the invoke/unwind instructions!
258 PM.add(createLowerInvokePass());
260 // decompose multi-dimensional array references into single-dim refs
261 PM.add(createDecomposeMultiDimRefsPass());
263 // Lower LLVM code to the form expected by the SPARCv9 instruction selector.
264 PM.add(createPreSelectionPass(TM));
265 PM.add(createLowerSelectPass());
267 // If the user's trying to read the generated code, they'll need to see the
268 // transformed input.
269 if (PrintMachineCode)
270 PM.add(new PrintFunctionPass());
272 // Construct and initialize the MachineFunction object for this fn.
273 PM.add(createMachineCodeConstructionPass(TM));
275 PM.add(createSparcV9BurgInstSelector(TM));
277 if (PrintMachineCode)
278 PM.add(createMachineFunctionPrinterPass(&std::cerr, "Before reg alloc:\n"));
280 PM.add(getRegisterAllocator(TM));
282 if (PrintMachineCode)
283 PM.add(createMachineFunctionPrinterPass(&std::cerr, "After reg alloc:\n"));
285 PM.add(createPrologEpilogInsertionPass());
287 if (!DisablePeephole)
288 PM.add(createPeepholeOptsPass(TM));
290 if (PrintMachineCode)
291 PM.add(createMachineFunctionPrinterPass(&std::cerr, "Final code:\n"));