1 //===-- SparcV9.cpp - General implementation file for the SparcV9 Target ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Primary interface to machine description for the UltraSPARC. Primarily just
11 // initializes machine-dependent parameters in class TargetMachine, and creates
12 // machine-dependent subclasses for classes such as TargetInstrInfo.
14 //===----------------------------------------------------------------------===//
16 #include "llvm/Function.h"
17 #include "llvm/IntrinsicLowering.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Assembly/PrintModulePass.h"
20 #include "llvm/CodeGen/InstrSelection.h"
21 #include "llvm/CodeGen/InstrScheduling.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFunctionInfo.h"
24 #include "llvm/CodeGen/MachineCodeForInstruction.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/Target/TargetMachineImpls.h"
27 #include "llvm/Transforms/Scalar.h"
28 #include "MappingInfo.h"
29 #include "SparcV9Internals.h"
30 #include "SparcV9TargetMachine.h"
31 #include "Support/CommandLine.h"
35 static const unsigned ImplicitRegUseList[] = { 0 }; /* not used yet */
36 // Build the MachineInstruction Description Array...
37 const TargetInstrDescriptor llvm::SparcV9MachineInstrDesc[] = {
38 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
39 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
40 { OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
41 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS, 0, \
42 ImplicitRegUseList, ImplicitRegUseList },
43 #include "SparcV9Instr.def"
46 //---------------------------------------------------------------------------
47 // Command line options to control choice of code generation passes.
48 //---------------------------------------------------------------------------
51 cl::opt<bool> DisableSched("disable-sched",
52 cl::desc("Disable local scheduling pass"));
54 cl::opt<bool> DisablePeephole("disable-peephole",
55 cl::desc("Disable peephole optimization pass"));
57 cl::opt<bool> EmitMappingInfo("enable-maps",
58 cl::desc("Emit LLVM-to-MachineCode mapping info to assembly"));
60 cl::opt<bool> DisableStrip("disable-strip",
61 cl::desc("Do not strip the LLVM bytecode in executable"));
64 //===---------------------------------------------------------------------===//
65 // Code generation/destruction passes
66 //===---------------------------------------------------------------------===//
69 class ConstructMachineFunction : public FunctionPass {
70 TargetMachine &Target;
72 ConstructMachineFunction(TargetMachine &T) : Target(T) {}
74 const char *getPassName() const {
75 return "ConstructMachineFunction";
78 bool runOnFunction(Function &F) {
79 MachineFunction::construct(&F, Target).getInfo()->CalculateArgSize();
84 struct DestroyMachineFunction : public FunctionPass {
85 const char *getPassName() const { return "DestroyMachineFunction"; }
87 static void freeMachineCode(Instruction &I) {
88 MachineCodeForInstruction::destroy(&I);
91 bool runOnFunction(Function &F) {
92 for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
93 for (BasicBlock::iterator I = FI->begin(), E = FI->end(); I != E; ++I)
94 MachineCodeForInstruction::get(I).dropAllReferences();
96 for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
97 for_each(FI->begin(), FI->end(), freeMachineCode);
99 MachineFunction::destruct(&F);
104 FunctionPass *createMachineCodeConstructionPass(TargetMachine &Target) {
105 return new ConstructMachineFunction(Target);
109 FunctionPass *llvm::createSparcV9MachineCodeDestructionPass() {
110 return new DestroyMachineFunction();
114 SparcV9TargetMachine::SparcV9TargetMachine(IntrinsicLowering *il)
115 : TargetMachine("UltraSparcV9-Native", il, false),
122 /// addPassesToEmitAssembly - This method controls the entire code generation
123 /// process for the ultra sparc.
126 SparcV9TargetMachine::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out)
128 // Replace malloc and free instructions with library calls.
129 PM.add(createLowerAllocationsPass());
131 // FIXME: implement the switch instruction in the instruction selector.
132 PM.add(createLowerSwitchPass());
134 // FIXME: implement the invoke/unwind instructions!
135 PM.add(createLowerInvokePass());
137 // decompose multi-dimensional array references into single-dim refs
138 PM.add(createDecomposeMultiDimRefsPass());
140 // Lower LLVM code to the form expected by the SPARCv9 instruction selector.
141 PM.add(createPreSelectionPass(*this));
142 PM.add(createLowerSelectPass());
144 // Run basic LLVM dataflow optimizations, to clean up after pre-selection.
145 PM.add(createReassociatePass());
146 PM.add(createLICMPass());
147 PM.add(createGCSEPass());
149 // Construct and initialize the MachineFunction object for this fn.
150 PM.add(createMachineCodeConstructionPass(*this));
152 // Insert empty stackslots in the stack frame of each function
153 // so %fp+offset-8 and %fp+offset-16 are empty slots now!
154 PM.add(createStackSlotsPass(*this));
156 PM.add(createInstructionSelectionPass(*this));
159 PM.add(createInstructionSchedulingWithSSAPass(*this));
161 if (PrintMachineCode)
162 PM.add(createMachineFunctionPrinterPass(&std::cerr, "Before reg alloc:\n"));
164 PM.add(getRegisterAllocator(*this));
166 if (PrintMachineCode)
167 PM.add(createMachineFunctionPrinterPass(&std::cerr, "After reg alloc:\n"));
169 PM.add(createPrologEpilogInsertionPass());
171 if (!DisablePeephole)
172 PM.add(createPeepholeOptsPass(*this));
175 PM.add(getMappingInfoAsmPrinterPass(Out));
177 // Output assembly language to the .s file. Assembly emission is split into
178 // two parts: Function output and Global value output. This is because
179 // function output is pipelined with all of the rest of code generation stuff,
180 // allowing machine code representations for functions to be free'd after the
181 // function has been emitted.
182 PM.add(createAsmPrinterPass(Out, *this));
184 // Free machine-code IR which is no longer needed:
185 PM.add(createSparcV9MachineCodeDestructionPass());
187 // Emit bytecode to the assembly file into its special section next
188 if (EmitMappingInfo) {
189 // Strip all of the symbols from the bytecode so that it will be smaller...
191 PM.add(createSymbolStrippingPass());
192 PM.add(createBytecodeAsmPrinterPass(Out));
198 /// addPassesToJITCompile - This method controls the JIT method of code
199 /// generation for the UltraSparcV9.
201 void SparcV9JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
202 // Replace malloc and free instructions with library calls.
203 PM.add(createLowerAllocationsPass());
205 // FIXME: implement the switch instruction in the instruction selector.
206 PM.add(createLowerSwitchPass());
208 // FIXME: implement the invoke/unwind instructions!
209 PM.add(createLowerInvokePass());
211 // decompose multi-dimensional array references into single-dim refs
212 PM.add(createDecomposeMultiDimRefsPass());
214 // Lower LLVM code to the form expected by the SPARCv9 instruction selector.
215 PM.add(createPreSelectionPass(TM));
216 PM.add(createLowerSelectPass());
218 // Run basic LLVM dataflow optimizations, to clean up after pre-selection.
219 PM.add(createReassociatePass());
220 // FIXME: these passes crash the FunctionPassManager when being added...
221 //PM.add(createLICMPass());
222 //PM.add(createGCSEPass());
224 // Construct and initialize the MachineFunction object for this fn.
225 PM.add(createMachineCodeConstructionPass(TM));
227 PM.add(createInstructionSelectionPass(TM));
229 if (PrintMachineCode)
230 PM.add(createMachineFunctionPrinterPass(&std::cerr, "Before reg alloc:\n"));
232 PM.add(getRegisterAllocator(TM));
234 if (PrintMachineCode)
235 PM.add(createMachineFunctionPrinterPass(&std::cerr, "After reg alloc:\n"));
237 PM.add(createPrologEpilogInsertionPass());
239 if (!DisablePeephole)
240 PM.add(createPeepholeOptsPass(TM));
243 /// allocateSparcV9TargetMachine - Allocate and return a subclass of TargetMachine
244 /// that implements the SparcV9 backend. (the llvm/CodeGen/SparcV9.h interface)
246 TargetMachine *llvm::allocateSparcV9TargetMachine(const Module &M,
247 IntrinsicLowering *IL) {
248 return new SparcV9TargetMachine(IL);