1 //===-- Sparc.cpp - General implementation file for the Sparc Target ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Primary interface to machine description for the UltraSPARC. Primarily just
11 // initializes machine-dependent parameters in class TargetMachine, and creates
12 // machine-dependent subclasses for classes such as TargetInstrInfo.
14 //===----------------------------------------------------------------------===//
16 #include "llvm/Function.h"
17 #include "llvm/IntrinsicLowering.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Assembly/PrintModulePass.h"
20 #include "llvm/CodeGen/InstrSelection.h"
21 #include "llvm/CodeGen/InstrScheduling.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFunctionInfo.h"
24 #include "llvm/CodeGen/MachineCodeForInstruction.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/Target/TargetMachineImpls.h"
27 #include "llvm/Transforms/Scalar.h"
28 #include "MappingInfo.h"
29 #include "SparcInternals.h"
30 #include "SparcTargetMachine.h"
31 #include "Support/CommandLine.h"
35 static const unsigned ImplicitRegUseList[] = { 0 }; /* not used yet */
36 // Build the MachineInstruction Description Array...
37 const TargetInstrDescriptor llvm::SparcMachineInstrDesc[] = {
38 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
39 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
40 { OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
41 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS, 0, \
42 ImplicitRegUseList, ImplicitRegUseList },
43 #include "SparcInstr.def"
46 //---------------------------------------------------------------------------
47 // Command line options to control choice of code generation passes.
48 //---------------------------------------------------------------------------
51 cl::opt<bool> DisableSched("disable-sched",
52 cl::desc("Disable local scheduling pass"));
54 cl::opt<bool> DisablePeephole("disable-peephole",
55 cl::desc("Disable peephole optimization pass"));
57 cl::opt<bool> EmitMappingInfo("enable-maps",
58 cl::desc("Emit LLVM-to-MachineCode mapping info to assembly"));
60 cl::opt<bool> DisableStrip("disable-strip",
61 cl::desc("Do not strip the LLVM bytecode in executable"));
63 cl::opt<bool> DumpInput("dump-input",
64 cl::desc("Print bytecode before code generation"),
68 //===---------------------------------------------------------------------===//
69 // Code generation/destruction passes
70 //===---------------------------------------------------------------------===//
73 class ConstructMachineFunction : public FunctionPass {
74 TargetMachine &Target;
76 ConstructMachineFunction(TargetMachine &T) : Target(T) {}
78 const char *getPassName() const {
79 return "ConstructMachineFunction";
82 bool runOnFunction(Function &F) {
83 MachineFunction::construct(&F, Target).getInfo()->CalculateArgSize();
88 struct DestroyMachineFunction : public FunctionPass {
89 const char *getPassName() const { return "FreeMachineFunction"; }
91 static void freeMachineCode(Instruction &I) {
92 MachineCodeForInstruction::destroy(&I);
95 bool runOnFunction(Function &F) {
96 for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
97 for (BasicBlock::iterator I = FI->begin(), E = FI->end(); I != E; ++I)
98 MachineCodeForInstruction::get(I).dropAllReferences();
100 for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
101 for_each(FI->begin(), FI->end(), freeMachineCode);
103 MachineFunction::destruct(&F);
108 FunctionPass *createMachineCodeConstructionPass(TargetMachine &Target) {
109 return new ConstructMachineFunction(Target);
113 FunctionPass *llvm::createSparcMachineCodeDestructionPass() {
114 return new DestroyMachineFunction();
118 SparcTargetMachine::SparcTargetMachine(IntrinsicLowering *il)
119 : TargetMachine("UltraSparc-Native", il, false),
127 // addPassesToEmitAssembly - This method controls the entire code generation
128 // process for the ultra sparc.
131 SparcTargetMachine::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out)
133 // The following 3 passes used to be inserted specially by llc.
134 // Replace malloc and free instructions with library calls.
135 PM.add(createLowerAllocationsPass());
137 // Strip all of the symbols from the bytecode so that it will be smaller...
139 PM.add(createSymbolStrippingPass());
141 // FIXME: implement the switch instruction in the instruction selector.
142 PM.add(createLowerSwitchPass());
144 // FIXME: implement the invoke/unwind instructions!
145 PM.add(createLowerInvokePass());
147 // decompose multi-dimensional array references into single-dim refs
148 PM.add(createDecomposeMultiDimRefsPass());
150 // Construct and initialize the MachineFunction object for this fn.
151 PM.add(createMachineCodeConstructionPass(*this));
153 //Insert empty stackslots in the stack frame of each function
154 //so %fp+offset-8 and %fp+offset-16 are empty slots now!
155 PM.add(createStackSlotsPass(*this));
157 // Specialize LLVM code for this target machine
158 PM.add(createPreSelectionPass(*this));
159 // Run basic dataflow optimizations on LLVM code
160 PM.add(createReassociatePass());
161 PM.add(createLICMPass());
162 PM.add(createGCSEPass());
164 // If LLVM dumping after transformations is requested, add it to the pipeline
166 PM.add(new PrintFunctionPass("Input code to instr. selection:\n",
169 PM.add(createInstructionSelectionPass(*this));
172 PM.add(createInstructionSchedulingWithSSAPass(*this));
174 PM.add(getRegisterAllocator(*this));
176 PM.add(createPrologEpilogInsertionPass());
178 if (!DisablePeephole)
179 PM.add(createPeepholeOptsPass(*this));
182 PM.add(getMappingInfoAsmPrinterPass(Out));
184 // Output assembly language to the .s file. Assembly emission is split into
185 // two parts: Function output and Global value output. This is because
186 // function output is pipelined with all of the rest of code generation stuff,
187 // allowing machine code representations for functions to be free'd after the
188 // function has been emitted.
190 PM.add(createAsmPrinterPass(Out, *this));
191 PM.add(createSparcMachineCodeDestructionPass()); // Free mem no longer needed
193 // Emit bytecode to the assembly file into its special section next
195 PM.add(createBytecodeAsmPrinterPass(Out));
200 // addPassesToJITCompile - This method controls the JIT method of code
201 // generation for the UltraSparc.
203 void SparcJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
204 const TargetData &TD = TM.getTargetData();
206 PM.add(new TargetData("lli", TD.isLittleEndian(), TD.getPointerSize(),
207 TD.getPointerAlignment(), TD.getDoubleAlignment()));
209 // Replace malloc and free instructions with library calls.
210 // Do this after tracing until lli implements these lib calls.
211 // For now, it will emulate malloc and free internally.
212 PM.add(createLowerAllocationsPass());
214 // FIXME: implement the switch instruction in the instruction selector.
215 PM.add(createLowerSwitchPass());
217 // FIXME: implement the invoke/unwind instructions!
218 PM.add(createLowerInvokePass());
220 // decompose multi-dimensional array references into single-dim refs
221 PM.add(createDecomposeMultiDimRefsPass());
223 // Construct and initialize the MachineFunction object for this fn.
224 PM.add(createMachineCodeConstructionPass(TM));
226 // Specialize LLVM code for this target machine and then
227 // run basic dataflow optimizations on LLVM code.
228 PM.add(createPreSelectionPass(TM));
229 // Run basic dataflow optimizations on LLVM code
230 PM.add(createReassociatePass());
232 // FIXME: these passes crash the FunctionPassManager when being added...
233 //PM.add(createLICMPass());
234 //PM.add(createGCSEPass());
236 PM.add(createInstructionSelectionPass(TM));
238 PM.add(getRegisterAllocator(TM));
239 PM.add(createPrologEpilogInsertionPass());
241 if (!DisablePeephole)
242 PM.add(createPeepholeOptsPass(TM));
245 //----------------------------------------------------------------------------
246 // allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine
247 // that implements the Sparc backend. (the llvm/CodeGen/Sparc.h interface)
248 //----------------------------------------------------------------------------
250 TargetMachine *llvm::allocateSparcTargetMachine(const Module &M,
251 IntrinsicLowering *IL) {
252 return new SparcTargetMachine(IL);