1 //===- Sparc.td - Target Description for Sparc V9 Target --------*- C++ -*-===//
3 //===----------------------------------------------------------------------===//
5 //===----------------------------------------------------------------------===//
9 // F3 - Common superclass of all F3 instructions. All instructions have an op3
13 set op{1} = 1; // Op = 2 or 3
14 set Inst{24-19} = op3;
17 // F3_rs1 - Common class of instructions that have an rs1 field
20 set Inst{18-14} = rs1;
23 // F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
24 class F3_rs1rs2 : F3_rs1 {
29 // F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
30 class F3_rs1rs2rd : F3_rs1rs2 {
36 // F3_rs1simm13 - Common class of instructions that only have rs1 and simm13
37 class F3_rs1simm13 : F3_rs1 {
39 set Inst{12-0} = simm13;
42 class F3_rs1simm13rd : F3_rs1simm13 {
47 // F3_rs1rd - Common class of instructions that have an rs1 and rd fields
48 class F3_rs1rd : F3_rs1 {
53 // F3_rs2 - Common class of instructions that don't use an rs1
59 // F3_rs2rd - Common class of instructions use rs2 and rd, but not rs1
60 class F3_rs2rd : F3_rs2 {
65 // F3_rd - Common class of instructions that have an rd field
71 // F3_rdrs1 - Common class of instructions that have rd and rs1 fields
72 class F3_rdrs1 : F3_rd {
74 set Inst{18-14} = rs1;
77 // F3_rdrs1simm13 - Common class of instructions that have rd, rs1, and simm13
78 class F3_rdrs1simm13 : F3_rd {
80 set Inst{12-0} = simm13;
84 // F3_rdrs1rs2 - Common class of instructions that have rd, rs1, and rs2 fields
85 class F3_rdrs1rs2 : F3_rs1 {
91 // Specific F3 classes...
94 class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2rd {
98 set Inst{13} = 0; // i field = 0
99 //set Inst{12-5} = dontcare;
102 // The store instructions seem to like to see rd first, then rs1 and rs2
103 class F3_1rd<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1rs2 {
107 set Inst{13} = 0; // i field = 0
108 //set Inst{12-5} = dontcare;
111 class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rs1simm13rd {
115 set Inst{13} = 1; // i field = 1
118 // The store instructions seem to like to see rd first, then rs1 and imm
119 class F3_2rd<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1simm13 {
123 set Inst{13} = 1; // i field = 1
126 class F3_3<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2 {
133 class F3_4<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1simm13 {
138 //set Inst{29-25} = dontcare;
140 set Inst{12-0} = simm;
143 class F3_5<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,
144 string name> : F3_rs1rs2rd {
148 set Inst{13} = 0; // i field = 0
149 set Inst{12-10} = rcondVal; // rcond field
152 class F3_6<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,
153 string name> : F3_rs1 {
160 set Inst{13} = 1; // i field = 1
161 set Inst{12-10} = rcondVal; // rcond field
164 //FIXME: classes 7-10 not defined!!
166 class F3_11<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1rs2rd {
171 set Inst{13} = 0; // i field = 0
173 //set Inst{11-5} = dontcare;
176 class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1 {
183 set Inst{29-25} = rd;
184 set Inst{13} = 1; // i field = 1
185 set Inst{12} = 0; // x field = 0
186 //set Inst{11-5} = dontcare;
187 set Inst{4-0} = shcnt;
190 class F3_13<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1 {
197 set Inst{29-25} = rd;
198 set Inst{13} = 1; // i field = 1
199 set Inst{12} = 1; // x field = 1
200 //set Inst{11-6} = dontcare;
201 set Inst{5-0} = shcnt;
204 class F3_14<bits<2> opVal, bits<6> op3Val,
205 bits<9> opfVal, string name> : F3_rs2rd {
209 //set Inst{18-14} = dontcare;
210 set Inst{13-5} = opfVal;
213 class F3_15<bits<2> opVal, bits<6> op3Val,
214 bits<9> opfVal, string name> : F3 {
221 set Inst{26-25} = cc;
222 set Inst{18-14} = rs1;
223 set Inst{13-5} = opfVal;
227 class F3_16<bits<2> opVal, bits<6> op3Val,
228 bits<9> opfval, string name> : F3_rs1rs2rd {
232 set Inst{13-5} = opfval;
235 class F3_17<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1rd {
239 //Inst{13-0} = dontcare;
242 class F3_18<bits<5> fcn, string name> : F3 {
246 set Inst{29-25} = fcn;
247 //set Inst{18-0 } = dontcare;
250 class F3_19<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
254 //Inst{18-0} = dontcare;
257 // FIXME: class F3_20
258 // FIXME: class F3_21