1 //===- Sparc.td - Target Description for Sparc V9 Target --------*- C++ -*-===//
3 //===----------------------------------------------------------------------===//
5 //===----------------------------------------------------------------------===//
9 // F3 - Common superclass of all F3 instructions. All instructions have an op3
13 set op{1} = 1; // Op = 2 or 3
14 set Inst{24-19} = op3;
17 // F3_rs1 - Common class of instructions that have an rs1 field
20 set Inst{18-14} = rs1;
23 // F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
24 class F3_rs1rs2 : F3_rs1 {
29 // F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
30 class F3_rs1rs2rd : F3_rs1rs2 {
36 // F3_rs1simm13 - Common class of instructions that only have rs1 and simm13
37 class F3_rs1simm13 : F3_rs1 {
39 set Inst{12-0} = simm13;
42 class F3_rs1simm13rd : F3_rs1simm13 {
47 // F3_rs1rd - Common class of instructions that have an rs1 and rd fields
48 class F3_rs1rd : F3_rs1 {
53 // F3_rs2 - Common class of instructions that don't use an rs1
59 // F3_rs2rd - Common class of instructions use rs2 and rd, but not rs1
60 class F3_rs2rd : F3_rs2 {
65 // F3_rd - Common class of instructions that only have an rd field
72 // Specific F3 classes...
75 class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2rd {
79 set Inst{13} = 0; // i field = 0
80 //set Inst{12-5} = dontcare;
83 class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rs1simm13rd {
87 set Inst{13} = 1; // i field = 1
90 class F3_3<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2 {
97 class F3_4<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1simm13 {
102 //set Inst{29-25} = dontcare;
104 set Inst{12-0} = simm;
107 class F3_5<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,
108 string name> : F3_rs1rs2rd {
112 set Inst{13} = 0; // i field = 0
113 set Inst{12-10} = rcondVal; // rcond field
116 class F3_6<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,
117 string name> : F3_rs1 {
124 set Inst{13} = 1; // i field = 1
125 set Inst{12-10} = rcondVal; // rcond field
128 //FIXME: classes 7-10 not defined!!
130 class F3_11<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1rs2rd {
135 set Inst{13} = 0; // i field = 0
137 //set Inst{11-5} = dontcare;
140 class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1 {
147 set Inst{29-25} = rd;
148 set Inst{13} = 1; // i field = 1
149 set Inst{12} = 0; // x field = 0
150 //set Inst{11-5} = dontcare;
151 set Inst{4-0} = shcnt;
154 class F3_13<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1 {
161 set Inst{29-25} = rd;
162 set Inst{13} = 1; // i field = 1
163 set Inst{12} = 1; // x field = 1
164 //set Inst{11-6} = dontcare;
165 set Inst{5-0} = shcnt;
168 class F3_14<bits<2> opVal, bits<6> op3Val,
169 bits<9> opfval, string name> : F3_rs2rd {
173 //set Inst{18-14} = dontcare;
174 set Inst{13-5} = opfval;
177 class F3_16<bits<2> opVal, bits<6> op3Val,
178 bits<9> opfval, string name> : F3_rs1rs2rd {
182 set Inst{13-5} = opfval;
185 class F3_17<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1rd {
189 //Inst{13-0} = dontcare;
192 class F3_18<bits<5> fcn, string name> : F3 {
196 set Inst{29-25} = fcn;
197 //set Inst{18-0 } = dontcare;
200 class F3_19<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
204 //Inst{18-0} = dontcare;
207 // FIXME: class F3_20
208 // FIXME: class F3_21