1 //===- Sparc.td - Target Description for Sparc V9 Target --------*- C++ -*-===//
3 //===----------------------------------------------------------------------===//
5 //===----------------------------------------------------------------------===//
9 // F3 - Common superclass of all F3 instructions. All instructions have an op3
13 set op{1} = 1; // Op = 2 or 3
14 set Inst{24-19} = op3;
22 class F3_rdsimm13 : F3_rd {
24 set Inst{12-0} = simm13;
27 class F3_rdsimm13rs1 : F3_rdsimm13 {
29 set Inst{18-14} = rs1;
32 // F3_rdrs1 - Common superclass of instructions that use rd & rs1
33 class F3_rdrs1 : F3_rd {
35 set Inst{18-14} = rs1;
38 // F3_rs1rdrs2 - Common superclass of instructions with rd, rs1, & rs2 fields
39 class F3_rdrs1rs2 : F3_rdrs1 {
44 // F3_rs1 - Common class of instructions that do not have an rd field,
48 //set Inst{29-25} = dontcare;
49 set Inst{18-14} = rs1;
52 // F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
53 class F3_rs1rs2 : F3_rs1 {
55 //set Inst{12-5} = dontcare;
59 // F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
60 class F3_rs1rs2rd : F3_rs1rs2 {
66 // F3_rs1simm13 - Common class of instructions that only have rs1 and simm13
67 class F3_rs1simm13 : F3_rs1 {
69 set Inst{12-0} = simm13;
72 class F3_rs1simm13rd : F3_rs1simm13 {
77 // F3_rs2 - Common class of instructions that don't use an rs1
83 // F3_rs2rd - Common class of instructions use rs2 and rd, but not rs1
84 class F3_rs2rd : F3_rs2 {
90 // Specific F3 classes...
93 class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2rd {
97 set Inst{13} = 0; // i field = 0
98 //set Inst{12-5} = dontcare;
101 class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rs1simm13rd {
105 set Inst{13} = 1; // i field = 1
109 // The ordering is actually incorrect in these: in the assemble syntax,
111 class F3_1a<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1rs2 {
115 set Inst{13} = 0; // i field = 0
116 //set Inst{12-5} = dontcare;
119 class F3_2a<bits<2> opVal, bits<6> op3val, string name> : F3_rdsimm13rs1 {
123 set Inst{13} = 1; // i field = 1
128 class F3_3<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2 {
135 class F3_4<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1simm13 {
140 //set Inst{29-25} = dontcare;
142 set Inst{12-0} = simm;
145 class F3_11<bits<2> opVal, bits<6> op3Val, string name> : F3_rdrs1rs2 {
150 set Inst{13} = 0; // i field = 0
152 //set Inst{11-5} = dontcare;
155 class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
162 set Inst{18-14} = rs1;
163 set Inst{13} = 1; // i field = 1
164 set Inst{12} = 0; // x field = 0
165 //set Inst{11-5} = dontcare;
166 set Inst{4-0} = shcnt;
169 class F3_13<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1 {
176 set Inst{29-25} = rd;
177 set Inst{13} = 1; // i field = 1
178 set Inst{12} = 1; // x field = 1
179 //set Inst{11-6} = dontcare;
180 set Inst{5-0} = shcnt;
183 class F3_14<bits<2> opVal, bits<6> op3Val,
184 bits<9> opfval, string name> : F3_rs2rd {
188 //set Inst{18-14} = dontcare;
189 set Inst{13-5} = opfval;
192 class F3_16<bits<2> opVal, bits<6> op3Val,
193 bits<9> opfval, string name> : F3_rdrs1rs2 {
197 set Inst{13-5} = opfval;
200 class F3_17<bits<2> opVal, bits<6> op3Val, string name> : F3_rdrs1 {
204 //Inst{13-0} = dontcare;
207 class F3_18<bits<5> fcn, string name> : F3 {
211 set Inst{29-25} = fcn;
212 //set Inst{18-0 } = dontcare;
215 class F3_19<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
219 //Inst{18-0} = dontcare;
222 // FIXME: class F3_20
223 // FIXME: class F3_21