1 //===- Sparc.td - Target Description for Sparc V9 Target --------*- C++ -*-===//
3 //===----------------------------------------------------------------------===//
5 //===----------------------------------------------------------------------===//
9 // F3 - Common superclass of all F3 instructions. All instructions have an op3
13 set op{1} = 1; // Op = 2 or 3
14 set Inst{24-19} = op3;
17 // F3_rs1 - Common class of instructions that have an rs1 field
20 set Inst{18-14} = rs1;
23 // F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
24 class F3_rs1rs2 : F3_rs1 {
29 // F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
30 class F3_rs1rs2rd : F3_rs1rs2 {
35 // F3_rs1simm13 - Common class of instructions that only have rs1 and simm13
36 class F3_rs1simm13 : F3_rs1 {
38 set Inst{12-0} = simm13;
41 class F3_rs1simm13rd : F3_rs1simm13 {
46 // F3_rs1rd - Common class of instructions that have an rs1 and rd fields
47 class F3_rs1rd : F3_rs1 {
52 // F3_rs2 - Common class of instructions that don't use an rs1
58 // F3_rs2rd - Common class of instructions that use rs2 and rd, but not rs1
59 class F3_rs2rd : F3_rs2 {
64 // F3_rd - Common class of instructions that have an rd field
70 // F3_rdrs1 - Common class of instructions that have rd and rs1 fields
71 class F3_rdrs1 : F3_rd {
73 set Inst{18-14} = rs1;
76 // F3_rdrs1simm13 - Common class of instructions that have rd, rs1, and simm13
77 class F3_rdrs1simm13 : F3_rdrs1 {
79 set Inst{12-0} = simm13;
82 // F3_rdrs1rs2 - Common class of instructions that have rd, rs1, and rs2 fields
83 class F3_rdrs1rs2 : F3_rdrs1 {
89 // Specific F3 classes...
92 class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2rd {
96 set Inst{13} = 0; // i field = 0
97 set Inst{12-5} = 0; // don't care
100 // The store instructions seem to like to see rd first, then rs1 and rs2
101 class F3_1rd<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1rs2 {
105 set Inst{13} = 0; // i field = 0
106 set Inst{12-5} = 0; // don't care
109 class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rs1simm13rd {
113 set Inst{13} = 1; // i field = 1
116 // The store instructions seem to like to see rd first, then rs1 and imm
117 class F3_2rd<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1simm13 {
121 set Inst{13} = 1; // i field = 1
124 class F3_3<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2 {
128 set Inst{29-25} = 0; // don't care
129 set Inst{13} = 0; // i field = 0
130 set Inst{12-5} = 0; // don't care
133 class F3_4<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1simm13 {
138 set Inst{29-25} = 0; // don't care
139 set Inst{13} = 1; // i field = 1
140 set Inst{12-0} = simm;
143 class F3_5<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,
144 string name> : F3_rs1rs2rd {
148 set Inst{13} = 0; // i field = 0
149 set Inst{12-10} = rcondVal; // rcond field
150 set Inst{9-5} = 0; // don't care
153 class F3_6<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,
154 string name> : F3_rs1 {
161 set Inst{29-25} = rd;
162 set Inst{13} = 1; // i field = 1
163 set Inst{12-10} = rcondVal; // rcond field
164 set Inst{9-0} = simm10;
167 //FIXME: classes 7-10 not defined!!
169 class F3_11<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1rs2rd {
174 set Inst{13} = 0; // i field = 0
176 set Inst{11-5} = 0; // don't care
179 class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1 {
186 set Inst{29-25} = rd;
187 set Inst{13} = 1; // i field = 1
188 set Inst{12} = 0; // x field = 0
189 set Inst{11-5} = 0; // don't care
190 set Inst{4-0} = shcnt;
193 class F3_13<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1 {
200 set Inst{29-25} = rd;
201 set Inst{13} = 1; // i field = 1
202 set Inst{12} = 1; // x field = 1
203 set Inst{11-6} = 0; // don't care
204 set Inst{5-0} = shcnt;
207 class F3_14<bits<2> opVal, bits<6> op3Val,
208 bits<9> opfVal, string name> : F3_rs2rd {
212 set Inst{18-14} = 0; // don't care
213 set Inst{13-5} = opfVal;
216 class F3_15<bits<2> opVal, bits<6> op3Val,
217 bits<9> opfVal, string name> : F3 {
225 set Inst{29-27} = 0; // defined to be zero
226 set Inst{26-25} = cc;
227 set Inst{18-14} = rs1;
228 set Inst{13-5} = opfVal;
232 class F3_16<bits<2> opVal, bits<6> op3Val,
233 bits<9> opfval, string name> : F3_rs1rs2rd {
237 set Inst{13-5} = opfval;
240 class F3_17<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1rd {
244 set Inst{13-0} = 0; // don't care
247 class F3_18<bits<5> fcn, string name> : F3 {
251 set Inst{29-25} = fcn;
252 set Inst{18-0 } = 0; // don't care;
255 class F3_19<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
259 set Inst{18-0} = 0; // don't care
262 // FIXME: class F3_20
263 // FIXME: class F3_21