1 //===- SparcV9_F3.td - SparcV9 Format 3 Instructions -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
14 // F3 - Common superclass of all F3 instructions. All instructions have an op3
18 let op{1} = 1; // Op = 2 or 3
19 let Inst{24-19} = op3;
22 // F3_rs1 - Common class of instructions that have an rs1 field
25 let Inst{18-14} = rs1;
28 // F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
29 class F3_rs1rs2 : F3_rs1 {
34 // F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
35 class F3_rs1rs2rd : F3_rs1rs2 {
40 // F3_rs1simm13 - Common class of instructions that only have rs1 and simm13
41 class F3_rs1simm13 : F3_rs1 {
43 let Inst{12-0} = simm13;
46 class F3_rs1simm13rd : F3_rs1simm13 {
51 // F3_rs1rd - Common class of instructions that have an rs1 and rd fields
52 class F3_rs1rd : F3_rs1 {
57 // F3_rs2 - Common class of instructions that don't use an rs1
63 // F3_rs2rd - Common class of instructions that use rs2 and rd, but not rs1
64 class F3_rs2rd : F3_rs2 {
69 // F3_rd - Common class of instructions that have an rd field
75 // F3_rdrs1 - Common class of instructions that have rd and rs1 fields
76 class F3_rdrs1 : F3_rd {
78 let Inst{18-14} = rs1;
81 // F3_rdrs1simm13 - Common class of instructions that have rd, rs1, and simm13
82 class F3_rdrs1simm13 : F3_rdrs1 {
84 let Inst{12-0} = simm13;
87 // F3_rdrs1rs2 - Common class of instructions that have rd, rs1, and rs2 fields
88 class F3_rdrs1rs2 : F3_rdrs1 {
94 // Specific F3 classes...
97 class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2rd {
101 let Inst{13} = 0; // i field = 0
102 let Inst{12-5} = 0; // don't care
105 // The store instructions seem to like to see rd first, then rs1 and rs2
106 class F3_1rd<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1rs2 {
110 let Inst{13} = 0; // i field = 0
111 let Inst{12-5} = 0; // don't care
114 class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rs1simm13rd {
118 let Inst{13} = 1; // i field = 1
121 // The store instructions seem to like to see rd first, then rs1 and imm
122 class F3_2rd<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1simm13 {
126 let Inst{13} = 1; // i field = 1
129 class F3_3<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2 {
133 let Inst{29-25} = 0; // don't care
134 let Inst{13} = 0; // i field = 0
135 let Inst{12-5} = 0; // don't care
138 class F3_4<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1simm13 {
142 let Inst{29-25} = 0; // don't care
143 let Inst{13} = 1; // i field = 1
144 let Inst{12-0} = simm13;
147 class F3_5<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,
148 string name> : F3_rs1rs2rd {
152 let Inst{13} = 0; // i field = 0
153 let Inst{12-10} = rcondVal; // rcond field
154 let Inst{9-5} = 0; // don't care
157 class F3_6<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,
158 string name> : F3_rs1 {
165 let Inst{29-25} = rd;
166 let Inst{13} = 1; // i field = 1
167 let Inst{12-10} = rcondVal; // rcond field
168 let Inst{9-0} = simm10;
171 //FIXME: classes 7-10 not defined!!
173 class F3_11<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1rs2rd {
178 let Inst{13} = 0; // i field = 0
180 let Inst{11-5} = 0; // don't care
183 class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1 {
190 let Inst{29-25} = rd;
191 let Inst{13} = 1; // i field = 1
192 let Inst{12} = 0; // x field = 0
193 let Inst{11-5} = 0; // don't care
194 let Inst{4-0} = shcnt;
197 class F3_13<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1 {
204 let Inst{29-25} = rd;
205 let Inst{13} = 1; // i field = 1
206 let Inst{12} = 1; // x field = 1
207 let Inst{11-6} = 0; // don't care
208 let Inst{5-0} = shcnt;
211 class F3_14<bits<2> opVal, bits<6> op3Val,
212 bits<9> opfVal, string name> : F3_rs2rd {
216 let Inst{18-14} = 0; // don't care
217 let Inst{13-5} = opfVal;
220 class F3_15<bits<2> opVal, bits<6> op3Val,
221 bits<9> opfVal, string name> : F3 {
229 let Inst{29-27} = 0; // defined to be zero
230 let Inst{26-25} = cc;
231 let Inst{18-14} = rs1;
232 let Inst{13-5} = opfVal;
236 class F3_16<bits<2> opVal, bits<6> op3Val,
237 bits<9> opfval, string name> : F3_rs1rs2rd {
241 let Inst{13-5} = opfval;
244 class F3_17<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1rd {
248 let Inst{13-0} = 0; // don't care
251 class F3_18<bits<5> fcn, string name> : F3 {
255 let Inst{29-25} = fcn;
256 let Inst{18-0 } = 0; // don't care;
259 class F3_19<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
263 let Inst{18-0} = 0; // don't care
266 // FIXME: class F3_20
267 // FIXME: class F3_21