1 //===- Sparc.td - Target Description for Sparc V9 Target --------*- C++ -*-===//
3 //===----------------------------------------------------------------------===//
5 //===----------------------------------------------------------------------===//
9 // F3 - Common superclass of all F3 instructions. All instructions have an op3
13 set op{1} = 1; // Op = 2 or 3
14 set Inst{24-19} = op3;
22 class F3_rdsimm13 : F3_rd {
24 set Inst{12-0} = simm13;
27 class F3_rdsimm13rs1 : F3_rdsimm13 {
29 set Inst{18-14} = rs1;
32 // F3_rdrs1 - Common superclass of instructions that use rd & rs1
33 class F3_rdrs1 : F3_rd {
35 set Inst{18-14} = rs1;
38 // F3_rs1rdrs2 - Common superclass of instructions with rd, rs1, & rs2 fields
39 class F3_rdrs1rs2 : F3_rdrs1 {
44 // F3_rs1 - Common class of instructions that do not have an rd field,
48 //set Inst{29-25} = dontcare;
49 set Inst{18-14} = rs1;
52 // F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
53 class F3_rs1rs2 : F3_rs1 {
55 //set Inst{12-5} = dontcare;
59 // F3_rs1simm13 - Common class of instructions that only have rs1 and simm13
60 class F3_rs1simm13 : F3_rs1 {
62 set Inst{12-0} = simm13;
66 // Specific F3 classes...
69 class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1rs2 {
73 set Inst{13} = 0; // i field = 0
74 //set Inst{12-5} = dontcare;
77 class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rdsimm13rs1 {
81 set Inst{13} = 1; // i field = 1
84 class F3_3<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2 {
91 class F3_4<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1simm13 {
96 //set Inst{29-25} = dontcare;
98 set Inst{12-0} = simm;
101 class F3_11<bits<2> opVal, bits<6> op3Val, string name> : F3_rdrs1rs2 {
106 set Inst{13} = 0; // i field = 0
108 //set Inst{11-5} = dontcare;
111 class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
118 set Inst{18-14} = rs1;
119 set Inst{13} = 1; // i field = 1
120 set Inst{12} = 0; // x field = 0
121 //set Inst{11-5} = dontcare;
122 set Inst{4-0} = shcnt;
125 class F3_13<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
132 set Inst{18-14} = rs1;
133 set Inst{13} = 1; // i field = 1
134 set Inst{12} = 1; // x field = 1
135 //set Inst{11-6} = dontcare;
136 set Inst{5-0} = shcnt;
139 class F3_14<bits<2> opVal, bits<6> op3Val,
140 bits<9> opfval, string name> : F3_rdrs1rs2 {
144 //set Inst{18-14} = dontcare;
145 set Inst{13-5} = opfval;
148 class F3_16<bits<2> opVal, bits<6> op3Val,
149 bits<9> opfval, string name> : F3_rdrs1rs2 {
153 set Inst{13-5} = opfval;
156 class F3_17<bits<2> opVal, bits<6> op3Val, string name> : F3_rdrs1 {
160 //Inst{13-0} = dontcare;
163 class F3_18<bits<5> fcn, string name> : F3 {
167 set Inst{29-25} = fcn;
168 //set Inst{18-0 } = dontcare;
171 class F3_19<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
175 //Inst{18-0} = dontcare;
178 // FIXME: class F3_20
179 // FIXME: class F3_21