1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "llvm/MC/MCContext.h"
12 #include "llvm/MC/MCExpr.h"
13 #include "llvm/MC/MCInst.h"
14 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCSubtargetInfo.h"
17 #include "llvm/MC/MCTargetAsmParser.h"
18 #include "llvm/Support/TargetRegistry.h"
22 // Return true if Expr is in the range [MinValue, MaxValue].
23 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
24 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) {
25 int64_t Value = CE->getValue();
26 return Value >= MinValue && Value <= MaxValue;
49 class SystemZOperand : public MCParsedAsmOperand {
62 SMLoc StartLoc, EndLoc;
64 // A string of length Length, starting at Data.
70 // LLVM register Num, which has kind Kind. In some ways it might be
71 // easier for this class to have a register bank (general, floating-point
72 // or access) and a raw register number (0-15). This would postpone the
73 // interpretation of the operand to the add*() methods and avoid the need
74 // for context-dependent parsing. However, we do things the current way
75 // because of the virtual getReg() method, which needs to distinguish
76 // between (say) %r0 used as a single register and %r0 used as a pair.
77 // Context-dependent parsing can also give us slightly better error
78 // messages when invalid pairs like %r1 are used.
84 // Base + Disp + Index, where Base and Index are LLVM registers or 0.
85 // RegKind says what type the registers have (ADDR32Reg or ADDR64Reg).
86 // Length is the operand length for D(L,B)-style operands, otherwise
105 SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
106 : Kind(kind), StartLoc(startLoc), EndLoc(endLoc)
109 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
110 // Add as immediates when possible. Null MCExpr = 0.
112 Inst.addOperand(MCOperand::CreateImm(0));
113 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
114 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
116 Inst.addOperand(MCOperand::CreateExpr(Expr));
120 // Create particular kinds of operand.
121 static SystemZOperand *createInvalid(SMLoc StartLoc, SMLoc EndLoc) {
122 return new SystemZOperand(KindInvalid, StartLoc, EndLoc);
124 static SystemZOperand *createToken(StringRef Str, SMLoc Loc) {
125 SystemZOperand *Op = new SystemZOperand(KindToken, Loc, Loc);
126 Op->Token.Data = Str.data();
127 Op->Token.Length = Str.size();
130 static SystemZOperand *createReg(RegisterKind Kind, unsigned Num,
131 SMLoc StartLoc, SMLoc EndLoc) {
132 SystemZOperand *Op = new SystemZOperand(KindReg, StartLoc, EndLoc);
137 static SystemZOperand *createAccessReg(unsigned Num, SMLoc StartLoc,
139 SystemZOperand *Op = new SystemZOperand(KindAccessReg, StartLoc, EndLoc);
143 static SystemZOperand *createImm(const MCExpr *Expr, SMLoc StartLoc,
145 SystemZOperand *Op = new SystemZOperand(KindImm, StartLoc, EndLoc);
149 static SystemZOperand *createMem(RegisterKind RegKind, unsigned Base,
150 const MCExpr *Disp, unsigned Index,
151 const MCExpr *Length, SMLoc StartLoc,
153 SystemZOperand *Op = new SystemZOperand(KindMem, StartLoc, EndLoc);
154 Op->Mem.RegKind = RegKind;
156 Op->Mem.Index = Index;
158 Op->Mem.Length = Length;
163 virtual bool isToken() const LLVM_OVERRIDE {
164 return Kind == KindToken;
166 StringRef getToken() const {
167 assert(Kind == KindToken && "Not a token");
168 return StringRef(Token.Data, Token.Length);
171 // Register operands.
172 virtual bool isReg() const LLVM_OVERRIDE {
173 return Kind == KindReg;
175 bool isReg(RegisterKind RegKind) const {
176 return Kind == KindReg && Reg.Kind == RegKind;
178 virtual unsigned getReg() const LLVM_OVERRIDE {
179 assert(Kind == KindReg && "Not a register");
183 // Access register operands. Access registers aren't exposed to LLVM
185 bool isAccessReg() const {
186 return Kind == KindAccessReg;
189 // Immediate operands.
190 virtual bool isImm() const LLVM_OVERRIDE {
191 return Kind == KindImm;
193 bool isImm(int64_t MinValue, int64_t MaxValue) const {
194 return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
196 const MCExpr *getImm() const {
197 assert(Kind == KindImm && "Not an immediate");
202 virtual bool isMem() const LLVM_OVERRIDE {
203 return Kind == KindMem;
205 bool isMem(RegisterKind RegKind, MemoryKind MemKind) const {
206 return (Kind == KindMem &&
207 Mem.RegKind == RegKind &&
208 (MemKind == BDXMem || !Mem.Index) &&
209 (MemKind == BDLMem) == (Mem.Length != 0));
211 bool isMemDisp12(RegisterKind RegKind, MemoryKind MemKind) const {
212 return isMem(RegKind, MemKind) && inRange(Mem.Disp, 0, 0xfff);
214 bool isMemDisp20(RegisterKind RegKind, MemoryKind MemKind) const {
215 return isMem(RegKind, MemKind) && inRange(Mem.Disp, -524288, 524287);
217 bool isMemDisp12Len8(RegisterKind RegKind) const {
218 return isMemDisp12(RegKind, BDLMem) && inRange(Mem.Length, 1, 0x100);
221 // Override MCParsedAsmOperand.
222 virtual SMLoc getStartLoc() const LLVM_OVERRIDE { return StartLoc; }
223 virtual SMLoc getEndLoc() const LLVM_OVERRIDE { return EndLoc; }
224 virtual void print(raw_ostream &OS) const LLVM_OVERRIDE;
226 // Used by the TableGen code to add particular types of operand
227 // to an instruction.
228 void addRegOperands(MCInst &Inst, unsigned N) const {
229 assert(N == 1 && "Invalid number of operands");
230 Inst.addOperand(MCOperand::CreateReg(getReg()));
232 void addAccessRegOperands(MCInst &Inst, unsigned N) const {
233 assert(N == 1 && "Invalid number of operands");
234 assert(Kind == KindAccessReg && "Invalid operand type");
235 Inst.addOperand(MCOperand::CreateImm(AccessReg));
237 void addImmOperands(MCInst &Inst, unsigned N) const {
238 assert(N == 1 && "Invalid number of operands");
239 addExpr(Inst, getImm());
241 void addBDAddrOperands(MCInst &Inst, unsigned N) const {
242 assert(N == 2 && "Invalid number of operands");
243 assert(Kind == KindMem && Mem.Index == 0 && "Invalid operand type");
244 Inst.addOperand(MCOperand::CreateReg(Mem.Base));
245 addExpr(Inst, Mem.Disp);
247 void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
248 assert(N == 3 && "Invalid number of operands");
249 assert(Kind == KindMem && "Invalid operand type");
250 Inst.addOperand(MCOperand::CreateReg(Mem.Base));
251 addExpr(Inst, Mem.Disp);
252 Inst.addOperand(MCOperand::CreateReg(Mem.Index));
254 void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
255 assert(N == 3 && "Invalid number of operands");
256 assert(Kind == KindMem && "Invalid operand type");
257 Inst.addOperand(MCOperand::CreateReg(Mem.Base));
258 addExpr(Inst, Mem.Disp);
259 addExpr(Inst, Mem.Length);
262 // Used by the TableGen code to check for particular operand types.
263 bool isGR32() const { return isReg(GR32Reg); }
264 bool isGR64() const { return isReg(GR64Reg); }
265 bool isGR128() const { return isReg(GR128Reg); }
266 bool isADDR32() const { return isReg(ADDR32Reg); }
267 bool isADDR64() const { return isReg(ADDR64Reg); }
268 bool isADDR128() const { return false; }
269 bool isFP32() const { return isReg(FP32Reg); }
270 bool isFP64() const { return isReg(FP64Reg); }
271 bool isFP128() const { return isReg(FP128Reg); }
272 bool isBDAddr32Disp12() const { return isMemDisp12(ADDR32Reg, BDMem); }
273 bool isBDAddr32Disp20() const { return isMemDisp20(ADDR32Reg, BDMem); }
274 bool isBDAddr64Disp12() const { return isMemDisp12(ADDR64Reg, BDMem); }
275 bool isBDAddr64Disp20() const { return isMemDisp20(ADDR64Reg, BDMem); }
276 bool isBDXAddr64Disp12() const { return isMemDisp12(ADDR64Reg, BDXMem); }
277 bool isBDXAddr64Disp20() const { return isMemDisp20(ADDR64Reg, BDXMem); }
278 bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
279 bool isU4Imm() const { return isImm(0, 15); }
280 bool isU6Imm() const { return isImm(0, 63); }
281 bool isU8Imm() const { return isImm(0, 255); }
282 bool isS8Imm() const { return isImm(-128, 127); }
283 bool isU16Imm() const { return isImm(0, 65535); }
284 bool isS16Imm() const { return isImm(-32768, 32767); }
285 bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
286 bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
289 class SystemZAsmParser : public MCTargetAsmParser {
290 #define GET_ASSEMBLER_HEADER
291 #include "SystemZGenAsmMatcher.inc"
294 MCSubtargetInfo &STI;
304 SMLoc StartLoc, EndLoc;
307 bool parseRegister(Register &Reg);
309 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
310 bool IsAddress = false);
313 parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
314 RegisterGroup Group, const unsigned *Regs, RegisterKind Kind);
316 bool parseAddress(unsigned &Base, const MCExpr *&Disp,
317 unsigned &Index, const MCExpr *&Length,
318 const unsigned *Regs, RegisterKind RegKind);
321 parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
322 const unsigned *Regs, RegisterKind RegKind,
325 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
329 SystemZAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
330 : MCTargetAsmParser(), STI(sti), Parser(parser) {
331 MCAsmParserExtension::Initialize(Parser);
333 // Initialize the set of available features.
334 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
337 // Override MCTargetAsmParser.
338 virtual bool ParseDirective(AsmToken DirectiveID) LLVM_OVERRIDE;
339 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
340 SMLoc &EndLoc) LLVM_OVERRIDE;
341 virtual bool ParseInstruction(ParseInstructionInfo &Info,
342 StringRef Name, SMLoc NameLoc,
343 SmallVectorImpl<MCParsedAsmOperand*> &Operands)
346 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
347 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
348 MCStreamer &Out, unsigned &ErrorInfo,
349 bool MatchingInlineAsm) LLVM_OVERRIDE;
351 // Used by the TableGen code to parse particular operand types.
353 parseGR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
354 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
357 parseGR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
358 return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
361 parseGR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
362 return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
365 parseADDR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
366 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
369 parseADDR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
370 return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
373 parseADDR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
374 llvm_unreachable("Shouldn't be used as an operand");
377 parseFP32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
378 return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
381 parseFP64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
382 return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
385 parseFP128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
386 return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
389 parseBDAddr32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
390 return parseAddress(Operands, SystemZMC::GR32Regs, ADDR32Reg, BDMem);
393 parseBDAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
394 return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDMem);
397 parseBDXAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
398 return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDXMem);
401 parseBDLAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
402 return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDLMem);
405 parseAccessReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
407 parsePCRel(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
408 int64_t MinVal, int64_t MaxVal);
410 parsePCRel16(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
411 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1);
414 parsePCRel32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
415 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1);
420 #define GET_REGISTER_MATCHER
421 #define GET_SUBTARGET_FEATURE_NAME
422 #define GET_MATCHER_IMPLEMENTATION
423 #include "SystemZGenAsmMatcher.inc"
425 void SystemZOperand::print(raw_ostream &OS) const {
426 llvm_unreachable("Not implemented");
429 // Parse one register of the form %<prefix><number>.
430 bool SystemZAsmParser::parseRegister(Register &Reg) {
431 Reg.StartLoc = Parser.getTok().getLoc();
434 if (Parser.getTok().isNot(AsmToken::Percent))
435 return Error(Parser.getTok().getLoc(), "register expected");
438 // Expect a register name.
439 if (Parser.getTok().isNot(AsmToken::Identifier))
440 return Error(Reg.StartLoc, "invalid register");
442 // Check that there's a prefix.
443 StringRef Name = Parser.getTok().getString();
445 return Error(Reg.StartLoc, "invalid register");
446 char Prefix = Name[0];
448 // Treat the rest of the register name as a register number.
449 if (Name.substr(1).getAsInteger(10, Reg.Num))
450 return Error(Reg.StartLoc, "invalid register");
452 // Look for valid combinations of prefix and number.
453 if (Prefix == 'r' && Reg.Num < 16)
455 else if (Prefix == 'f' && Reg.Num < 16)
457 else if (Prefix == 'a' && Reg.Num < 16)
458 Reg.Group = RegAccess;
460 return Error(Reg.StartLoc, "invalid register");
462 Reg.EndLoc = Parser.getTok().getLoc();
467 // Parse a register of group Group. If Regs is nonnull, use it to map
468 // the raw register number to LLVM numbering, with zero entries indicating
469 // an invalid register. IsAddress says whether the register appears in an
471 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
472 const unsigned *Regs, bool IsAddress) {
473 if (parseRegister(Reg))
475 if (Reg.Group != Group)
476 return Error(Reg.StartLoc, "invalid operand for instruction");
477 if (Regs && Regs[Reg.Num] == 0)
478 return Error(Reg.StartLoc, "invalid register pair");
479 if (Reg.Num == 0 && IsAddress)
480 return Error(Reg.StartLoc, "%r0 used in an address");
482 Reg.Num = Regs[Reg.Num];
486 // Parse a register and add it to Operands. The other arguments are as above.
487 SystemZAsmParser::OperandMatchResultTy
488 SystemZAsmParser::parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
489 RegisterGroup Group, const unsigned *Regs,
491 if (Parser.getTok().isNot(AsmToken::Percent))
492 return MatchOperand_NoMatch;
495 bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
496 if (parseRegister(Reg, Group, Regs, IsAddress))
497 return MatchOperand_ParseFail;
499 Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
500 Reg.StartLoc, Reg.EndLoc));
501 return MatchOperand_Success;
504 // Parse a memory operand into Base, Disp, Index and Length.
505 // Regs maps asm register numbers to LLVM register numbers and RegKind
506 // says what kind of address register we're using (ADDR32Reg or ADDR64Reg).
507 bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp,
508 unsigned &Index, const MCExpr *&Length,
509 const unsigned *Regs,
510 RegisterKind RegKind) {
511 // Parse the displacement, which must always be present.
512 if (getParser().parseExpression(Disp))
515 // Parse the optional base and index.
519 if (getLexer().is(AsmToken::LParen)) {
522 if (getLexer().is(AsmToken::Percent)) {
523 // Parse the first register and decide whether it's a base or an index.
525 if (parseRegister(Reg, RegGR, Regs, RegKind))
527 if (getLexer().is(AsmToken::Comma))
533 if (getParser().parseExpression(Length))
537 // Check whether there's a second register. It's the base if so.
538 if (getLexer().is(AsmToken::Comma)) {
541 if (parseRegister(Reg, RegGR, Regs, RegKind))
546 // Consume the closing bracket.
547 if (getLexer().isNot(AsmToken::RParen))
548 return Error(Parser.getTok().getLoc(), "unexpected token in address");
554 // Parse a memory operand and add it to Operands. The other arguments
556 SystemZAsmParser::OperandMatchResultTy
557 SystemZAsmParser::parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
558 const unsigned *Regs, RegisterKind RegKind,
559 MemoryKind MemKind) {
560 SMLoc StartLoc = Parser.getTok().getLoc();
561 unsigned Base, Index;
563 const MCExpr *Length;
564 if (parseAddress(Base, Disp, Index, Length, Regs, RegKind))
565 return MatchOperand_ParseFail;
567 if (Index && MemKind != BDXMem)
569 Error(StartLoc, "invalid use of indexed addressing");
570 return MatchOperand_ParseFail;
573 if (Length && MemKind != BDLMem)
575 Error(StartLoc, "invalid use of length addressing");
576 return MatchOperand_ParseFail;
579 if (!Length && MemKind == BDLMem)
581 Error(StartLoc, "missing length in address");
582 return MatchOperand_ParseFail;
586 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
587 Operands.push_back(SystemZOperand::createMem(RegKind, Base, Disp, Index,
588 Length, StartLoc, EndLoc));
589 return MatchOperand_Success;
592 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
596 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
599 if (parseRegister(Reg))
601 if (Reg.Group == RegGR)
602 RegNo = SystemZMC::GR64Regs[Reg.Num];
603 else if (Reg.Group == RegFP)
604 RegNo = SystemZMC::FP64Regs[Reg.Num];
606 // FIXME: Access registers aren't modelled as LLVM registers yet.
607 return Error(Reg.StartLoc, "invalid operand for instruction");
608 StartLoc = Reg.StartLoc;
613 bool SystemZAsmParser::
614 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
615 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
616 Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
618 // Read the remaining operands.
619 if (getLexer().isNot(AsmToken::EndOfStatement)) {
620 // Read the first operand.
621 if (parseOperand(Operands, Name)) {
622 Parser.eatToEndOfStatement();
626 // Read any subsequent operands.
627 while (getLexer().is(AsmToken::Comma)) {
629 if (parseOperand(Operands, Name)) {
630 Parser.eatToEndOfStatement();
634 if (getLexer().isNot(AsmToken::EndOfStatement)) {
635 SMLoc Loc = getLexer().getLoc();
636 Parser.eatToEndOfStatement();
637 return Error(Loc, "unexpected token in argument list");
641 // Consume the EndOfStatement.
646 bool SystemZAsmParser::
647 parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
648 StringRef Mnemonic) {
649 // Check if the current operand has a custom associated parser, if so, try to
650 // custom parse the operand, or fallback to the general approach.
651 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
652 if (ResTy == MatchOperand_Success)
655 // If there wasn't a custom match, try the generic matcher below. Otherwise,
656 // there was a match, but an error occurred, in which case, just return that
657 // the operand parsing failed.
658 if (ResTy == MatchOperand_ParseFail)
661 // Check for a register. All real register operands should have used
662 // a context-dependent parse routine, which gives the required register
663 // class. The code is here to mop up other cases, like those where
664 // the instruction isn't recognized.
665 if (Parser.getTok().is(AsmToken::Percent)) {
667 if (parseRegister(Reg))
669 Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
673 // The only other type of operand is an immediate or address. As above,
674 // real address operands should have used a context-dependent parse routine,
675 // so we treat any plain expression as an immediate.
676 SMLoc StartLoc = Parser.getTok().getLoc();
677 unsigned Base, Index;
678 const MCExpr *Expr, *Length;
679 if (parseAddress(Base, Expr, Index, Length, SystemZMC::GR64Regs, ADDR64Reg))
683 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
684 if (Base || Index || Length)
685 Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
687 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
691 bool SystemZAsmParser::
692 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
693 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
694 MCStreamer &Out, unsigned &ErrorInfo,
695 bool MatchingInlineAsm) {
697 unsigned MatchResult;
699 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
701 switch (MatchResult) {
705 Out.EmitInstruction(Inst);
708 case Match_MissingFeature: {
709 assert(ErrorInfo && "Unknown missing feature!");
710 // Special case the error message for the very common case where only
711 // a single subtarget feature is missing
712 std::string Msg = "instruction requires:";
714 for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
715 if (ErrorInfo & Mask) {
717 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
721 return Error(IDLoc, Msg);
724 case Match_InvalidOperand: {
725 SMLoc ErrorLoc = IDLoc;
726 if (ErrorInfo != ~0U) {
727 if (ErrorInfo >= Operands.size())
728 return Error(IDLoc, "too few operands for instruction");
730 ErrorLoc = ((SystemZOperand*)Operands[ErrorInfo])->getStartLoc();
731 if (ErrorLoc == SMLoc())
734 return Error(ErrorLoc, "invalid operand for instruction");
737 case Match_MnemonicFail:
738 return Error(IDLoc, "invalid instruction");
741 llvm_unreachable("Unexpected match type");
744 SystemZAsmParser::OperandMatchResultTy SystemZAsmParser::
745 parseAccessReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
746 if (Parser.getTok().isNot(AsmToken::Percent))
747 return MatchOperand_NoMatch;
750 if (parseRegister(Reg, RegAccess, 0))
751 return MatchOperand_ParseFail;
753 Operands.push_back(SystemZOperand::createAccessReg(Reg.Num,
756 return MatchOperand_Success;
759 SystemZAsmParser::OperandMatchResultTy SystemZAsmParser::
760 parsePCRel(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
761 int64_t MinVal, int64_t MaxVal) {
762 MCContext &Ctx = getContext();
763 MCStreamer &Out = getStreamer();
765 SMLoc StartLoc = Parser.getTok().getLoc();
766 if (getParser().parseExpression(Expr))
767 return MatchOperand_NoMatch;
769 // For consistency with the GNU assembler, treat immediates as offsets
771 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) {
772 int64_t Value = CE->getValue();
773 if ((Value & 1) || Value < MinVal || Value > MaxVal) {
774 Error(StartLoc, "offset out of range");
775 return MatchOperand_ParseFail;
777 MCSymbol *Sym = Ctx.CreateTempSymbol();
779 const MCExpr *Base = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
781 Expr = Value == 0 ? Base : MCBinaryExpr::CreateAdd(Base, Expr, Ctx);
785 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
786 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
787 return MatchOperand_Success;
790 // Force static initialization.
791 extern "C" void LLVMInitializeSystemZAsmParser() {
792 RegisterMCAsmParser<SystemZAsmParser> X(TheSystemZTarget);