1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "llvm/ADT/STLExtras.h"
12 #include "llvm/MC/MCContext.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCStreamer.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCTargetAsmParser.h"
19 #include "llvm/Support/TargetRegistry.h"
23 // Return true if Expr is in the range [MinValue, MaxValue].
24 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
25 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) {
26 int64_t Value = CE->getValue();
27 return Value >= MinValue && Value <= MaxValue;
50 class SystemZOperand : public MCParsedAsmOperand {
63 SMLoc StartLoc, EndLoc;
65 // A string of length Length, starting at Data.
71 // LLVM register Num, which has kind Kind. In some ways it might be
72 // easier for this class to have a register bank (general, floating-point
73 // or access) and a raw register number (0-15). This would postpone the
74 // interpretation of the operand to the add*() methods and avoid the need
75 // for context-dependent parsing. However, we do things the current way
76 // because of the virtual getReg() method, which needs to distinguish
77 // between (say) %r0 used as a single register and %r0 used as a pair.
78 // Context-dependent parsing can also give us slightly better error
79 // messages when invalid pairs like %r1 are used.
85 // Base + Disp + Index, where Base and Index are LLVM registers or 0.
86 // RegKind says what type the registers have (ADDR32Reg or ADDR64Reg).
87 // Length is the operand length for D(L,B)-style operands, otherwise
106 SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
107 : Kind(kind), StartLoc(startLoc), EndLoc(endLoc)
110 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
111 // Add as immediates when possible. Null MCExpr = 0.
113 Inst.addOperand(MCOperand::CreateImm(0));
114 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
115 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
117 Inst.addOperand(MCOperand::CreateExpr(Expr));
121 // Create particular kinds of operand.
122 static SystemZOperand *createInvalid(SMLoc StartLoc, SMLoc EndLoc) {
123 return new SystemZOperand(KindInvalid, StartLoc, EndLoc);
125 static SystemZOperand *createToken(StringRef Str, SMLoc Loc) {
126 SystemZOperand *Op = new SystemZOperand(KindToken, Loc, Loc);
127 Op->Token.Data = Str.data();
128 Op->Token.Length = Str.size();
131 static SystemZOperand *createReg(RegisterKind Kind, unsigned Num,
132 SMLoc StartLoc, SMLoc EndLoc) {
133 SystemZOperand *Op = new SystemZOperand(KindReg, StartLoc, EndLoc);
138 static SystemZOperand *createAccessReg(unsigned Num, SMLoc StartLoc,
140 SystemZOperand *Op = new SystemZOperand(KindAccessReg, StartLoc, EndLoc);
144 static SystemZOperand *createImm(const MCExpr *Expr, SMLoc StartLoc,
146 SystemZOperand *Op = new SystemZOperand(KindImm, StartLoc, EndLoc);
150 static SystemZOperand *createMem(RegisterKind RegKind, unsigned Base,
151 const MCExpr *Disp, unsigned Index,
152 const MCExpr *Length, SMLoc StartLoc,
154 SystemZOperand *Op = new SystemZOperand(KindMem, StartLoc, EndLoc);
155 Op->Mem.RegKind = RegKind;
157 Op->Mem.Index = Index;
159 Op->Mem.Length = Length;
164 virtual bool isToken() const LLVM_OVERRIDE {
165 return Kind == KindToken;
167 StringRef getToken() const {
168 assert(Kind == KindToken && "Not a token");
169 return StringRef(Token.Data, Token.Length);
172 // Register operands.
173 virtual bool isReg() const LLVM_OVERRIDE {
174 return Kind == KindReg;
176 bool isReg(RegisterKind RegKind) const {
177 return Kind == KindReg && Reg.Kind == RegKind;
179 virtual unsigned getReg() const LLVM_OVERRIDE {
180 assert(Kind == KindReg && "Not a register");
184 // Access register operands. Access registers aren't exposed to LLVM
186 bool isAccessReg() const {
187 return Kind == KindAccessReg;
190 // Immediate operands.
191 virtual bool isImm() const LLVM_OVERRIDE {
192 return Kind == KindImm;
194 bool isImm(int64_t MinValue, int64_t MaxValue) const {
195 return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
197 const MCExpr *getImm() const {
198 assert(Kind == KindImm && "Not an immediate");
203 virtual bool isMem() const LLVM_OVERRIDE {
204 return Kind == KindMem;
206 bool isMem(RegisterKind RegKind, MemoryKind MemKind) const {
207 return (Kind == KindMem &&
208 Mem.RegKind == RegKind &&
209 (MemKind == BDXMem || !Mem.Index) &&
210 (MemKind == BDLMem) == (Mem.Length != 0));
212 bool isMemDisp12(RegisterKind RegKind, MemoryKind MemKind) const {
213 return isMem(RegKind, MemKind) && inRange(Mem.Disp, 0, 0xfff);
215 bool isMemDisp20(RegisterKind RegKind, MemoryKind MemKind) const {
216 return isMem(RegKind, MemKind) && inRange(Mem.Disp, -524288, 524287);
218 bool isMemDisp12Len8(RegisterKind RegKind) const {
219 return isMemDisp12(RegKind, BDLMem) && inRange(Mem.Length, 1, 0x100);
222 // Override MCParsedAsmOperand.
223 virtual SMLoc getStartLoc() const LLVM_OVERRIDE { return StartLoc; }
224 virtual SMLoc getEndLoc() const LLVM_OVERRIDE { return EndLoc; }
225 virtual void print(raw_ostream &OS) const LLVM_OVERRIDE;
227 // Used by the TableGen code to add particular types of operand
228 // to an instruction.
229 void addRegOperands(MCInst &Inst, unsigned N) const {
230 assert(N == 1 && "Invalid number of operands");
231 Inst.addOperand(MCOperand::CreateReg(getReg()));
233 void addAccessRegOperands(MCInst &Inst, unsigned N) const {
234 assert(N == 1 && "Invalid number of operands");
235 assert(Kind == KindAccessReg && "Invalid operand type");
236 Inst.addOperand(MCOperand::CreateImm(AccessReg));
238 void addImmOperands(MCInst &Inst, unsigned N) const {
239 assert(N == 1 && "Invalid number of operands");
240 addExpr(Inst, getImm());
242 void addBDAddrOperands(MCInst &Inst, unsigned N) const {
243 assert(N == 2 && "Invalid number of operands");
244 assert(Kind == KindMem && Mem.Index == 0 && "Invalid operand type");
245 Inst.addOperand(MCOperand::CreateReg(Mem.Base));
246 addExpr(Inst, Mem.Disp);
248 void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
249 assert(N == 3 && "Invalid number of operands");
250 assert(Kind == KindMem && "Invalid operand type");
251 Inst.addOperand(MCOperand::CreateReg(Mem.Base));
252 addExpr(Inst, Mem.Disp);
253 Inst.addOperand(MCOperand::CreateReg(Mem.Index));
255 void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
256 assert(N == 3 && "Invalid number of operands");
257 assert(Kind == KindMem && "Invalid operand type");
258 Inst.addOperand(MCOperand::CreateReg(Mem.Base));
259 addExpr(Inst, Mem.Disp);
260 addExpr(Inst, Mem.Length);
263 // Used by the TableGen code to check for particular operand types.
264 bool isGR32() const { return isReg(GR32Reg); }
265 bool isGR64() const { return isReg(GR64Reg); }
266 bool isGR128() const { return isReg(GR128Reg); }
267 bool isADDR32() const { return isReg(ADDR32Reg); }
268 bool isADDR64() const { return isReg(ADDR64Reg); }
269 bool isADDR128() const { return false; }
270 bool isFP32() const { return isReg(FP32Reg); }
271 bool isFP64() const { return isReg(FP64Reg); }
272 bool isFP128() const { return isReg(FP128Reg); }
273 bool isBDAddr32Disp12() const { return isMemDisp12(ADDR32Reg, BDMem); }
274 bool isBDAddr32Disp20() const { return isMemDisp20(ADDR32Reg, BDMem); }
275 bool isBDAddr64Disp12() const { return isMemDisp12(ADDR64Reg, BDMem); }
276 bool isBDAddr64Disp20() const { return isMemDisp20(ADDR64Reg, BDMem); }
277 bool isBDXAddr64Disp12() const { return isMemDisp12(ADDR64Reg, BDXMem); }
278 bool isBDXAddr64Disp20() const { return isMemDisp20(ADDR64Reg, BDXMem); }
279 bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
280 bool isU4Imm() const { return isImm(0, 15); }
281 bool isU6Imm() const { return isImm(0, 63); }
282 bool isU8Imm() const { return isImm(0, 255); }
283 bool isS8Imm() const { return isImm(-128, 127); }
284 bool isU16Imm() const { return isImm(0, 65535); }
285 bool isS16Imm() const { return isImm(-32768, 32767); }
286 bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
287 bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
290 class SystemZAsmParser : public MCTargetAsmParser {
291 #define GET_ASSEMBLER_HEADER
292 #include "SystemZGenAsmMatcher.inc"
295 MCSubtargetInfo &STI;
305 SMLoc StartLoc, EndLoc;
308 bool parseRegister(Register &Reg);
310 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
311 bool IsAddress = false);
314 parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
315 RegisterGroup Group, const unsigned *Regs, RegisterKind Kind);
317 bool parseAddress(unsigned &Base, const MCExpr *&Disp,
318 unsigned &Index, const MCExpr *&Length,
319 const unsigned *Regs, RegisterKind RegKind);
322 parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
323 const unsigned *Regs, RegisterKind RegKind,
326 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
330 SystemZAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
331 : MCTargetAsmParser(), STI(sti), Parser(parser) {
332 MCAsmParserExtension::Initialize(Parser);
334 // Initialize the set of available features.
335 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
338 // Override MCTargetAsmParser.
339 virtual bool ParseDirective(AsmToken DirectiveID) LLVM_OVERRIDE;
340 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
341 SMLoc &EndLoc) LLVM_OVERRIDE;
342 virtual bool ParseInstruction(ParseInstructionInfo &Info,
343 StringRef Name, SMLoc NameLoc,
344 SmallVectorImpl<MCParsedAsmOperand*> &Operands)
347 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
348 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
349 MCStreamer &Out, unsigned &ErrorInfo,
350 bool MatchingInlineAsm) LLVM_OVERRIDE;
352 // Used by the TableGen code to parse particular operand types.
354 parseGR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
355 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
358 parseGR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
359 return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
362 parseGR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
363 return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
366 parseADDR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
367 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
370 parseADDR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
371 return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
374 parseADDR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
375 llvm_unreachable("Shouldn't be used as an operand");
378 parseFP32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
379 return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
382 parseFP64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
383 return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
386 parseFP128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
387 return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
390 parseBDAddr32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
391 return parseAddress(Operands, SystemZMC::GR32Regs, ADDR32Reg, BDMem);
394 parseBDAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
395 return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDMem);
398 parseBDXAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
399 return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDXMem);
402 parseBDLAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
403 return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDLMem);
406 parseAccessReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
408 parsePCRel(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
409 int64_t MinVal, int64_t MaxVal);
411 parsePCRel16(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
412 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1);
415 parsePCRel32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
416 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1);
421 #define GET_REGISTER_MATCHER
422 #define GET_SUBTARGET_FEATURE_NAME
423 #define GET_MATCHER_IMPLEMENTATION
424 #include "SystemZGenAsmMatcher.inc"
426 void SystemZOperand::print(raw_ostream &OS) const {
427 llvm_unreachable("Not implemented");
430 // Parse one register of the form %<prefix><number>.
431 bool SystemZAsmParser::parseRegister(Register &Reg) {
432 Reg.StartLoc = Parser.getTok().getLoc();
435 if (Parser.getTok().isNot(AsmToken::Percent))
436 return Error(Parser.getTok().getLoc(), "register expected");
439 // Expect a register name.
440 if (Parser.getTok().isNot(AsmToken::Identifier))
441 return Error(Reg.StartLoc, "invalid register");
443 // Check that there's a prefix.
444 StringRef Name = Parser.getTok().getString();
446 return Error(Reg.StartLoc, "invalid register");
447 char Prefix = Name[0];
449 // Treat the rest of the register name as a register number.
450 if (Name.substr(1).getAsInteger(10, Reg.Num))
451 return Error(Reg.StartLoc, "invalid register");
453 // Look for valid combinations of prefix and number.
454 if (Prefix == 'r' && Reg.Num < 16)
456 else if (Prefix == 'f' && Reg.Num < 16)
458 else if (Prefix == 'a' && Reg.Num < 16)
459 Reg.Group = RegAccess;
461 return Error(Reg.StartLoc, "invalid register");
463 Reg.EndLoc = Parser.getTok().getLoc();
468 // Parse a register of group Group. If Regs is nonnull, use it to map
469 // the raw register number to LLVM numbering, with zero entries indicating
470 // an invalid register. IsAddress says whether the register appears in an
472 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
473 const unsigned *Regs, bool IsAddress) {
474 if (parseRegister(Reg))
476 if (Reg.Group != Group)
477 return Error(Reg.StartLoc, "invalid operand for instruction");
478 if (Regs && Regs[Reg.Num] == 0)
479 return Error(Reg.StartLoc, "invalid register pair");
480 if (Reg.Num == 0 && IsAddress)
481 return Error(Reg.StartLoc, "%r0 used in an address");
483 Reg.Num = Regs[Reg.Num];
487 // Parse a register and add it to Operands. The other arguments are as above.
488 SystemZAsmParser::OperandMatchResultTy
489 SystemZAsmParser::parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
490 RegisterGroup Group, const unsigned *Regs,
492 if (Parser.getTok().isNot(AsmToken::Percent))
493 return MatchOperand_NoMatch;
496 bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
497 if (parseRegister(Reg, Group, Regs, IsAddress))
498 return MatchOperand_ParseFail;
500 Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
501 Reg.StartLoc, Reg.EndLoc));
502 return MatchOperand_Success;
505 // Parse a memory operand into Base, Disp, Index and Length.
506 // Regs maps asm register numbers to LLVM register numbers and RegKind
507 // says what kind of address register we're using (ADDR32Reg or ADDR64Reg).
508 bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp,
509 unsigned &Index, const MCExpr *&Length,
510 const unsigned *Regs,
511 RegisterKind RegKind) {
512 // Parse the displacement, which must always be present.
513 if (getParser().parseExpression(Disp))
516 // Parse the optional base and index.
520 if (getLexer().is(AsmToken::LParen)) {
523 if (getLexer().is(AsmToken::Percent)) {
524 // Parse the first register and decide whether it's a base or an index.
526 if (parseRegister(Reg, RegGR, Regs, RegKind))
528 if (getLexer().is(AsmToken::Comma))
534 if (getParser().parseExpression(Length))
538 // Check whether there's a second register. It's the base if so.
539 if (getLexer().is(AsmToken::Comma)) {
542 if (parseRegister(Reg, RegGR, Regs, RegKind))
547 // Consume the closing bracket.
548 if (getLexer().isNot(AsmToken::RParen))
549 return Error(Parser.getTok().getLoc(), "unexpected token in address");
555 // Parse a memory operand and add it to Operands. The other arguments
557 SystemZAsmParser::OperandMatchResultTy
558 SystemZAsmParser::parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
559 const unsigned *Regs, RegisterKind RegKind,
560 MemoryKind MemKind) {
561 SMLoc StartLoc = Parser.getTok().getLoc();
562 unsigned Base, Index;
564 const MCExpr *Length;
565 if (parseAddress(Base, Disp, Index, Length, Regs, RegKind))
566 return MatchOperand_ParseFail;
568 if (Index && MemKind != BDXMem)
570 Error(StartLoc, "invalid use of indexed addressing");
571 return MatchOperand_ParseFail;
574 if (Length && MemKind != BDLMem)
576 Error(StartLoc, "invalid use of length addressing");
577 return MatchOperand_ParseFail;
580 if (!Length && MemKind == BDLMem)
582 Error(StartLoc, "missing length in address");
583 return MatchOperand_ParseFail;
587 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
588 Operands.push_back(SystemZOperand::createMem(RegKind, Base, Disp, Index,
589 Length, StartLoc, EndLoc));
590 return MatchOperand_Success;
593 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
597 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
600 if (parseRegister(Reg))
602 if (Reg.Group == RegGR)
603 RegNo = SystemZMC::GR64Regs[Reg.Num];
604 else if (Reg.Group == RegFP)
605 RegNo = SystemZMC::FP64Regs[Reg.Num];
607 // FIXME: Access registers aren't modelled as LLVM registers yet.
608 return Error(Reg.StartLoc, "invalid operand for instruction");
609 StartLoc = Reg.StartLoc;
614 bool SystemZAsmParser::
615 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
616 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
617 Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
619 // Read the remaining operands.
620 if (getLexer().isNot(AsmToken::EndOfStatement)) {
621 // Read the first operand.
622 if (parseOperand(Operands, Name)) {
623 Parser.eatToEndOfStatement();
627 // Read any subsequent operands.
628 while (getLexer().is(AsmToken::Comma)) {
630 if (parseOperand(Operands, Name)) {
631 Parser.eatToEndOfStatement();
635 if (getLexer().isNot(AsmToken::EndOfStatement)) {
636 SMLoc Loc = getLexer().getLoc();
637 Parser.eatToEndOfStatement();
638 return Error(Loc, "unexpected token in argument list");
642 // Consume the EndOfStatement.
647 bool SystemZAsmParser::
648 parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
649 StringRef Mnemonic) {
650 // Check if the current operand has a custom associated parser, if so, try to
651 // custom parse the operand, or fallback to the general approach.
652 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
653 if (ResTy == MatchOperand_Success)
656 // If there wasn't a custom match, try the generic matcher below. Otherwise,
657 // there was a match, but an error occurred, in which case, just return that
658 // the operand parsing failed.
659 if (ResTy == MatchOperand_ParseFail)
662 // Check for a register. All real register operands should have used
663 // a context-dependent parse routine, which gives the required register
664 // class. The code is here to mop up other cases, like those where
665 // the instruction isn't recognized.
666 if (Parser.getTok().is(AsmToken::Percent)) {
668 if (parseRegister(Reg))
670 Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
674 // The only other type of operand is an immediate or address. As above,
675 // real address operands should have used a context-dependent parse routine,
676 // so we treat any plain expression as an immediate.
677 SMLoc StartLoc = Parser.getTok().getLoc();
678 unsigned Base, Index;
679 const MCExpr *Expr, *Length;
680 if (parseAddress(Base, Expr, Index, Length, SystemZMC::GR64Regs, ADDR64Reg))
684 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
685 if (Base || Index || Length)
686 Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
688 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
692 bool SystemZAsmParser::
693 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
694 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
695 MCStreamer &Out, unsigned &ErrorInfo,
696 bool MatchingInlineAsm) {
698 unsigned MatchResult;
700 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
702 switch (MatchResult) {
706 Out.EmitInstruction(Inst);
709 case Match_MissingFeature: {
710 assert(ErrorInfo && "Unknown missing feature!");
711 // Special case the error message for the very common case where only
712 // a single subtarget feature is missing
713 std::string Msg = "instruction requires:";
715 for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
716 if (ErrorInfo & Mask) {
718 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
722 return Error(IDLoc, Msg);
725 case Match_InvalidOperand: {
726 SMLoc ErrorLoc = IDLoc;
727 if (ErrorInfo != ~0U) {
728 if (ErrorInfo >= Operands.size())
729 return Error(IDLoc, "too few operands for instruction");
731 ErrorLoc = ((SystemZOperand*)Operands[ErrorInfo])->getStartLoc();
732 if (ErrorLoc == SMLoc())
735 return Error(ErrorLoc, "invalid operand for instruction");
738 case Match_MnemonicFail:
739 return Error(IDLoc, "invalid instruction");
742 llvm_unreachable("Unexpected match type");
745 SystemZAsmParser::OperandMatchResultTy SystemZAsmParser::
746 parseAccessReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
747 if (Parser.getTok().isNot(AsmToken::Percent))
748 return MatchOperand_NoMatch;
751 if (parseRegister(Reg, RegAccess, 0))
752 return MatchOperand_ParseFail;
754 Operands.push_back(SystemZOperand::createAccessReg(Reg.Num,
757 return MatchOperand_Success;
760 SystemZAsmParser::OperandMatchResultTy SystemZAsmParser::
761 parsePCRel(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
762 int64_t MinVal, int64_t MaxVal) {
763 MCContext &Ctx = getContext();
764 MCStreamer &Out = getStreamer();
766 SMLoc StartLoc = Parser.getTok().getLoc();
767 if (getParser().parseExpression(Expr))
768 return MatchOperand_NoMatch;
770 // For consistency with the GNU assembler, treat immediates as offsets
772 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) {
773 int64_t Value = CE->getValue();
774 if ((Value & 1) || Value < MinVal || Value > MaxVal) {
775 Error(StartLoc, "offset out of range");
776 return MatchOperand_ParseFail;
778 MCSymbol *Sym = Ctx.CreateTempSymbol();
780 const MCExpr *Base = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
782 Expr = Value == 0 ? Base : MCBinaryExpr::CreateAdd(Base, Expr, Ctx);
786 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
787 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
788 return MatchOperand_Success;
791 // Force static initialization.
792 extern "C" void LLVMInitializeSystemZAsmParser() {
793 RegisterMCAsmParser<SystemZAsmParser> X(TheSystemZTarget);