1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "llvm/ADT/STLExtras.h"
12 #include "llvm/MC/MCContext.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCStreamer.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCTargetAsmParser.h"
19 #include "llvm/Support/TargetRegistry.h"
23 // Return true if Expr is in the range [MinValue, MaxValue].
24 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
25 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
26 int64_t Value = CE->getValue();
27 return Value >= MinValue && Value <= MaxValue;
55 class SystemZOperand : public MCParsedAsmOperand {
69 SMLoc StartLoc, EndLoc;
71 // A string of length Length, starting at Data.
77 // LLVM register Num, which has kind Kind. In some ways it might be
78 // easier for this class to have a register bank (general, floating-point
79 // or access) and a raw register number (0-15). This would postpone the
80 // interpretation of the operand to the add*() methods and avoid the need
81 // for context-dependent parsing. However, we do things the current way
82 // because of the virtual getReg() method, which needs to distinguish
83 // between (say) %r0 used as a single register and %r0 used as a pair.
84 // Context-dependent parsing can also give us slightly better error
85 // messages when invalid pairs like %r1 are used.
91 // Base + Disp + Index, where Base and Index are LLVM registers or 0.
92 // MemKind says what type of memory this is and RegKind says what type
93 // the base register has (ADDR32Reg or ADDR64Reg). Length is the operand
94 // length for D(L,B)-style operands, otherwise it is null.
101 const MCExpr *Length;
104 // Imm is an immediate operand, and Sym is an optional TLS symbol
105 // for use with a __tls_get_offset marker relocation.
120 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
121 // Add as immediates when possible. Null MCExpr = 0.
123 Inst.addOperand(MCOperand::createImm(0));
124 else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
125 Inst.addOperand(MCOperand::createImm(CE->getValue()));
127 Inst.addOperand(MCOperand::createExpr(Expr));
131 SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
132 : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
134 // Create particular kinds of operand.
135 static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
137 return make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
139 static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
140 auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc);
141 Op->Token.Data = Str.data();
142 Op->Token.Length = Str.size();
145 static std::unique_ptr<SystemZOperand>
146 createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
147 auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
152 static std::unique_ptr<SystemZOperand>
153 createAccessReg(unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
154 auto Op = make_unique<SystemZOperand>(KindAccessReg, StartLoc, EndLoc);
158 static std::unique_ptr<SystemZOperand>
159 createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
160 auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
164 static std::unique_ptr<SystemZOperand>
165 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
166 const MCExpr *Disp, unsigned Index, const MCExpr *Length,
167 SMLoc StartLoc, SMLoc EndLoc) {
168 auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
169 Op->Mem.MemKind = MemKind;
170 Op->Mem.RegKind = RegKind;
172 Op->Mem.Index = Index;
174 Op->Mem.Length = Length;
177 static std::unique_ptr<SystemZOperand>
178 createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
179 SMLoc StartLoc, SMLoc EndLoc) {
180 auto Op = make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
181 Op->ImmTLS.Imm = Imm;
182 Op->ImmTLS.Sym = Sym;
187 bool isToken() const override {
188 return Kind == KindToken;
190 StringRef getToken() const {
191 assert(Kind == KindToken && "Not a token");
192 return StringRef(Token.Data, Token.Length);
195 // Register operands.
196 bool isReg() const override {
197 return Kind == KindReg;
199 bool isReg(RegisterKind RegKind) const {
200 return Kind == KindReg && Reg.Kind == RegKind;
202 unsigned getReg() const override {
203 assert(Kind == KindReg && "Not a register");
207 // Access register operands. Access registers aren't exposed to LLVM
209 bool isAccessReg() const {
210 return Kind == KindAccessReg;
213 // Immediate operands.
214 bool isImm() const override {
215 return Kind == KindImm;
217 bool isImm(int64_t MinValue, int64_t MaxValue) const {
218 return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
220 const MCExpr *getImm() const {
221 assert(Kind == KindImm && "Not an immediate");
225 // Immediate operands with optional TLS symbol.
226 bool isImmTLS() const {
227 return Kind == KindImmTLS;
231 bool isMem() const override {
232 return Kind == KindMem;
234 bool isMem(MemoryKind MemKind) const {
235 return (Kind == KindMem &&
236 (Mem.MemKind == MemKind ||
237 // A BDMem can be treated as a BDXMem in which the index
238 // register field is 0.
239 (Mem.MemKind == BDMem && MemKind == BDXMem)));
241 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
242 return isMem(MemKind) && Mem.RegKind == RegKind;
244 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
245 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
247 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
248 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
250 bool isMemDisp12Len8(RegisterKind RegKind) const {
251 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length, 1, 0x100);
253 void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
254 assert(N == 3 && "Invalid number of operands");
255 assert(isMem(BDVMem) && "Invalid operand type");
256 Inst.addOperand(MCOperand::createReg(Mem.Base));
257 addExpr(Inst, Mem.Disp);
258 Inst.addOperand(MCOperand::createReg(Mem.Index));
261 // Override MCParsedAsmOperand.
262 SMLoc getStartLoc() const override { return StartLoc; }
263 SMLoc getEndLoc() const override { return EndLoc; }
264 void print(raw_ostream &OS) const override;
266 // Used by the TableGen code to add particular types of operand
267 // to an instruction.
268 void addRegOperands(MCInst &Inst, unsigned N) const {
269 assert(N == 1 && "Invalid number of operands");
270 Inst.addOperand(MCOperand::createReg(getReg()));
272 void addAccessRegOperands(MCInst &Inst, unsigned N) const {
273 assert(N == 1 && "Invalid number of operands");
274 assert(Kind == KindAccessReg && "Invalid operand type");
275 Inst.addOperand(MCOperand::createImm(AccessReg));
277 void addImmOperands(MCInst &Inst, unsigned N) const {
278 assert(N == 1 && "Invalid number of operands");
279 addExpr(Inst, getImm());
281 void addBDAddrOperands(MCInst &Inst, unsigned N) const {
282 assert(N == 2 && "Invalid number of operands");
283 assert(isMem(BDMem) && "Invalid operand type");
284 Inst.addOperand(MCOperand::createReg(Mem.Base));
285 addExpr(Inst, Mem.Disp);
287 void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
288 assert(N == 3 && "Invalid number of operands");
289 assert(isMem(BDXMem) && "Invalid operand type");
290 Inst.addOperand(MCOperand::createReg(Mem.Base));
291 addExpr(Inst, Mem.Disp);
292 Inst.addOperand(MCOperand::createReg(Mem.Index));
294 void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
295 assert(N == 3 && "Invalid number of operands");
296 assert(isMem(BDLMem) && "Invalid operand type");
297 Inst.addOperand(MCOperand::createReg(Mem.Base));
298 addExpr(Inst, Mem.Disp);
299 addExpr(Inst, Mem.Length);
301 void addImmTLSOperands(MCInst &Inst, unsigned N) const {
302 assert(N == 2 && "Invalid number of operands");
303 assert(Kind == KindImmTLS && "Invalid operand type");
304 addExpr(Inst, ImmTLS.Imm);
306 addExpr(Inst, ImmTLS.Sym);
309 // Used by the TableGen code to check for particular operand types.
310 bool isGR32() const { return isReg(GR32Reg); }
311 bool isGRH32() const { return isReg(GRH32Reg); }
312 bool isGRX32() const { return false; }
313 bool isGR64() const { return isReg(GR64Reg); }
314 bool isGR128() const { return isReg(GR128Reg); }
315 bool isADDR32() const { return isReg(ADDR32Reg); }
316 bool isADDR64() const { return isReg(ADDR64Reg); }
317 bool isADDR128() const { return false; }
318 bool isFP32() const { return isReg(FP32Reg); }
319 bool isFP64() const { return isReg(FP64Reg); }
320 bool isFP128() const { return isReg(FP128Reg); }
321 bool isVR32() const { return isReg(VR32Reg); }
322 bool isVR64() const { return isReg(VR64Reg); }
323 bool isVF128() const { return false; }
324 bool isVR128() const { return isReg(VR128Reg); }
325 bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); }
326 bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); }
327 bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); }
328 bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, ADDR64Reg); }
329 bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); }
330 bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); }
331 bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
332 bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, ADDR64Reg); }
333 bool isU1Imm() const { return isImm(0, 1); }
334 bool isU2Imm() const { return isImm(0, 3); }
335 bool isU3Imm() const { return isImm(0, 7); }
336 bool isU4Imm() const { return isImm(0, 15); }
337 bool isU6Imm() const { return isImm(0, 63); }
338 bool isU8Imm() const { return isImm(0, 255); }
339 bool isS8Imm() const { return isImm(-128, 127); }
340 bool isU12Imm() const { return isImm(0, 4095); }
341 bool isU16Imm() const { return isImm(0, 65535); }
342 bool isS16Imm() const { return isImm(-32768, 32767); }
343 bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
344 bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
347 class SystemZAsmParser : public MCTargetAsmParser {
348 #define GET_ASSEMBLER_HEADER
349 #include "SystemZGenAsmMatcher.inc"
352 MCSubtargetInfo &STI;
363 SMLoc StartLoc, EndLoc;
366 bool parseRegister(Register &Reg);
368 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
369 bool IsAddress = false);
371 OperandMatchResultTy parseRegister(OperandVector &Operands,
372 RegisterGroup Group, const unsigned *Regs,
375 bool parseAddress(unsigned &Base, const MCExpr *&Disp,
376 unsigned &Index, bool &IsVector, const MCExpr *&Length,
377 const unsigned *Regs, RegisterKind RegKind);
379 OperandMatchResultTy parseAddress(OperandVector &Operands,
380 MemoryKind MemKind, const unsigned *Regs,
381 RegisterKind RegKind);
383 OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
384 int64_t MaxVal, bool AllowTLS);
386 bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
389 SystemZAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
390 const MCInstrInfo &MII,
391 const MCTargetOptions &Options)
392 : MCTargetAsmParser(Options), STI(sti), Parser(parser) {
393 MCAsmParserExtension::Initialize(Parser);
395 // Initialize the set of available features.
396 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
399 // Override MCTargetAsmParser.
400 bool ParseDirective(AsmToken DirectiveID) override;
401 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
402 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
403 SMLoc NameLoc, OperandVector &Operands) override;
404 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
405 OperandVector &Operands, MCStreamer &Out,
407 bool MatchingInlineAsm) override;
409 // Used by the TableGen code to parse particular operand types.
410 OperandMatchResultTy parseGR32(OperandVector &Operands) {
411 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
413 OperandMatchResultTy parseGRH32(OperandVector &Operands) {
414 return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
416 OperandMatchResultTy parseGRX32(OperandVector &Operands) {
417 llvm_unreachable("GRX32 should only be used for pseudo instructions");
419 OperandMatchResultTy parseGR64(OperandVector &Operands) {
420 return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
422 OperandMatchResultTy parseGR128(OperandVector &Operands) {
423 return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
425 OperandMatchResultTy parseADDR32(OperandVector &Operands) {
426 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
428 OperandMatchResultTy parseADDR64(OperandVector &Operands) {
429 return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
431 OperandMatchResultTy parseADDR128(OperandVector &Operands) {
432 llvm_unreachable("Shouldn't be used as an operand");
434 OperandMatchResultTy parseFP32(OperandVector &Operands) {
435 return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
437 OperandMatchResultTy parseFP64(OperandVector &Operands) {
438 return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
440 OperandMatchResultTy parseFP128(OperandVector &Operands) {
441 return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
443 OperandMatchResultTy parseVR32(OperandVector &Operands) {
444 return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg);
446 OperandMatchResultTy parseVR64(OperandVector &Operands) {
447 return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg);
449 OperandMatchResultTy parseVF128(OperandVector &Operands) {
450 llvm_unreachable("Shouldn't be used as an operand");
452 OperandMatchResultTy parseVR128(OperandVector &Operands) {
453 return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg);
455 OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
456 return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg);
458 OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
459 return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg);
461 OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
462 return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg);
464 OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
465 return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg);
467 OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
468 return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg);
470 OperandMatchResultTy parseAccessReg(OperandVector &Operands);
471 OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
472 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
474 OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
475 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
477 OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
478 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
480 OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
481 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
484 } // end anonymous namespace
486 #define GET_REGISTER_MATCHER
487 #define GET_SUBTARGET_FEATURE_NAME
488 #define GET_MATCHER_IMPLEMENTATION
489 #include "SystemZGenAsmMatcher.inc"
491 void SystemZOperand::print(raw_ostream &OS) const {
492 llvm_unreachable("Not implemented");
495 // Parse one register of the form %<prefix><number>.
496 bool SystemZAsmParser::parseRegister(Register &Reg) {
497 Reg.StartLoc = Parser.getTok().getLoc();
500 if (Parser.getTok().isNot(AsmToken::Percent))
501 return Error(Parser.getTok().getLoc(), "register expected");
504 // Expect a register name.
505 if (Parser.getTok().isNot(AsmToken::Identifier))
506 return Error(Reg.StartLoc, "invalid register");
508 // Check that there's a prefix.
509 StringRef Name = Parser.getTok().getString();
511 return Error(Reg.StartLoc, "invalid register");
512 char Prefix = Name[0];
514 // Treat the rest of the register name as a register number.
515 if (Name.substr(1).getAsInteger(10, Reg.Num))
516 return Error(Reg.StartLoc, "invalid register");
518 // Look for valid combinations of prefix and number.
519 if (Prefix == 'r' && Reg.Num < 16)
521 else if (Prefix == 'f' && Reg.Num < 16)
523 else if (Prefix == 'v' && Reg.Num < 32)
525 else if (Prefix == 'a' && Reg.Num < 16)
526 Reg.Group = RegAccess;
528 return Error(Reg.StartLoc, "invalid register");
530 Reg.EndLoc = Parser.getTok().getLoc();
535 // Parse a register of group Group. If Regs is nonnull, use it to map
536 // the raw register number to LLVM numbering, with zero entries
537 // indicating an invalid register. IsAddress says whether the
538 // register appears in an address context. Allow FP Group if expecting
539 // RegV Group, since the f-prefix yields the FP group even while used
540 // with vector instructions.
541 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
542 const unsigned *Regs, bool IsAddress) {
543 if (parseRegister(Reg))
545 if (Reg.Group != Group && !(Reg.Group == RegFP && Group == RegV))
546 return Error(Reg.StartLoc, "invalid operand for instruction");
547 if (Regs && Regs[Reg.Num] == 0)
548 return Error(Reg.StartLoc, "invalid register pair");
549 if (Reg.Num == 0 && IsAddress)
550 return Error(Reg.StartLoc, "%r0 used in an address");
552 Reg.Num = Regs[Reg.Num];
556 // Parse a register and add it to Operands. The other arguments are as above.
557 SystemZAsmParser::OperandMatchResultTy
558 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
559 const unsigned *Regs, RegisterKind Kind) {
560 if (Parser.getTok().isNot(AsmToken::Percent))
561 return MatchOperand_NoMatch;
564 bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
565 if (parseRegister(Reg, Group, Regs, IsAddress))
566 return MatchOperand_ParseFail;
568 Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
569 Reg.StartLoc, Reg.EndLoc));
570 return MatchOperand_Success;
573 // Parse a memory operand into Base, Disp, Index and Length.
574 // Regs maps asm register numbers to LLVM register numbers and RegKind
575 // says what kind of address register we're using (ADDR32Reg or ADDR64Reg).
576 bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp,
577 unsigned &Index, bool &IsVector,
578 const MCExpr *&Length, const unsigned *Regs,
579 RegisterKind RegKind) {
580 // Parse the displacement, which must always be present.
581 if (getParser().parseExpression(Disp))
584 // Parse the optional base and index.
589 if (getLexer().is(AsmToken::LParen)) {
592 if (getLexer().is(AsmToken::Percent)) {
593 // Parse the first register and decide whether it's a base or an index.
595 if (parseRegister(Reg))
597 if (Reg.Group == RegV) {
598 // A vector index register. The base register is optional.
600 Index = SystemZMC::VR128Regs[Reg.Num];
601 } else if (Reg.Group == RegGR) {
603 return Error(Reg.StartLoc, "%r0 used in an address");
604 // If the are two registers, the first one is the index and the
605 // second is the base.
606 if (getLexer().is(AsmToken::Comma))
607 Index = Regs[Reg.Num];
609 Base = Regs[Reg.Num];
611 return Error(Reg.StartLoc, "invalid address register");
614 if (getParser().parseExpression(Length))
618 // Check whether there's a second register. It's the base if so.
619 if (getLexer().is(AsmToken::Comma)) {
622 if (parseRegister(Reg, RegGR, Regs, RegKind))
627 // Consume the closing bracket.
628 if (getLexer().isNot(AsmToken::RParen))
629 return Error(Parser.getTok().getLoc(), "unexpected token in address");
635 // Parse a memory operand and add it to Operands. The other arguments
637 SystemZAsmParser::OperandMatchResultTy
638 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
639 const unsigned *Regs, RegisterKind RegKind) {
640 SMLoc StartLoc = Parser.getTok().getLoc();
641 unsigned Base, Index;
644 const MCExpr *Length;
645 if (parseAddress(Base, Disp, Index, IsVector, Length, Regs, RegKind))
646 return MatchOperand_ParseFail;
648 if (IsVector && MemKind != BDVMem) {
649 Error(StartLoc, "invalid use of vector addressing");
650 return MatchOperand_ParseFail;
653 if (!IsVector && MemKind == BDVMem) {
654 Error(StartLoc, "vector index required in address");
655 return MatchOperand_ParseFail;
658 if (Index && MemKind != BDXMem && MemKind != BDVMem) {
659 Error(StartLoc, "invalid use of indexed addressing");
660 return MatchOperand_ParseFail;
663 if (Length && MemKind != BDLMem) {
664 Error(StartLoc, "invalid use of length addressing");
665 return MatchOperand_ParseFail;
668 if (!Length && MemKind == BDLMem) {
669 Error(StartLoc, "missing length in address");
670 return MatchOperand_ParseFail;
674 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
675 Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
676 Index, Length, StartLoc,
678 return MatchOperand_Success;
681 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
685 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
688 if (parseRegister(Reg))
690 if (Reg.Group == RegGR)
691 RegNo = SystemZMC::GR64Regs[Reg.Num];
692 else if (Reg.Group == RegFP)
693 RegNo = SystemZMC::FP64Regs[Reg.Num];
694 else if (Reg.Group == RegV)
695 RegNo = SystemZMC::VR128Regs[Reg.Num];
697 // FIXME: Access registers aren't modelled as LLVM registers yet.
698 return Error(Reg.StartLoc, "invalid operand for instruction");
699 StartLoc = Reg.StartLoc;
704 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
705 StringRef Name, SMLoc NameLoc,
706 OperandVector &Operands) {
707 Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
709 // Read the remaining operands.
710 if (getLexer().isNot(AsmToken::EndOfStatement)) {
711 // Read the first operand.
712 if (parseOperand(Operands, Name)) {
713 Parser.eatToEndOfStatement();
717 // Read any subsequent operands.
718 while (getLexer().is(AsmToken::Comma)) {
720 if (parseOperand(Operands, Name)) {
721 Parser.eatToEndOfStatement();
725 if (getLexer().isNot(AsmToken::EndOfStatement)) {
726 SMLoc Loc = getLexer().getLoc();
727 Parser.eatToEndOfStatement();
728 return Error(Loc, "unexpected token in argument list");
732 // Consume the EndOfStatement.
737 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
738 StringRef Mnemonic) {
739 // Check if the current operand has a custom associated parser, if so, try to
740 // custom parse the operand, or fallback to the general approach.
741 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
742 if (ResTy == MatchOperand_Success)
745 // If there wasn't a custom match, try the generic matcher below. Otherwise,
746 // there was a match, but an error occurred, in which case, just return that
747 // the operand parsing failed.
748 if (ResTy == MatchOperand_ParseFail)
751 // Check for a register. All real register operands should have used
752 // a context-dependent parse routine, which gives the required register
753 // class. The code is here to mop up other cases, like those where
754 // the instruction isn't recognized.
755 if (Parser.getTok().is(AsmToken::Percent)) {
757 if (parseRegister(Reg))
759 Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
763 // The only other type of operand is an immediate or address. As above,
764 // real address operands should have used a context-dependent parse routine,
765 // so we treat any plain expression as an immediate.
766 SMLoc StartLoc = Parser.getTok().getLoc();
767 unsigned Base, Index;
769 const MCExpr *Expr, *Length;
770 if (parseAddress(Base, Expr, Index, IsVector, Length, SystemZMC::GR64Regs,
775 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
776 if (Base || Index || Length)
777 Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
779 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
783 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
784 OperandVector &Operands,
787 bool MatchingInlineAsm) {
789 unsigned MatchResult;
791 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
793 switch (MatchResult) {
796 Out.EmitInstruction(Inst, STI);
799 case Match_MissingFeature: {
800 assert(ErrorInfo && "Unknown missing feature!");
801 // Special case the error message for the very common case where only
802 // a single subtarget feature is missing
803 std::string Msg = "instruction requires:";
805 for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
806 if (ErrorInfo & Mask) {
808 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
812 return Error(IDLoc, Msg);
815 case Match_InvalidOperand: {
816 SMLoc ErrorLoc = IDLoc;
817 if (ErrorInfo != ~0ULL) {
818 if (ErrorInfo >= Operands.size())
819 return Error(IDLoc, "too few operands for instruction");
821 ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
822 if (ErrorLoc == SMLoc())
825 return Error(ErrorLoc, "invalid operand for instruction");
828 case Match_MnemonicFail:
829 return Error(IDLoc, "invalid instruction");
832 llvm_unreachable("Unexpected match type");
835 SystemZAsmParser::OperandMatchResultTy
836 SystemZAsmParser::parseAccessReg(OperandVector &Operands) {
837 if (Parser.getTok().isNot(AsmToken::Percent))
838 return MatchOperand_NoMatch;
841 if (parseRegister(Reg, RegAccess, nullptr))
842 return MatchOperand_ParseFail;
844 Operands.push_back(SystemZOperand::createAccessReg(Reg.Num,
847 return MatchOperand_Success;
850 SystemZAsmParser::OperandMatchResultTy
851 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
852 int64_t MaxVal, bool AllowTLS) {
853 MCContext &Ctx = getContext();
854 MCStreamer &Out = getStreamer();
856 SMLoc StartLoc = Parser.getTok().getLoc();
857 if (getParser().parseExpression(Expr))
858 return MatchOperand_NoMatch;
860 // For consistency with the GNU assembler, treat immediates as offsets
862 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
863 int64_t Value = CE->getValue();
864 if ((Value & 1) || Value < MinVal || Value > MaxVal) {
865 Error(StartLoc, "offset out of range");
866 return MatchOperand_ParseFail;
868 MCSymbol *Sym = Ctx.createTempSymbol();
870 const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
872 Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
875 // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
876 const MCExpr *Sym = nullptr;
877 if (AllowTLS && getLexer().is(AsmToken::Colon)) {
880 if (Parser.getTok().isNot(AsmToken::Identifier)) {
881 Error(Parser.getTok().getLoc(), "unexpected token");
882 return MatchOperand_ParseFail;
885 MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
886 StringRef Name = Parser.getTok().getString();
887 if (Name == "tls_gdcall")
888 Kind = MCSymbolRefExpr::VK_TLSGD;
889 else if (Name == "tls_ldcall")
890 Kind = MCSymbolRefExpr::VK_TLSLDM;
892 Error(Parser.getTok().getLoc(), "unknown TLS tag");
893 return MatchOperand_ParseFail;
897 if (Parser.getTok().isNot(AsmToken::Colon)) {
898 Error(Parser.getTok().getLoc(), "unexpected token");
899 return MatchOperand_ParseFail;
903 if (Parser.getTok().isNot(AsmToken::Identifier)) {
904 Error(Parser.getTok().getLoc(), "unexpected token");
905 return MatchOperand_ParseFail;
908 StringRef Identifier = Parser.getTok().getString();
909 Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
915 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
918 Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
921 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
923 return MatchOperand_Success;
926 // Force static initialization.
927 extern "C" void LLVMInitializeSystemZAsmParser() {
928 RegisterMCAsmParser<SystemZAsmParser> X(TheSystemZTarget);