1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "llvm/MC/MCExpr.h"
12 #include "llvm/MC/MCInst.h"
13 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
14 #include "llvm/MC/MCStreamer.h"
15 #include "llvm/MC/MCSubtargetInfo.h"
16 #include "llvm/MC/MCTargetAsmParser.h"
17 #include "llvm/Support/TargetRegistry.h"
21 // Return true if Expr is in the range [MinValue, MaxValue].
22 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
23 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) {
24 int64_t Value = CE->getValue();
25 return Value >= MinValue && Value <= MaxValue;
31 class SystemZOperand : public MCParsedAsmOperand {
54 SMLoc StartLoc, EndLoc;
56 // A string of length Length, starting at Data.
62 // LLVM register Num, which has kind Kind.
68 // Base + Disp + Index, where Base and Index are LLVM registers or 0.
69 // RegKind says what type the registers have (ADDR32Reg or ADDR64Reg).
86 SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
87 : Kind(kind), StartLoc(startLoc), EndLoc(endLoc)
90 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
91 // Add as immediates when possible. Null MCExpr = 0.
93 Inst.addOperand(MCOperand::CreateImm(0));
94 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
95 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
97 Inst.addOperand(MCOperand::CreateExpr(Expr));
101 // Create particular kinds of operand.
102 static SystemZOperand *createToken(StringRef Str, SMLoc Loc) {
103 SystemZOperand *Op = new SystemZOperand(KindToken, Loc, Loc);
104 Op->Token.Data = Str.data();
105 Op->Token.Length = Str.size();
108 static SystemZOperand *createReg(RegisterKind Kind, unsigned Num,
109 SMLoc StartLoc, SMLoc EndLoc) {
110 SystemZOperand *Op = new SystemZOperand(KindReg, StartLoc, EndLoc);
115 static SystemZOperand *createAccessReg(unsigned Num, SMLoc StartLoc,
117 SystemZOperand *Op = new SystemZOperand(KindAccessReg, StartLoc, EndLoc);
121 static SystemZOperand *createImm(const MCExpr *Expr, SMLoc StartLoc,
123 SystemZOperand *Op = new SystemZOperand(KindImm, StartLoc, EndLoc);
127 static SystemZOperand *createMem(RegisterKind RegKind, unsigned Base,
128 const MCExpr *Disp, unsigned Index,
129 SMLoc StartLoc, SMLoc EndLoc) {
130 SystemZOperand *Op = new SystemZOperand(KindMem, StartLoc, EndLoc);
131 Op->Mem.RegKind = RegKind;
133 Op->Mem.Index = Index;
139 virtual bool isToken() const LLVM_OVERRIDE {
140 return Kind == KindToken;
142 StringRef getToken() const {
143 assert(Kind == KindToken && "Not a token");
144 return StringRef(Token.Data, Token.Length);
147 // Register operands.
148 virtual bool isReg() const LLVM_OVERRIDE {
149 return Kind == KindReg;
151 bool isReg(RegisterKind RegKind) const {
152 return Kind == KindReg && Reg.Kind == RegKind;
154 virtual unsigned getReg() const LLVM_OVERRIDE {
155 assert(Kind == KindReg && "Not a register");
159 // Access register operands. Access registers aren't exposed to LLVM
161 bool isAccessReg() const {
162 return Kind == KindAccessReg;
165 // Immediate operands.
166 virtual bool isImm() const LLVM_OVERRIDE {
167 return Kind == KindImm;
169 bool isImm(int64_t MinValue, int64_t MaxValue) const {
170 return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
172 const MCExpr *getImm() const {
173 assert(Kind == KindImm && "Not an immediate");
178 virtual bool isMem() const LLVM_OVERRIDE {
179 return Kind == KindMem;
181 bool isMem(RegisterKind RegKind, bool HasIndex) const {
182 return (Kind == KindMem &&
183 Mem.RegKind == RegKind &&
184 (HasIndex || !Mem.Index));
186 bool isMemDisp12(RegisterKind RegKind, bool HasIndex) const {
187 return isMem(RegKind, HasIndex) && inRange(Mem.Disp, 0, 0xfff);
189 bool isMemDisp20(RegisterKind RegKind, bool HasIndex) const {
190 return isMem(RegKind, HasIndex) && inRange(Mem.Disp, -524288, 524287);
193 // Override MCParsedAsmOperand.
194 virtual SMLoc getStartLoc() const LLVM_OVERRIDE { return StartLoc; }
195 virtual SMLoc getEndLoc() const LLVM_OVERRIDE { return EndLoc; }
196 virtual void print(raw_ostream &OS) const LLVM_OVERRIDE;
198 // Used by the TableGen code to add particular types of operand
199 // to an instruction.
200 void addRegOperands(MCInst &Inst, unsigned N) const {
201 assert(N == 1 && "Invalid number of operands");
202 Inst.addOperand(MCOperand::CreateReg(getReg()));
204 void addAccessRegOperands(MCInst &Inst, unsigned N) const {
205 assert(N == 1 && "Invalid number of operands");
206 assert(Kind == KindAccessReg && "Invalid operand type");
207 Inst.addOperand(MCOperand::CreateImm(AccessReg));
209 void addImmOperands(MCInst &Inst, unsigned N) const {
210 assert(N == 1 && "Invalid number of operands");
211 addExpr(Inst, getImm());
213 void addBDAddrOperands(MCInst &Inst, unsigned N) const {
214 assert(N == 2 && "Invalid number of operands");
215 assert(Kind == KindMem && Mem.Index == 0 && "Invalid operand type");
216 Inst.addOperand(MCOperand::CreateReg(Mem.Base));
217 addExpr(Inst, Mem.Disp);
219 void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
220 assert(N == 3 && "Invalid number of operands");
221 assert(Kind == KindMem && "Invalid operand type");
222 Inst.addOperand(MCOperand::CreateReg(Mem.Base));
223 addExpr(Inst, Mem.Disp);
224 Inst.addOperand(MCOperand::CreateReg(Mem.Index));
227 // Used by the TableGen code to check for particular operand types.
228 bool isGR32() const { return isReg(GR32Reg); }
229 bool isGR64() const { return isReg(GR64Reg); }
230 bool isGR128() const { return isReg(GR128Reg); }
231 bool isADDR32() const { return isReg(ADDR32Reg); }
232 bool isADDR64() const { return isReg(ADDR64Reg); }
233 bool isADDR128() const { return false; }
234 bool isFP32() const { return isReg(FP32Reg); }
235 bool isFP64() const { return isReg(FP64Reg); }
236 bool isFP128() const { return isReg(FP128Reg); }
237 bool isBDAddr32Disp12() const { return isMemDisp12(ADDR32Reg, false); }
238 bool isBDAddr32Disp20() const { return isMemDisp20(ADDR32Reg, false); }
239 bool isBDAddr64Disp12() const { return isMemDisp12(ADDR64Reg, false); }
240 bool isBDAddr64Disp20() const { return isMemDisp20(ADDR64Reg, false); }
241 bool isBDXAddr64Disp12() const { return isMemDisp12(ADDR64Reg, true); }
242 bool isBDXAddr64Disp20() const { return isMemDisp20(ADDR64Reg, true); }
243 bool isU4Imm() const { return isImm(0, 15); }
244 bool isU6Imm() const { return isImm(0, 63); }
245 bool isU8Imm() const { return isImm(0, 255); }
246 bool isS8Imm() const { return isImm(-128, 127); }
247 bool isU16Imm() const { return isImm(0, 65535); }
248 bool isS16Imm() const { return isImm(-32768, 32767); }
249 bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
250 bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
253 class SystemZAsmParser : public MCTargetAsmParser {
254 #define GET_ASSEMBLER_HEADER
255 #include "SystemZGenAsmMatcher.inc"
258 MCSubtargetInfo &STI;
263 SMLoc StartLoc, EndLoc;
266 bool parseRegister(Register &Reg);
269 parseRegister(Register &Reg, char Prefix, const unsigned *Regs,
270 bool IsAddress = false);
273 parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
274 char Prefix, const unsigned *Regs,
275 SystemZOperand::RegisterKind Kind,
276 bool IsAddress = false);
279 parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
280 const unsigned *Regs, SystemZOperand::RegisterKind RegKind,
283 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
287 SystemZAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
288 : MCTargetAsmParser(), STI(sti), Parser(parser) {
289 MCAsmParserExtension::Initialize(Parser);
291 // Initialize the set of available features.
292 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
295 // Override MCTargetAsmParser.
296 virtual bool ParseDirective(AsmToken DirectiveID) LLVM_OVERRIDE;
297 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
298 SMLoc &EndLoc) LLVM_OVERRIDE;
299 virtual bool ParseInstruction(ParseInstructionInfo &Info,
300 StringRef Name, SMLoc NameLoc,
301 SmallVectorImpl<MCParsedAsmOperand*> &Operands)
304 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
305 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
306 MCStreamer &Out, unsigned &ErrorInfo,
307 bool MatchingInlineAsm) LLVM_OVERRIDE;
309 // Used by the TableGen code to parse particular operand types.
311 parseGR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
312 return parseRegister(Operands, 'r', SystemZMC::GR32Regs,
313 SystemZOperand::GR32Reg);
316 parseGR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
317 return parseRegister(Operands, 'r', SystemZMC::GR64Regs,
318 SystemZOperand::GR64Reg);
321 parseGR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
322 return parseRegister(Operands, 'r', SystemZMC::GR128Regs,
323 SystemZOperand::GR128Reg);
326 parseADDR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
327 return parseRegister(Operands, 'r', SystemZMC::GR32Regs,
328 SystemZOperand::ADDR32Reg, true);
331 parseADDR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
332 return parseRegister(Operands, 'r', SystemZMC::GR64Regs,
333 SystemZOperand::ADDR64Reg, true);
336 parseADDR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
337 llvm_unreachable("Shouldn't be used as an operand");
340 parseFP32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
341 return parseRegister(Operands, 'f', SystemZMC::FP32Regs,
342 SystemZOperand::FP32Reg);
345 parseFP64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
346 return parseRegister(Operands, 'f', SystemZMC::FP64Regs,
347 SystemZOperand::FP64Reg);
350 parseFP128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
351 return parseRegister(Operands, 'f', SystemZMC::FP128Regs,
352 SystemZOperand::FP128Reg);
355 parseBDAddr32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
356 return parseAddress(Operands, SystemZMC::GR32Regs,
357 SystemZOperand::ADDR32Reg, false);
360 parseBDAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
361 return parseAddress(Operands, SystemZMC::GR64Regs,
362 SystemZOperand::ADDR64Reg, false);
365 parseBDXAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
366 return parseAddress(Operands, SystemZMC::GR64Regs,
367 SystemZOperand::ADDR64Reg, true);
370 parseAccessReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
374 #define GET_REGISTER_MATCHER
375 #define GET_SUBTARGET_FEATURE_NAME
376 #define GET_MATCHER_IMPLEMENTATION
377 #include "SystemZGenAsmMatcher.inc"
379 void SystemZOperand::print(raw_ostream &OS) const {
380 llvm_unreachable("Not implemented");
383 // Parse one register of the form %<prefix><number>.
384 bool SystemZAsmParser::parseRegister(Register &Reg) {
385 Reg.StartLoc = Parser.getTok().getLoc();
388 if (Parser.getTok().isNot(AsmToken::Percent))
392 // Expect a register name.
393 if (Parser.getTok().isNot(AsmToken::Identifier))
397 StringRef Name = Parser.getTok().getString();
400 Reg.Prefix = Name[0];
402 // Treat the rest of the register name as a register number.
403 if (Name.substr(1).getAsInteger(10, Reg.Number))
406 Reg.EndLoc = Parser.getTok().getLoc();
411 // Parse a register with prefix Prefix and convert it to LLVM numbering.
412 // Regs maps asm register numbers to LLVM register numbers, with zero
413 // entries indicating an invalid register. IsAddress says whether the
414 // register appears in an address context.
415 SystemZAsmParser::OperandMatchResultTy
416 SystemZAsmParser::parseRegister(Register &Reg, char Prefix,
417 const unsigned *Regs, bool IsAddress) {
418 if (parseRegister(Reg))
419 return MatchOperand_NoMatch;
420 if (Reg.Prefix != Prefix || Reg.Number > 15 || Regs[Reg.Number] == 0) {
421 Error(Reg.StartLoc, "invalid register");
422 return MatchOperand_ParseFail;
424 if (Reg.Number == 0 && IsAddress) {
425 Error(Reg.StartLoc, "%r0 used in an address");
426 return MatchOperand_ParseFail;
428 Reg.Number = Regs[Reg.Number];
429 return MatchOperand_Success;
432 // Parse a register and add it to Operands. Prefix is 'r' for GPRs,
433 // 'f' for FPRs, etc. Regs maps asm register numbers to LLVM register numbers,
434 // with zero entries indicating an invalid register. Kind is the type of
435 // register represented by Regs and IsAddress says whether the register is
436 // being parsed in an address context, meaning that %r0 evaluates as 0.
437 SystemZAsmParser::OperandMatchResultTy
438 SystemZAsmParser::parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
439 char Prefix, const unsigned *Regs,
440 SystemZOperand::RegisterKind Kind,
443 OperandMatchResultTy Result = parseRegister(Reg, Prefix, Regs, IsAddress);
444 if (Result == MatchOperand_Success)
445 Operands.push_back(SystemZOperand::createReg(Kind, Reg.Number,
446 Reg.StartLoc, Reg.EndLoc));
450 // Parse a memory operand and add it to Operands. Regs maps asm register
451 // numbers to LLVM address registers and RegKind says what kind of address
452 // register we're using (ADDR32Reg or ADDR64Reg). HasIndex says whether
453 // the address allows index registers.
454 SystemZAsmParser::OperandMatchResultTy
455 SystemZAsmParser::parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
456 const unsigned *Regs,
457 SystemZOperand::RegisterKind RegKind,
459 SMLoc StartLoc = Parser.getTok().getLoc();
461 // Parse the displacement, which must always be present.
463 if (getParser().parseExpression(Disp))
464 return MatchOperand_NoMatch;
466 // Parse the optional base and index.
469 if (getLexer().is(AsmToken::LParen)) {
472 // Parse the first register.
474 OperandMatchResultTy Result = parseRegister(Reg, 'r', SystemZMC::GR64Regs,
476 if (Result != MatchOperand_Success)
479 // Check whether there's a second register. If so, the one that we
480 // just parsed was the index.
481 if (getLexer().is(AsmToken::Comma)) {
485 Error(Reg.StartLoc, "invalid use of indexed addressing");
486 return MatchOperand_ParseFail;
490 Result = parseRegister(Reg, 'r', SystemZMC::GR64Regs, true);
491 if (Result != MatchOperand_Success)
496 // Consume the closing bracket.
497 if (getLexer().isNot(AsmToken::RParen))
498 return MatchOperand_NoMatch;
503 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
504 Operands.push_back(SystemZOperand::createMem(RegKind, Base, Disp, Index,
506 return MatchOperand_Success;
509 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
513 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
516 if (parseRegister(Reg))
517 return Error(Reg.StartLoc, "register expected");
518 if (Reg.Prefix == 'r' && Reg.Number < 16)
519 RegNo = SystemZMC::GR64Regs[Reg.Number];
520 else if (Reg.Prefix == 'f' && Reg.Number < 16)
521 RegNo = SystemZMC::FP64Regs[Reg.Number];
523 return Error(Reg.StartLoc, "invalid register");
524 StartLoc = Reg.StartLoc;
529 bool SystemZAsmParser::
530 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
531 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
532 Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
534 // Read the remaining operands.
535 if (getLexer().isNot(AsmToken::EndOfStatement)) {
536 // Read the first operand.
537 if (parseOperand(Operands, Name)) {
538 Parser.eatToEndOfStatement();
542 // Read any subsequent operands.
543 while (getLexer().is(AsmToken::Comma)) {
545 if (parseOperand(Operands, Name)) {
546 Parser.eatToEndOfStatement();
550 if (getLexer().isNot(AsmToken::EndOfStatement)) {
551 SMLoc Loc = getLexer().getLoc();
552 Parser.eatToEndOfStatement();
553 return Error(Loc, "unexpected token in argument list");
557 // Consume the EndOfStatement.
562 bool SystemZAsmParser::
563 parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
564 StringRef Mnemonic) {
565 // Check if the current operand has a custom associated parser, if so, try to
566 // custom parse the operand, or fallback to the general approach.
567 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
568 if (ResTy == MatchOperand_Success)
571 // If there wasn't a custom match, try the generic matcher below. Otherwise,
572 // there was a match, but an error occurred, in which case, just return that
573 // the operand parsing failed.
574 if (ResTy == MatchOperand_ParseFail)
577 // The only other type of operand is an immediate.
579 SMLoc StartLoc = Parser.getTok().getLoc();
580 if (getParser().parseExpression(Expr))
584 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
585 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
589 bool SystemZAsmParser::
590 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
591 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
592 MCStreamer &Out, unsigned &ErrorInfo,
593 bool MatchingInlineAsm) {
595 unsigned MatchResult;
597 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
599 switch (MatchResult) {
603 Out.EmitInstruction(Inst);
606 case Match_MissingFeature: {
607 assert(ErrorInfo && "Unknown missing feature!");
608 // Special case the error message for the very common case where only
609 // a single subtarget feature is missing
610 std::string Msg = "instruction requires:";
612 for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
613 if (ErrorInfo & Mask) {
615 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
619 return Error(IDLoc, Msg);
622 case Match_InvalidOperand: {
623 SMLoc ErrorLoc = IDLoc;
624 if (ErrorInfo != ~0U) {
625 if (ErrorInfo >= Operands.size())
626 return Error(IDLoc, "too few operands for instruction");
628 ErrorLoc = ((SystemZOperand*)Operands[ErrorInfo])->getStartLoc();
629 if (ErrorLoc == SMLoc())
632 return Error(ErrorLoc, "invalid operand for instruction");
635 case Match_MnemonicFail:
636 return Error(IDLoc, "invalid instruction");
639 llvm_unreachable("Unexpected match type");
642 SystemZAsmParser::OperandMatchResultTy SystemZAsmParser::
643 parseAccessReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
645 if (parseRegister(Reg))
646 return MatchOperand_NoMatch;
647 if (Reg.Prefix != 'a' || Reg.Number > 15) {
648 Error(Reg.StartLoc, "invalid register");
649 return MatchOperand_ParseFail;
651 Operands.push_back(SystemZOperand::createAccessReg(Reg.Number,
652 Reg.StartLoc, Reg.EndLoc));
653 return MatchOperand_Success;
656 // Force static initialization.
657 extern "C" void LLVMInitializeSystemZAsmParser() {
658 RegisterMCAsmParser<SystemZAsmParser> X(TheSystemZTarget);