1 //===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
11 #define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
13 #include "llvm/Support/DataTypes.h"
23 class MCSubtargetInfo;
26 class raw_pwrite_stream;
29 extern Target TheSystemZTarget;
32 // How many bytes are in the ABI-defined, caller-allocated part of
34 const int64_t CallFrameSize = 160;
36 // The offset of the DWARF CFA from the incoming stack pointer.
37 const int64_t CFAOffsetFromInitialSP = CallFrameSize;
39 // Maps of asm register numbers to LLVM register numbers, with 0 indicating
40 // an invalid register. In principle we could use 32-bit and 64-bit register
41 // classes directly, provided that we relegated the GPR allocation order
42 // in SystemZRegisterInfo.td to an AltOrder and left the default order
43 // as %r0-%r15. It seems better to provide the same interface for
44 // all classes though.
45 extern const unsigned GR32Regs[16];
46 extern const unsigned GRH32Regs[16];
47 extern const unsigned GR64Regs[16];
48 extern const unsigned GR128Regs[16];
49 extern const unsigned FP32Regs[16];
50 extern const unsigned FP64Regs[16];
51 extern const unsigned FP128Regs[16];
52 extern const unsigned VR32Regs[32];
53 extern const unsigned VR64Regs[32];
54 extern const unsigned VR128Regs[32];
56 // Return the 0-based number of the first architectural register that
57 // contains the given LLVM register. E.g. R1D -> 1.
58 unsigned getFirstReg(unsigned Reg);
60 // Return the given register as a GR64.
61 inline unsigned getRegAsGR64(unsigned Reg) {
62 return GR64Regs[getFirstReg(Reg)];
65 // Return the given register as a low GR32.
66 inline unsigned getRegAsGR32(unsigned Reg) {
67 return GR32Regs[getFirstReg(Reg)];
70 // Return the given register as a high GR32.
71 inline unsigned getRegAsGRH32(unsigned Reg) {
72 return GRH32Regs[getFirstReg(Reg)];
75 // Return the given register as a VR128.
76 inline unsigned getRegAsVR128(unsigned Reg) {
77 return VR128Regs[getFirstReg(Reg)];
79 } // end namespace SystemZMC
81 MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
82 const MCRegisterInfo &MRI,
85 MCAsmBackend *createSystemZMCAsmBackend(const Target &T,
86 const MCRegisterInfo &MRI,
87 StringRef TT, StringRef CPU);
89 MCObjectWriter *createSystemZObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI);
90 } // end namespace llvm
92 // Defines symbolic names for SystemZ registers.
93 // This defines a mapping from register name to register number.
94 #define GET_REGINFO_ENUM
95 #include "SystemZGenRegisterInfo.inc"
97 // Defines symbolic names for the SystemZ instructions.
98 #define GET_INSTRINFO_ENUM
99 #include "SystemZGenInstrInfo.inc"
101 #define GET_SUBTARGETINFO_ENUM
102 #include "SystemZGenSubtargetInfo.inc"