1 //===---------------------------------------------------------------------===//
2 // Random notes about and ideas for the SystemZ backend.
3 //===---------------------------------------------------------------------===//
5 The initial backend is deliberately restricted to z10. We should add support
6 for later architectures at some point.
10 SystemZDAGToDAGISel::SelectInlineAsmMemoryOperand() is passed "m" for all
11 inline asm memory constraints; it doesn't get to see the original constraint.
12 This means that it must conservatively treat all inline asm constraints
13 as the most restricted type, "R".
17 If an inline asm ties an i32 "r" result to an i64 input, the input
18 will be treated as an i32, leaving the upper bits uninitialised.
21 define void @f4(i32 *%dst) {
22 %val = call i32 asm "blah $0", "=r,0" (i64 103)
23 store i32 %val, i32 *%dst
27 from CodeGen/SystemZ/asm-09.ll will use LHI rather than LGHI.
28 to load 103. This seems to be a general target-independent problem.
32 The tuning of the choice between LOAD ADDRESS (LA) and addition in
33 SystemZISelDAGToDAG.cpp is suspect. It should be tweaked based on
34 performance measurements.
38 There is no scheduling support.
42 We don't use the BRANCH ON INDEX instructions.
46 We might want to use BRANCH ON CONDITION for conditional indirect calls
47 and conditional returns.
51 We don't use the TEST DATA CLASS instructions.
55 We only use MVC, XC and CLC for constant-length block operations.
56 We could extend them to variable-length operations too,
57 using EXECUTE RELATIVE LONG.
59 MVCIN, MVCLE and CLCLE may be worthwhile too.
63 We don't use CUSE or the TRANSLATE family of instructions for string
64 operations. The TRANSLATE ones are probably more difficult to exploit.
68 We don't take full advantage of builtins like fabsl because the calling
69 conventions require f128s to be returned by invisible reference.
73 ADD LOGICAL WITH SIGNED IMMEDIATE could be useful when we need to
74 produce a carry. SUBTRACT LOGICAL IMMEDIATE could be useful when we
75 need to produce a borrow. (Note that there are no memory forms of
76 ADD LOGICAL WITH CARRY and SUBTRACT LOGICAL WITH BORROW, so the high
77 part of 128-bit memory operations would probably need to be done
82 We don't use the halfword forms of LOAD REVERSED and STORE REVERSED
87 We don't use ICM or STCM.
91 DAGCombiner doesn't yet fold truncations of extended loads. Functions like:
93 unsigned long f (unsigned long x, unsigned short *y)
95 return (x << 32) | *y;
105 but truncating the load would give:
115 define i64 @f1(i64 %a) {
120 ought to be implemented as:
126 but two-address optimisations reverse the order of the AND and force:
133 CodeGen/SystemZ/and-04.ll has several examples of this.
137 Out-of-range displacements are usually handled by loading the full
138 address into a register. In many cases it would be better to create
139 an anchor point instead. E.g. for:
141 define void @f4a(i128 *%aptr, i64 %base) {
142 %addr = add i64 %base, 524288
143 %bptr = inttoptr i64 %addr to i128 *
144 %a = load volatile i128 *%aptr
145 %b = load i128 *%bptr
146 %add = add i128 %a, %b
147 store i128 %add, i128 *%aptr
151 (from CodeGen/SystemZ/int-add-08.ll) we load %base+524288 and %base+524296
152 into separate registers, rather than using %base+524288 as a base for both.
156 Dynamic stack allocations round the size to 8 bytes and then allocate
157 that rounded amount. It would be simpler to subtract the unrounded
158 size from the copy of the stack pointer and then align the result.
159 See CodeGen/SystemZ/alloca-01.ll for an example.
163 If needed, we can support 16-byte atomics using LPQ, STPQ and CSDG.
167 We might want to model all access registers and use them to spill